TWI893593B - Electronic device and 3d chip package structure thereof - Google Patents

Abstract

The present application is related to an electronic device that comprises a plurality of circuit units and a compensation circuit. The plurality of circuit units are connected in parallel to each other and are electrically connected to a power terminal to receive a power voltage. The compensation circuit is electrically connected to the plurality of circuit units and outputs a compensation voltage to the electrically connected circuit units. At least one of the plurality of circuit units is located away from the power terminal.

Description

Electronic device and 3D chip packaging structure thereof

This application relates to a semiconductor device and a semiconductor package structure, particularly an electronic device and a 3D chip package structure thereof.

As users demand more and more data and computing power from electronic products, and to meet the need for thinner, lighter, and shorter electronic products, semiconductor devices continue to develop towards smaller size, lower power consumption, and higher bandwidth.

However, as data volumes and computing power increase, the number of electronic components and circuits required within semiconductor devices has also increased accordingly, significantly increasing the number of pins required. To meet the demand for smaller semiconductor devices, the number of pins must be minimized. This reduction in pin count can lead to unstable power supply to the semiconductor device's internal circuitry.

Therefore, how to provide a semiconductor device that can stably supply power is one of the problems that need to be solved urgently in this field.

To solve the above technical problems, this application proposes an electronic device and a 3D chip packaging structure thereof, which can compensate the power voltage inside the electronic device, allowing the internal circuit of the electronic device to operate normally under a stable power voltage, thereby achieving the purpose of enabling the integrated circuit chip to provide a stable power voltage.

To achieve the aforementioned objectives, this application provides an electronic device comprising a plurality of circuit units and a compensation circuit. The plurality of circuit units are connected in parallel and electrically connected to a power terminal to receive a power voltage. The compensation circuit is electrically connected to the circuit units and outputs a compensation voltage to the electrically connected circuit units, with at least one of the circuit units being remote from the power terminal.

To achieve the above-mentioned objectives, the present application proposes a 3D chip packaging structure comprising the aforementioned electronic device. The electronic device comprises a memory crystal layer and a connection layer. The memory crystal layer comprises at least one memory partition. The connection layer is located on one side of the memory crystal layer and is configured with at least one connection pad. The connection layer corresponding to the at least one memory partition defines at least one connection clear space area and at least one connection area, the at least one connection clear space area being adjacent to the at least one connection area, and the area of the at least one connection clear space area being equal to or greater than the area of the at least one connection area. The at least one connection pad is only configured in the at least one connection area.

Based on the above, the electronic device and 3D chip package structure embodiment of the present application includes a compensation circuit, and the compensation circuit is used to output a compensation voltage to the circuit unit to compensate for the power voltage that has declined due to being far away from the power terminal, so that the circuit unit can operate normally with sufficient power voltage, thereby achieving the purpose of providing a stable power voltage to the integrated circuit chip.

Please refer to Figure 1, which is a schematic diagram of an electronic device embodiment of the present application. In this embodiment, the electronic device is a memory device, and the circuit unit is a storage unit. The memory device 10 includes a memory crystal layer 11 and a connection layer 12. The connection layer 12 is located on one side of the memory crystal layer 11. The memory crystal layer 11 includes at least one memory partition 111 and at least one compensation circuit 112. The at least one memory partition 111 is electrically connected to the at least one compensation circuit 112. In this embodiment, a plurality of memory partitions 111 (111a, 111b) are used as an example, and the present application is not limited thereto.

The connection layer 12 is used to configure at least one connection pad 121. At least one connection pad 121 is electrically connected to the corresponding memory partition 111, and at least one connection pad 121 is in contact with the corresponding conductive pillar 20. In this embodiment, a plurality of connection pads 121 are used as an example, but this application is not limited thereto.

Furthermore, the connection layer 12 defines at least one connection clear area 13 and at least one connection area 14. The at least one connection clear area 13 is disposed adjacent to the at least one connection area 14. In this embodiment, the at least one connection pad 121 is disposed only in the at least one connection area 14. That is, the connection pads 121 are not disposed in the at least one connection clear area 13.

In one embodiment, at least one connection pad 121 can be implemented by a HBL and a HBC.

In this embodiment, the memory device 10 is implemented as a high-bandwidth memory (HBM).

Furthermore, at least one conductive pillar 20 is only configured corresponding to at least one connection area 14. That is, at least one conductive pillar 20 is not configured in at least one connection clear area 13. As shown in Figure 1, a plurality of conductive pillars 20 are only configured corresponding to the connection area 14 and are arranged on the left and right sides corresponding to the memory device 10 in the figure. In this embodiment, each conductive pillar 20 is in contact with and connected to the connection pad 121 configured corresponding to the at least one connection area 14. Therefore, in this embodiment, the number of at least one conductive pillar 20 corresponds to the number of at least one connection pad 121. That is, the number of at least one conductive pillar 20 is the same as the number of at least one connection pad 121. In this embodiment, a plurality of conductive pillars 20 are electrically connected to an external circuit to individually receive power voltage, compensated power voltage, or ground from the external circuit. In one embodiment, at least one conductive pillar 20 can be implemented by multiple metal layers, and this application is not limited thereto.

The architecture of each memory partition 111 is further described using memory partition 111a as an example. Memory partition 111a includes a plurality of storage cells 1111 connected in parallel. One end of each storage cell 1111 is electrically connected to a corresponding power terminal VDD1 to receive a power voltage, while the other end of each storage cell 1111 is electrically connected to a corresponding ground terminal GND1 for grounding. Power terminal VDD1 is electrically connected to a corresponding connection pad 121 (such as connection pad 121 in connection area 14 on the left side of FIG. 1 ) to receive a power voltage from an external circuit. The ground terminal GND1 is electrically connected to a corresponding other connection pad 121 (such as the other connection pad 121 in the left connection area 14 in FIG. 1 ) and is grounded through the corresponding connection pad 121. The architecture of the memory partition 111b is the same as that of the memory partition 111a, and the power terminal VDD2 is electrically connected to a corresponding connection pad 121 (such as the other connection pad 121 in the right connection area 14 in FIG. 1 ) to receive power voltage from an external circuit. The ground terminal GND2 is electrically connected to a corresponding other connection pad 121 (such as the other connection pad 121 in the right connection area 14 in FIG. 1 ) and is grounded through the corresponding connection pad 121. Therefore, no further description is given here.

Furthermore, one end of compensation circuit 112a is electrically connected to a compensation power supply terminal VDDa1, and the other end of compensation circuit 112a is electrically connected to one end of storage cell 1111 in memory partition 111a. Compensation circuit 112a outputs a compensation voltage to one end of the electrically connected storage cell 1111. Compensation power supply terminal VDDa1 is electrically connected to a corresponding connection pad 121 (e.g., another connection pad 121 in the left connection area 14 in FIG. 1 ) for receiving a compensation power supply voltage from an external circuit. Similarly, one end of compensation circuit 112b is electrically connected to a compensation power supply terminal VDDa2, and the other end of compensation circuit 112b is electrically connected to one end of storage cell 1111 in memory partition 111b, thereby outputting a compensation voltage to the electrically connected storage cell 1111. Compensation power supply terminal VDDa2 is electrically connected to a corresponding connection pad 121 (e.g., another connection pad 121 in the right connection area 14 in FIG. 1 ) for receiving a compensation power supply voltage from an external circuit.

Since the power voltage is only provided to the power terminal VDD1 through the corresponding connection pad 121, the position of the power terminal VDD1 will be limited by the position of the connection pad 121. That is, when the power voltage input port (or pin) is limited, multiple storage units 1111 need to provide power voltage through the same power terminal VDD1. However, the power voltage attenuates during transmission due to trace length or process defects, causing storage cells 1111 (e.g., storage cell 1111a) that are far away from the power terminal VDD1 to be unable to receive sufficient power voltage for read and write operations. Compared to other storage cells 1111, these cells are more susceptible to data read errors due to power voltage attenuation. Therefore, the present application configures a compensation circuit 112 in the electronic device and enables the compensation circuit 112 to provide a compensation voltage to the storage unit 1111 to compensate for the attenuated power voltage. This allows the storage units 1111 electrically connected to the same power terminal VDD1 to have sufficient power voltage to perform corresponding read and write operations, thereby avoiding the occurrence of read data judgment errors.

In this embodiment, the voltage value of the compensation power voltage is greater than the voltage value of the compensation voltage, and the voltage value of the power voltage is the same as the voltage value of the compensation voltage.

In this embodiment, one compensation circuit 112 is electrically connected to the memory partition 111a as an example for illustration. However, the number of compensation circuits 112 can be increased according to the number of storage cells 1111 in the memory partition 111a and/or the power voltage requirement, and this application is not limited to this example.

In one embodiment, the compensation circuit 112 is a low-dropout regulator (LDO).

Please refer to FIG. 2 , which is a schematic diagram of another embodiment of the electronic device of the present application. In this embodiment, the electronic device is exemplified by a logic circuit device, and the circuit unit is exemplified by a circuit component.

The logic circuit device 30 includes a plurality of circuit components 32 , a compensation circuit 33 , and a plurality of connection pads 40 .

One end of the plurality of circuit components 32 is electrically connected to the power terminal VDD3, and the other end of the plurality of circuit components 32 is electrically connected to the ground terminal GND3. The plurality of circuit components 32 are connected in parallel. The power terminal VDD3 is electrically connected to a corresponding connection pad 40 to receive a power voltage from an external circuit. The ground terminal GND3 is electrically connected to another corresponding connection pad 40 to be grounded through the corresponding connection pad 40.

One end of the compensation circuit 33 is electrically connected to the compensation power supply terminal VDDa3, and the other end of the compensation circuit 33 is electrically connected to one end of a plurality of circuit components 32. The compensation circuit 33 outputs a compensation voltage to the electrically connected circuit components 32. The compensation power supply terminal VDDa3 is electrically connected to a corresponding connection pad 40 for receiving a compensation power supply voltage from an external circuit.

In this embodiment, the voltage value of the compensation power voltage is greater than the voltage value of the compensation voltage, and the voltage value of the power voltage is the same as the voltage value of the compensation voltage.

In this embodiment, one compensation circuit 33 is used as an example for illustration. However, the number of compensation circuits 33 can be increased according to the number of circuit components 32 and/or power voltage requirements, and is not limited to this example.

In one embodiment, the compensation circuit 33 is a low-dropout regulator (LDO).

In one embodiment, the circuit component 32 can be a controller circuit, a processor circuit, or other circuit components, and the present application is not limited thereto.

In this embodiment, the logic circuit device 30 is an integrated circuit device packaged using a wire bonding process.

Therefore, when the power voltage input ports (or pins) are limited, the power voltage will attenuate during transmission due to trace length or process defects. As a result, circuit components 32 far from the power terminal VDD3 (such as circuit component 32a) will not be able to operate with sufficient power voltage. Compared with other circuit components 32, these circuit components are more likely to malfunction due to unstable power voltage. Therefore, the present application configures a compensation circuit 33 in the electronic device and provides a compensation voltage to the circuit components 32 to compensate for the attenuated power voltage, so that each circuit component 32 can operate with sufficient power voltage to avoid malfunction.

Next, please refer to Figure 3, which is a schematic diagram of an embodiment of the 3D chip package structure of the present application. The 3D chip package structure 1 includes a memory device 10, a logic circuit device 30, and a substrate 50. The memory device 10 is connected to one side of the logic circuit device 30 via at least one conductive pillar 20, and the substrate 50 is connected to the other side of the logic circuit device 30 via a plurality of connection pads 40. Therefore, the logic circuit device 30 is located between the memory device 10 and the substrate 50.

In one embodiment, the memory device 10 can be implemented by the embodiment of FIG. 1 , and the logic circuit device 30 can be implemented by the embodiment of FIG. 2 , and the present application is not limited thereto.

In this embodiment, the connection region 14 corresponding to a memory partition 111 may be adjacent to a side of the memory partition 111. As shown in FIG3, the connection region 14 of the memory partition 111a is respectively arranged on the left and right sides of the corresponding memory partition 111a.

In this embodiment, the plurality of conductive pillars 20 are only arranged corresponding to the connection region 14 and on the left and right sides of the memory region 111a (111b) in the figure.

In one embodiment, the memory device 10 can receive a power voltage, a compensated power voltage, or be grounded through the logic circuit device 30 via a plurality of conductive pillars 20 .

The logic circuit device 30 is disposed on one side of the memory device 10 and is coupled to the memory device 10 via the conductive pillars 20. The logic circuit device 30 includes at least one circuit component 32. In one embodiment, the logic circuit device 30 further includes at least one memory controller 31. The at least one memory controller 31 is electrically connected to the corresponding conductive pillars 20. Furthermore, the at least one memory controller 31 may be disposed corresponding to the at least one connection clear area 13 and/or the at least one connection area 14 of the connection layer 12. For example, as shown in FIG3 , taking a plurality of memory controllers 31 as an example, the memory controllers 31 may be arranged corresponding to the connection area 14 of the memory partition 111 a and at least on one side of the logic circuit device 30. In other embodiments, the memory controllers 31 may be arranged corresponding to the connection clear area 13 of the memory partition 111 a and away from the side of the logic circuit device 30. In the embodiment in which the memory controllers 31 are arranged corresponding to the connection area 14 of the memory partition 111 a, the memory controllers 31 may be in contact with and connected to the corresponding conductive pillars 20. In an embodiment where the memory controllers 31 are arranged corresponding to the connection clear area 13 of the memory partition 111 a, the memory controllers 31 can be electrically connected to the conductive pillars 20 through a metal wiring layer (not shown) of the logic circuit device 30.

Furthermore, at least one circuit component 32 of logic circuit device 30 is arranged corresponding to at least one connection clear area 13. The vertical projection of at least one circuit component 32 overlaps with the vertical projection of at least one connection clear area 13, and the vertical projection of at least one circuit component 32 does not overlap with the vertical projection of at least one connection area 14. For example, circuit component 32b shown in FIG3 is arranged corresponding to connection clear area 13 of memory partition 111a, and the vertical projection of circuit component 32b overlaps with the vertical projection of connection clear area 13 of memory partition 111a. In this embodiment, at least one circuit component 32 is implemented as an intellectual property (IP) component.

In one embodiment (as shown in FIG. 2 ), the logic circuit device 30 may be connected to the other side of the substrate 50 via a plurality of connection pads 40 to receive power voltage provided by the substrate 50 , compensate power voltage, or be grounded via the substrate 50 .

In this embodiment, the 3D chip package structure 1 is a single-chip system (SoC) implemented by wafer stacking (3D Wafer on Wafer, WoW).

Because the 3D chip package structure 1 embodiment provided by this application includes a connection clearance area 13 and a connection area 14, and the connection pads 121 and the conductive pillars 20 are arranged corresponding to the connection area 14, the conductive pillars 20 are concentrated in the connection area 14 to form the connection clearance area 13. The circuit components 32 do not need to be modified and/or divided according to the distribution of the conductive pillars 20. Instead, the original circuit design architecture can be directly applied to the integrated circuit design in the 3D chip package structure 1 in accordance with the connection clearance area 13. This effectively simplifies the circuit design difficulty and reduces the overall design cost of the integrated circuit chip using the existing quantized circuit components 32, thereby achieving the goal of improving the design convenience of the integrated circuit chip.

In summary, the electronic device and 3D chip package structure embodiments of the present application include a compensation circuit that outputs a compensation voltage to the circuit unit to compensate for the power voltage that has degraded due to being far away from the power terminal. This allows circuit units connected to the same power terminal to operate normally with sufficient power voltage, thereby achieving the goal of providing a stable power voltage to the integrated circuit chip. Furthermore, the 3D chip package structure provided by this application arranges connection pads in predefined connection areas, creating a clear connection area without conductive pillars. This allows the circuit units of a logic circuit device to be directly incorporated into the 3D chip package structure without changing their internal design, aligning them with the clear connection area. This simplifies circuit design and reduces the overall design cost of the integrated circuit chip using existing circuit units. Therefore, this application achieves the goal of enhancing the design convenience of integrated circuit chips.

1: 3D chip package structure 10: Memory device 11: Memory crystal layer 111, 111a, 111b: Memory partitions 1111, 1111a: Storage cells 112, 112a, 112b: Compensation circuit 12: Connection layer 121: Connection pad 13: Connection clearance area 14: Connection area 20: Conductive pillar 30: Logic circuit device 31: Memory controller 32, 32a, 32b: Circuit components 33: Compensation circuit 40: Connection pad 50: Substrate VDD1, VDD2, VDD3: Power supply terminals VDDa1, VDDa2, VDDa3: Compensation power supply terminals GND1, GND2, GND3: Ground terminals

Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present application; Figure 2 is a schematic diagram of an electronic device according to an embodiment of the present application; and Figure 3 is a schematic diagram of a 3D chip package structure according to an embodiment of the present application.

10: Memory device

11: Memory crystal layer

111, 111a, 111b: Memory partitions

1111, 1111a: Storage unit

112, 112a, 112b: Compensation circuit

12: Connection layer

121: Connection pad

13: Connecting to the Clear Area

14: Connection Area

20: Conductive Column

VDD1, VDD2: power supply terminals

VDDa1, VDDa2: Compensation power supply terminals

GND1, GND2: Ground terminals

Claims (9)

An electronic device includes: a plurality of circuit units connected in parallel and electrically connected to a power terminal to receive a power voltage; and a compensation circuit electrically connected to the circuit units and outputting a compensation voltage to the electrically connected circuit units, at least one of the circuit units being remote from the power terminal. The electronic device of claim 1, wherein the compensation circuit is a low voltage differential linear voltage regulator circuit. The electronic device of claim 1, wherein a voltage value of the power voltage is the same as a voltage value of the compensation voltage. The electronic device as described in claim 1, wherein the electronic device is a logic circuit device and the circuit units are a circuit component. The electronic device as described in claim 1, wherein the electronic device is a memory device and the circuit units are a storage unit. A 3D chip package structure comprises: The electronic device of claim 1, comprising: a memory crystal layer including at least one memory partition; and a connection layer, located on one side of the memory crystal layer and having at least one connection pad disposed thereon; wherein, the connection layer corresponding to the at least one memory partition defines at least one connection clear area and at least one connection area, the at least one connection clear area being adjacent to the at least one connection area, the at least one connection clear area having an area equal to or larger than the at least one connection area, and the at least one connection pad being disposed only in the at least one connection area. The 3D chip package structure as described in claim 6, wherein the electronic device further includes at least one conductive column, the at least one conductive column is connected to the at least one connection pad and is configured corresponding to the at least one connection area. In the 3D chip package structure of claim 6, the at least one connection region is adjacent to a side of the at least one memory partition. In the 3D chip package structure as described in claim 7, the at least one conductive column is electrically connected to the power terminal.