TWI394219B - Electrical connection method of semiconductor packages and a peelable adhesive flexible board used for the same - Google Patents
Electrical connection method of semiconductor packages and a peelable adhesive flexible board used for the same Download PDFInfo
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- TWI394219B TWI394219B TW98137168A TW98137168A TWI394219B TW I394219 B TWI394219 B TW I394219B TW 98137168 A TW98137168 A TW 98137168A TW 98137168 A TW98137168 A TW 98137168A TW I394219 B TWI394219 B TW I394219B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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Description
本發明係有關於半導體裝置,特別係有關於一種半導體封裝之電性連接方法及其使用之可撕式黏性軟板。The present invention relates to a semiconductor device, and more particularly to a method of electrically connecting a semiconductor package and a tearable viscous flexible board for use therewith.
目前在半導體之封裝結構中,允許將多個相同記憶體容量之晶片堆疊並封裝在同一封裝體內,以達到兩倍或兩倍以上容量之功能,例如:將兩個以上記憶體容量為512M以上之晶片堆疊結合並封裝成一個記憶體容量為1024M以上之封裝構造,即所謂的「多晶片堆疊封裝」。傳統上,所使用的半導體晶片可區分為中央銲墊(central pad)型晶片與周圍銲墊(peripheral pad)型晶片。特別是將中央銲墊型晶片以主動面(即積體電路形成表面)朝上堆疊時,需要打線較長的銲線,以使晶片電性連接至基板。利用主動面朝上的多晶片堆疊封裝產品係可採用覆線膠層(Film Over Wire,FOW),作為晶片間隔之填充與保護銲線,但由於連接中央銲墊的銲線較長,會有著過高線弧並且在晶片之間留有較長且非固定的線體,使得銲線容易碰觸到上下晶片造成短路以及發生甩線的風險。Currently, in a semiconductor package structure, a plurality of wafers of the same memory capacity are allowed to be stacked and packaged in the same package to achieve a function of twice or more than a capacity, for example, a memory capacity of two or more memories is 512 M or more. The wafer stack is combined and packaged into a package structure having a memory capacity of 1024 M or more, a so-called "multi-wafer stacked package". Conventionally, semiconductor wafers used can be classified into a central pad type wafer and a peripheral pad type wafer. In particular, when the central pad type wafer is stacked with the active surface (ie, the integrated circuit forming surface) facing upward, it is necessary to wire a long bonding wire to electrically connect the wafer to the substrate. The use of active face-up multi-wafer stack packaging products can be used as a film overfill (FOW) as a wafer spacer fill and protective bond wire, but because the bond wire connecting the center pad is long, there will be Excessive line arcs and long and non-fixed wire bodies between the wafers make it easy for the wire to touch the upper and lower wafers causing a short circuit and the risk of twisting.
如第1圖所示,一種習知使用打線之多晶片堆疊結構主要包含有一基板110、一第一晶片120、一第一銲線130、一第二晶片150以及一第二銲線170。該第一晶片120係以主動面朝上方式設置於該基板110上,並且該第一晶片120之主動面121係形成有複數個第一銲墊122。該些第一銲線130與該些第二銲線170係為打線形成之金線。該些第一銲線130係電性連接該第一晶片120之該些第一銲墊122至該基板110之接指111。該第二晶片150係藉由一覆線膠層160(Film Over Wire,FOW)設置於該第一晶片120之主動面121上,並且該覆線膠層160係包覆該些第一銲線130在該主動面121上方的線段。該第二晶片150之主動面151係具有複數個第二銲墊152,並且該些第二銲線170係電性連接該些第二銲墊152至該基板110之接指111。在黏設該第二晶片150的過程中,該覆線膠層160(Film Over Wire,FOW)係可預先形成於該第二晶片150之背面,當貼附該第二晶片150至該第一晶片120上時,經施壓與加熱以使該覆線膠層160包覆該些第一銲線130。然而,由於該覆線膠層160必須要能發揮降低該些第一銲線130之線弧的作能,以避免該些第一銲線130碰觸到該第一晶片120之背面,故對該些第一銲線130造成一定的下壓作用力。溫度壓力等條件一個操作不慎,常使得該些第一銲線130造成甩線或過度變形,甚至碰觸至該第一晶片120之主動面121或銲線互相碰觸而造成短路,導致產品可靠性不佳,更降低了製程速度。此外,為了使該覆線膠層160能夠包覆住該些第一銲線130,而該些第一銲線130又具有一定的打線弧高,故只能使該覆線膠層160之厚度維持在一不可減少之預定值,這會增加了整體的封裝高度。As shown in FIG. 1 , a conventional multi-wafer stack structure using wire bonding mainly includes a substrate 110 , a first wafer 120 , a first bonding wire 130 , a second wafer 150 , and a second bonding wire 170 . The first wafer 120 is disposed on the substrate 110 in an active face-up manner, and the active surface 121 of the first wafer 120 is formed with a plurality of first pads 122. The first bonding wires 130 and the second bonding wires 170 are gold wires formed by wire bonding. The first bonding wires 130 are electrically connected to the first pads 122 of the first wafer 120 to the fingers 111 of the substrate 110 . The second wafer 150 is disposed on the active surface 121 of the first wafer 120 by a Film Over Wire (FOW), and the wire bonding layer 160 covers the first bonding wires. A line segment above the active surface 121. The active surface 151 of the second wafer 150 has a plurality of second pads 152, and the second bonding wires 170 electrically connect the second pads 152 to the fingers 111 of the substrate 110. In the process of affixing the second wafer 150, the Film Over Wire (FOW) may be formed on the back surface of the second wafer 150, and when the second wafer 150 is attached to the first The wafer 120 is pressed and heated to coat the first bonding wires 130 with the first bonding wire 130. However, since the overcoat layer 160 must be capable of reducing the line arc of the first bonding wires 130, the first bonding wires 130 are prevented from contacting the back surface of the first wafer 120. The first bonding wires 130 cause a certain pressing force. Conditions such as temperature and pressure are inadvertently operated, often causing the first bonding wires 130 to cause twisting or excessive deformation, and even touching the active surface 121 of the first wafer 120 or the bonding wires touching each other to cause a short circuit, resulting in a product Poor reliability and reduced process speed. In addition, in order to enable the wire bonding layer 160 to cover the first bonding wires 130, and the first bonding wires 130 have a certain arcing height, the thickness of the wire bonding layer 160 can only be made. Maintaining a predetermined value that cannot be reduced, this increases the overall package height.
因此,目前利用打線作為半導體封裝之電性連接方法,通常是以金線作為打線材料,具有較昂貴之材料成本。特別是中央銲墊型晶片的晶片堆疊數量越多,必須面臨複雜或長銲線製程,更容易發生甩線之情況,亦會造成線塌或接觸晶片邊緣的風險。一旦將傳統的打線方式運用在多晶片堆疊的產品上時,由於皆是利用銲線達到電性連接,隨著晶片堆疊數量越多,在後續封裝製程中也越容易衍生出許多各種關於銲線之不良問題,也無法應用於小線距(fine-pitch,所指為銲線的間距不超過50微米)的封裝產品中。Therefore, at present, wire bonding is used as an electrical connection method for a semiconductor package, and a gold wire is usually used as a wire bonding material, which has a relatively expensive material cost. In particular, the larger the number of wafer stacks of the central pad type wafer, the more complicated or long wire bonding processes must be faced, the more prone to twisting, and the risk of wire collapse or contact with the edge of the wafer. Once the traditional wire bonding method is applied to the multi-wafer stacked products, since the bonding wires are used to achieve electrical connection, as the number of wafer stacks increases, it is easier to derive various kinds of bonding wires in the subsequent packaging process. The problem is not applicable to packaged products with small pitch (fine-pitch, which means that the pitch of the wire is no more than 50 microns).
本發明之主要目的係在於提供一種半導體封裝之電性連接方法及其使用之可撕式黏性軟板,能完全免除以往打線之甩線問題,更毋須擔心造成線塌與接觸晶片之風險,特別可應用於小線距並取代複雜或長銲線製程,提升了封裝的能力與可靠性。The main purpose of the present invention is to provide a method for electrically connecting a semiconductor package and a tearable flexible flexible board for use thereof, which can completely eliminate the problem of the twisting line of the conventional wire bonding, and further avoid the risk of causing the wire to collapse and contact the wafer. It is especially suitable for small line spacing and replaces complex or long wire bonding processes, improving the package's ability and reliability.
本發明之次一目的係在於提供一種半導體封裝之電性連接方法及其使用之可撕式黏性軟板,能提升整體封裝製程效率,更降低了製造成本。A second object of the present invention is to provide a method for electrically connecting a semiconductor package and a tearable flexible flexible board used thereby, which can improve the overall packaging process efficiency and reduce the manufacturing cost.
本發明之再一目的係在於提供一種半導體封裝之電性連接方法及其使用之可撕式黏性軟板,可以達到取代銲線以消除線弧,應用於多晶片堆疊時可縮小晶片堆疊間隙並且在晶片堆疊間隙內不容易產生氣泡。A further object of the present invention is to provide a method for electrically connecting a semiconductor package and a tearable flexible flexible board therefor, which can replace the bonding wire to eliminate the line arc, and can reduce the wafer stacking gap when applied to the multi-wafer stacking. And bubbles are not easily generated in the wafer stack gap.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種半導體封裝之電性連接方法,主要包含有以下步驟:提供一基板,係具有複數個接指。設置一第一晶片於該基板上,在該第一晶片的主動面上設有複數個第一銲墊。設置複數個第一凸塊於該些第一銲墊上。設置一可撕式黏性軟板於該第一晶片上,其中該可撕式黏性軟板之一黏性表面係黏附有複數個可撓性內引腳。進行第一次壓焊步驟,以使該些可撓性內引腳接合至該些第一凸塊。進行第二次壓焊步驟,以使該些可撓性內引腳接合至該些接指。撕離該可撕式黏性軟板而在該第一晶片與該基板之間留下該些可撓性內引腳。本發明另揭示應用於上述電性連接方法之可撕式黏性軟板。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses an electrical connection method for a semiconductor package, which mainly comprises the following steps: providing a substrate having a plurality of fingers. A first wafer is disposed on the substrate, and a plurality of first pads are disposed on the active surface of the first wafer. A plurality of first bumps are disposed on the first pads. A tear-off viscous flexible sheet is disposed on the first wafer, wherein a viscous surface of the detachable viscous flexible board is adhered to a plurality of flexible inner leads. A first pressure bonding step is performed to bond the flexible inner leads to the first bumps. A second pressure welding step is performed to bond the flexible inner leads to the fingers. The tearable viscous flexible sheet is torn away to leave the flexible inner leads between the first wafer and the substrate. The present invention further discloses a tear-off viscous flexible board applied to the above electrical connection method.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述之半導體封裝之電性連接方法中,在設置該些第一凸塊之後與設置該可撕式黏性軟板之前,可另包含之步驟為:覆蓋一絕緣塗佈層於該第一晶片的主動面並顯露出該些第一凸塊,以供該可撕式黏性軟板之黏附,並且該絕緣塗佈層係為一軟膠層。In the foregoing electrical connection method of the semiconductor package, after the first bumps are disposed and before the tearable viscous flexible board is disposed, the method may further include: covering an insulating coating layer on the first The active surface of the wafer exposes the first bumps for adhesion of the tearable viscous flexible board, and the insulating coating layer is a soft rubber layer.
在前述之半導體封裝之電性連接方法中,該可撕式黏性軟板之主體係可為一UV黏性膠膜,並在該兩壓焊步驟之後另以紫外光照射方式降低該UV黏性膠膜對該些可撓性內引腳的黏著力。In the foregoing electrical connection method of the semiconductor package, the main system of the tearable flexible flexible board may be a UV adhesive film, and the UV adhesive is further reduced by ultraviolet light irradiation after the two pressure welding steps. Adhesion of the adhesive film to the flexible inner leads.
在前述之半導體封裝之電性連接方法中,該些可撓性內引腳係可為銅線,並且該些可撓性內引腳之外圍包覆一金層。In the above electrical connection method of the semiconductor package, the flexible inner leads may be copper wires, and the outer edges of the flexible inner leads are covered with a gold layer.
在前述之半導體封裝之電性連接方法中,該些第一銲墊係可設置於該第一晶片的主動面的中央,並且該些可撓性內引腳係呈梳狀交錯排列。In the above electrical connection method of the semiconductor package, the first pads may be disposed at the center of the active surface of the first wafer, and the flexible inner leads are staggered in a comb shape.
在前述之半導體封裝之電性連接方法中,可另包含之步驟為:設置一第二晶片於該第一晶片上,並以一覆線膠層形成於該第一晶片與該第二晶片之間,用以黏接該第一晶片與該第二晶片並局部包覆該些可撓性內引腳。In the foregoing method of electrically connecting the semiconductor package, the method further includes the steps of: disposing a second wafer on the first wafer, and forming a first adhesive layer on the first wafer and the second wafer For bonding the first wafer and the second wafer and partially covering the flexible inner leads.
在前述之半導體封裝之電性連接方法中,該第一晶片與該第二晶片係可具有相同尺寸與功能,並且該第二晶片之主動面係設有複數個第二銲墊。In the foregoing electrical connection method of the semiconductor package, the first wafer and the second wafer system may have the same size and function, and the active surface of the second wafer is provided with a plurality of second pads.
在前述之半導體封裝之電性連接方法中,在設置該第二晶片之步驟之後,可另包含之步驟為:設置複數個第二凸塊於該些第二銲墊上。設置一第二可撕式黏性軟板於該第二晶片上,其中該第二可撕式黏性軟板之一黏性表面係黏附有複數個第二可撓性內引腳。進行第三次壓焊步驟,以使該些第二可撓性內引腳接合至該些第二凸塊。進行第四次壓焊步驟,以使該些第二可撓性內引腳接合至該些接指。撕離該第二可撕式黏性軟板而在該第二晶片與該基板之間留下該些第二可撓性內引腳。In the foregoing electrical connection method of the semiconductor package, after the step of disposing the second wafer, the method further includes the step of: providing a plurality of second bumps on the second pads. A second tear-off viscous flexible sheet is disposed on the second wafer, wherein a viscous surface of the second detachable viscous flexible board is adhered to the plurality of second flexible inner leads. A third pressure bonding step is performed to bond the second flexible inner leads to the second bumps. A fourth pressure bonding step is performed to bond the second flexible inner leads to the fingers. The second flexible adhesive flexible sheet is peeled off to leave the second flexible inner leads between the second wafer and the substrate.
在前述之半導體封裝之電性連接方法中,在設置該些第二凸塊之後與設置該第二可撕式黏性軟板之前,可另包含之步驟為:覆蓋一第二絕緣塗佈層於該第二晶片的主動面並顯露出該些第二凸塊,以供該第二可撕式黏性軟板之黏附。In the foregoing electrical connection method of the semiconductor package, after the second bumps are disposed and before the second flexible adhesive flexible board is disposed, the method further includes: covering a second insulating coating layer And forming the second bumps on the active surface of the second wafer for adhesion of the second tearable flexible flexible board.
在前述之半導體封裝之電性連接方法中,該黏性表面係可更黏附有一引腳匯流排,該引腳匯流排係具有至少一延伸引腳,與該些可撓性內引腳之內端並排。In the above electrical connection method of the semiconductor package, the adhesive surface may be adhered to a pin bus bar having at least one extension pin and the flexible inner pins. Side by side.
在前述之半導體封裝之電性連接方法中,該些可撓性內引腳係可包含往不同方向扇開之複數個第一側內引腳與複數個第二側內引腳,該引腳匯流排係穿過該些第一側內引腳與該些第二側內引腳之間的間隙。In the above electrical connection method of the semiconductor package, the flexible inner leads may include a plurality of first side inner pins and a plurality of second side inner pins fanned in different directions, the pin The busbar passes through a gap between the first side inner pin and the second side inner pins.
在前述之半導體封裝之電性連接方法中,該些第一銲墊係可由複數個第一排銲墊與複數個第二排銲墊所構成,當該可撕式黏性軟板設置於該第一晶片時,該些第一側內引腳之內端係對準於該些第一排銲墊,且該些第二側內引腳之內端係對準於該些第二排銲墊。In the above electrical connection method of the semiconductor package, the first pads may be composed of a plurality of first row pads and a plurality of second row pads, and the tearable flexible board is disposed on the In the first wafer, the inner ends of the first inner pins are aligned with the first row of pads, and the inner ends of the second side inner leads are aligned with the second rows of pads pad.
由以上技術方案可以看出,本發明之半導體封裝之電性連接方法及其使用之可撕式黏性軟板,有以下優點與功效:It can be seen from the above technical solutions that the electrical connection method of the semiconductor package of the present invention and the tearable flexible flexible board used thereof have the following advantages and effects:
一、可藉由覆蓋絕緣塗佈層與貼附具有可撓性內引腳之可撕式黏性軟板作為其中一技術手段,由於可撕式黏性軟板黏附有可撓性內引腳,並藉由可撓性內引腳電性連接晶片與基板,故能完全免除以往打線之甩線問題,更毋須擔心造成線塌與接觸晶片之風險,特別可應用於小線距並取代複雜或長銲線製程,提升了封裝的能力與可靠性。1. As a technical means by covering the insulating coating layer and attaching a tearable flexible flexible board having a flexible inner lead, since the tearable adhesive flexible board adheres to the flexible inner lead And electrically connecting the wafer and the substrate through the flexible inner lead, so that the problem of the conventional wire bonding can be completely eliminated, and there is no need to worry about the risk of causing the wire to collapse and contact the chip, especially for small line spacing and replacing the complex. Or long wire bonding process, which improves the package's ability and reliability.
二、可藉由貼附具有可撓性內引腳之可撕式黏性軟板作為其中一技術手段,由於可撕式黏性軟板係黏附有可撓性內引腳,使可撓性內引腳對準凸塊與金手指,並達到電性連接關係,故能取代以往的打線製程,提升整體封裝製程效率。Second, by attaching a tearable viscous flexible board with a flexible inner lead as one of the technical means, since the tearable viscous flexible board is adhered with a flexible inner lead, flexibility is achieved. The inner pin is aligned with the gold finger and the gold finger, and the electrical connection relationship is achieved, so that the previous wire bonding process can be replaced, and the overall packaging process efficiency is improved.
三、可藉由貼附具有可撓性內引腳之可撕式黏性軟板作為其中一技術手段,由於可撓性內引腳係為銅線,僅是於可撓性內引腳之外圍包覆一金層,故能降低材料成本,更低於以往所使用之金線。3. A flexible floppy flexible board with a flexible inner lead can be attached as one of the technical means. Since the flexible inner lead is made of copper wire, it is only for the flexible inner lead. The outer layer is covered with a gold layer, which can reduce the material cost and is lower than the gold wire used in the past.
四、可藉由貼附具有可撓性內引腳之可撕式黏性軟板作為其中一技術手段,由於可撓性內引腳可以達到取代銲線以消除線弧,應用於多晶片堆疊時可縮小晶片堆疊間隙並且在晶片堆疊間隙內不容易產生氣泡。因此,在與習知相同封裝厚度之情況下能堆疊更多的晶片。Fourth, by attaching a tearable flexible flexible board with a flexible inner lead as one of the technical means, since the flexible inner lead can be substituted for the bonding wire to eliminate the line arc, it is applied to the multi-wafer stacking. The wafer stack gap can be reduced and bubbles are not easily generated in the wafer stack gap. Therefore, more wafers can be stacked with the same package thickness as conventional.
以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明本發明之基本架構或實施方法,故僅顯示與本案有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之第一具體實施例,一種半導體封裝之電性連接方法舉例說明於第2圖之流程方塊圖與第3A至3I圖之元件截面示意圖。該半導體封裝之電性連接方法根據第2圖,可包含以下步驟:「提供一基板」之步驟1、「設置一晶片於基板上」之步驟2、「設置第一凸塊於晶片之銲墊上」之步驟3、「覆蓋絕緣塗佈層於晶片之主動面」之步驟4、「設置可撕式黏性軟板於晶片上,」之步驟5、「進行第一次壓焊」之步驟6,「進行第二次壓焊」之步驟7以及「撕離可撕式黏性軟板」之步驟8,在各步驟上表現元件請參閱第3A至3I圖,說明如下所示。According to a first embodiment of the present invention, a method of electrically connecting a semiconductor package is illustrated in a block diagram of FIG. 2 and a cross-sectional view of an element of FIGS. 3A to 3I. According to FIG. 2, the electrical connection method of the semiconductor package may include the following steps: step 1 of “providing a substrate”, step 2 of “providing a wafer on the substrate”, and “setting a first bump on the pad of the wafer” Step 3, Step 4 of "covering the insulating coating layer on the active surface of the wafer", Step 5 of "Setting the tearable viscous soft board on the wafer," Step 5, "Step 1 of performing the first pressure welding" Step 7 of "Second Pressure Welding" and Step 8 of "Tear Off Removable Viscous Soft Board", please refer to Figures 3A to 3I for the components in each step, as shown below.
首先,執行步驟1。請參閱第3A圖所示,提供一基板210,係具有複數個接指211。該基板210可為一印刷電路板(printed circuit board,PCB)。在本實施例中,該些接指211之材質係可為金(Au),或表面鍍有金之銅墊。詳細而言,該些接指211係位於該基板210之兩側,而位於該基板210之晶片設置區(用以設置晶片之區域)之外。First, go to step 1. Referring to FIG. 3A, a substrate 210 is provided having a plurality of fingers 211. The substrate 210 can be a printed circuit board (PCB). In this embodiment, the materials of the fingers 211 may be gold (Au) or a copper pad with a gold plated surface. In detail, the fingers 211 are located on both sides of the substrate 210 and outside the wafer setting area of the substrate 210 (the area for setting the wafer).
執行步驟2。請參閱第3B圖所示,設置一第一晶片220於該基板210上,在該第一晶片220的主動面221上設有複數個第一銲墊222。具體而言,該第一晶片220係對準於上述的晶片設置區,以不覆蓋至該些接指211。並且,該第一晶片220的主動面221係朝上而遠離該基板210。在本實施例中,該些第一銲墊222係可設置於該第一晶片220的主動面221的中央,銲墊材質可選自於鋁(Al)。Go to step 2. As shown in FIG. 3B , a first wafer 220 is disposed on the substrate 210 , and a plurality of first pads 222 are disposed on the active surface 221 of the first wafer 220 . Specifically, the first wafer 220 is aligned with the above-mentioned wafer setting area so as not to cover the fingers 211. Moreover, the active surface 221 of the first wafer 220 faces upward and away from the substrate 210. In this embodiment, the first pads 222 may be disposed at the center of the active surface 221 of the first wafer 220, and the pad material may be selected from aluminum (Al).
執行步驟3。請參閱第3C圖所示,設置複數個第一凸塊223於該些第一銲墊222上,以使該第一晶片220具有突出於其主動面221之導電端子。在本實施例中,該些第一凸塊223之材質係可選自於金(Au),亦可為銅或鎳金。該些第一凸塊223之具體設置方法係可為打線或電鍍。Go to step 3. Referring to FIG. 3C, a plurality of first bumps 223 are disposed on the first pads 222 such that the first wafer 220 has conductive terminals protruding from the active surface 221 thereof. In this embodiment, the materials of the first bumps 223 may be selected from gold (Au), or may be copper or nickel gold. The specific setting method of the first bumps 223 may be wire bonding or electroplating.
執行一較佳之步驟4。請參閱第3D圖所示,在設置該些第一凸塊223之後,可另包含之步驟為:覆蓋一絕緣塗佈層240於該第一晶片220的主動面221並顯露出該些第一凸塊223,以供一可撕式黏性軟板230之黏附。更佳地,該絕緣塗佈層240係可為一軟膠層,故能在進行後續步驟時,達到暫時性固定以避免該可撕式黏性軟板230曲折過大並可達成伸縮有利於壓焊至凸塊之功效。Perform a preferred step 4. Referring to FIG. 3D, after the first bumps 223 are disposed, the method further includes: covering an insulating coating layer 240 on the active surface 221 of the first wafer 220 and revealing the first portions. The bump 223 is adhered to a tearable viscous flexible sheet 230. More preferably, the insulating coating layer 240 can be a soft rubber layer, so that the temporary fixing can be achieved when the subsequent steps are performed to avoid the tortuous viscous flexible sheet 230 being excessively bent and achieving expansion and contraction. The effect of soldering to bumps.
執行步驟5。請參閱第3E圖所示,並請參酌第4A圖繪示出該步驟之立體示意圖。設置該可撕式黏性軟板230於該第一晶片220上,其中該可撕式黏性軟板230之一黏性表面231係黏附有複數個可撓性內引腳232。在本實施例中,該些可撓性內引腳232係為銅導線,並且該些可撓性內引腳232之外圍包覆一金層232A(請參酌第5圖所示)。因此,可以降低材料成本,更低於以往打線製程中所使用之金線。更具體地,對應銲墊配置位置與欲扇開的導電路徑,該些可撓性內引腳232係可呈梳狀交錯排列,並貼附於該黏性表面231。在一較佳實施例中,該可撕式黏性軟板230之主體係可為一UV黏性膠膜233,使得該可撕式黏性軟板230在完成後續步驟之後,能夠另以紫外光照射方式降低該UV黏性膠膜233對該些可撓性內引腳232的黏著力。詳細而言,該可撕式黏性軟板230係由該UV黏性膠膜233與該些可撓性內引腳232所構成,並且在此步驟中,可藉由該UV黏性膠膜233所具有的黏著力,將該可撕式黏性軟板230黏著至該絕緣塗佈層240上,使得該些可撓性內引腳232能夠逐一對準該些第一凸塊223與該些接指211,避免該些可撓性內引腳232在後續電性連接的壓焊過程中產生位移之情況。此外,由於該可撕式黏性軟板230係可平貼於該絕緣塗佈層240上並產生黏性,故可以達到取代銲線以消除線弧,並預先固定該些可撓性內引腳232的位置,應用於多晶片堆疊時可縮小晶片堆疊間隙並且在晶片堆疊間隙內不容易產生氣泡。Go to step 5. Please refer to FIG. 3E, and a schematic diagram of the step is shown in FIG. 4A. The detachable viscous flexible sheet 230 is disposed on the first wafer 220, wherein one of the viscous surfaces 231 of the detachable viscous flexible sheet 230 is adhered to a plurality of flexible inner leads 232. In this embodiment, the flexible inner leads 232 are copper wires, and the outer periphery of the flexible inner leads 232 is covered with a gold layer 232A (please refer to FIG. 5). Therefore, the material cost can be reduced, which is lower than the gold wire used in the previous wire bonding process. More specifically, corresponding to the pad arrangement position and the conductive path to be fanned, the flexible inner leads 232 may be staggered in a comb shape and attached to the adhesive surface 231. In a preferred embodiment, the main system of the tearable flexible flexible sheet 230 can be a UV adhesive film 233, so that the tearable flexible flexible sheet 230 can be further ultraviolet after completing the subsequent steps. The light irradiation method reduces the adhesion of the UV adhesive film 233 to the flexible inner leads 232. In detail, the tearable adhesive flexible sheet 230 is composed of the UV adhesive film 233 and the flexible inner leads 232, and in this step, the UV adhesive film can be used. 233 has an adhesive force, and the tearable adhesive flexible sheet 230 is adhered to the insulating coating layer 240, so that the flexible inner leads 232 can be aligned with the first bumps 223 and the one. The fingers 211 prevent the flexible inner leads 232 from being displaced during the subsequent soldering of the electrical connections. In addition, since the tearable flexible flexible sheet 230 can be flatly attached to the insulating coating layer 240 and is viscous, it is possible to replace the bonding wires to eliminate the arc and pre-fix the flexible internal leads. The position of the foot 232, when applied to a multi-wafer stack, can reduce the wafer stack gap and is less likely to generate bubbles within the wafer stack gap.
執行步驟6。請參閱第3F圖所示,並請參酌第4B圖繪示出該步驟之立體示意圖。在所進行之第一次壓焊步驟中,藉由一壓焊工具10(bond tool)對準該些可撓性內引腳232之內端與該些第一凸塊223並施加壓力與溫度,以使該些可撓性內引腳232接合至該些第一凸塊223。在本實施例中,該壓焊工具10係可為一點對點小尺寸之熱壓頭,亦可為一次壓焊所有可撓性內引腳232之內端之矩形壓合塊。Go to step 6. Please refer to FIG. 3F, and please refer to FIG. 4B for a schematic perspective view of the step. In the first pressure welding step, the inner end of the flexible inner leads 232 and the first bumps 223 are aligned and pressure and temperature are applied by a bonding tool 10 (bond tool). The flexible inner leads 232 are bonded to the first bumps 223. In this embodiment, the pressure bonding tool 10 can be a small-to-point small-sized thermal head, or a rectangular pressing block that internally welds the inner ends of all the flexible inner pins 232.
執行步驟7。請參閱第3G圖所示,並請參酌第4C圖繪示出該步驟之立體示意圖。在所進行之第二次壓焊步驟中,藉由該壓焊工具10對準該些可撓性內引腳232之外端與該些接指211並施加壓力與溫度,以使該些可撓性內引腳232接合至該些接指211。在完成此步驟之後,該些可撓性內引腳232便已導通該些第一凸塊223與該些接指211,也就是說,該第一晶片220與該基板210已完成電性連接關係。在本實施例中,當該壓焊工具10壓焊該些可撓性內引腳232時,不需要截斷該些可撓性內引腳232之兩端,相較於習知的內引腳接合技術,該些可撓性內引腳232更不會有位移問題,以準確連接該些第一凸塊223與該些接指211。Go to step 7. Please refer to FIG. 3G, and please refer to FIG. 4C for a schematic perspective view of the step. In the second pressure welding step, the pressure welding tool 10 is used to align the outer ends of the flexible inner pins 232 with the fingers 211 and apply pressure and temperature to make the A flexible inner lead 232 is bonded to the fingers 211. After the step is completed, the flexible inner leads 232 have turned on the first bumps 223 and the contacts 211, that is, the first wafer 220 and the substrate 210 have been electrically connected. relationship. In this embodiment, when the pressure bonding tool 10 is pressure-welded to the flexible inner leads 232, it is not necessary to cut off the two ends of the flexible inner pins 232, compared with the conventional inner pins. In the bonding technique, the flexible inner leads 232 are less likely to have displacement problems to accurately connect the first bumps 223 and the fingers 211.
在一較佳實施例中,如第3H圖所示,並請參酌第4D圖繪示出該步驟之立體示意圖。可藉由一UV光照射器20,以紫外光照射該可撕式黏性軟板230,使該UV黏性膠膜233黏性降低而方便從該些可撓性內引腳232上剝離。In a preferred embodiment, as shown in FIG. 3H, a schematic perspective view of the step is illustrated in reference to FIG. 4D. The viscous flexible flexible sheet 230 can be irradiated with ultraviolet light by a UV light illuminator 20 to make the UV adhesive film 233 less adhesive and to be easily peeled off from the flexible inner leads 232.
之後,執行步驟8。請參閱第3I圖所示,並請參酌第4E圖繪示出該步驟之立體示意圖。撕離該可撕式黏性軟板230而在該第一晶片220與該基板210之間留下該些可撓性內引腳232,完全沒有習知的打線弧高。更具體地,此步驟是將已剝離之該UV黏性膠膜233移除,僅留下該些可撓性內引腳232。當完成該步驟之後,即使得該第一晶片220與該基板210之間達成無打線弧高之電性連接,能縮小整體的封裝高度。After that, go to step 8. Please refer to FIG. 3I, and please refer to FIG. 4E for a schematic perspective view of the step. The flexible viscous flexible sheet 230 is peeled off to leave the flexible inner leads 232 between the first wafer 220 and the substrate 210, without any conventional arcing height. More specifically, this step removes the stripped UV-adhesive film 233 leaving only the flexible inner leads 232. After the step is completed, the electrical connection between the first wafer 220 and the substrate 210 is achieved without the arcing height, and the overall package height can be reduced.
較佳地,應用該第一晶片220之第一銲墊222植設該些第一凸塊223,進而塗佈該絕緣塗佈層240,以預防該些可撓性內引腳232碰觸至該第一晶片220之主動面221而造成短路。本發明利用該可撕式黏性軟板230黏附至該絕緣塗佈層240(或可直接黏附至該第一晶片之主動面)以暫時定位該些可撓性內引腳232作為其中一技術手段,能完全免除以往打線之甩線問題,更毋須擔心造成線塌與接觸晶片之風險,特別可應用於小線距(fine-pitch)並取代複雜或長銲線製程,提升了封裝的能力與可靠性。其中,所謂的「小線距」也就是腳距密集化,通常係指該些可撓性內引腳232的內端間距在50微米(μm)以下。由於能夠達到取代銲線以消除線弧之功效,特別是應用於多晶片堆疊時可縮小晶片堆疊間隙,並且在晶片堆疊間隙內不容易產生氣泡。因此,在與習知相同封裝厚度之情況下能堆疊更多的晶片,以達到更高性能的封裝。此外,本發明係以上述的特殊內引腳接合(Inner Lead Bond,ILB)取代了以往的打線製程,更加提升了整體的封裝製程效率。Preferably, the first bumps 222 of the first wafer 220 are used to implant the first bumps 223, and the insulating coating layer 240 is coated to prevent the flexible inner leads 232 from touching. The active surface 221 of the first wafer 220 causes a short circuit. The present invention utilizes the tearable flexible flexible sheet 230 to adhere to the insulating coating layer 240 (or can directly adhere to the active surface of the first wafer) to temporarily position the flexible inner leads 232 as one of the technologies. Means can completely eliminate the problem of the previous line, and it is not necessary to worry about the risk of causing line collapse and contact with the chip. It can be applied to fine-pitch and replace complex or long wire-bonding process, which improves the package capability. With reliability. Here, the so-called "small line pitch", that is, the pitch of the pitch, generally means that the inner end of the flexible inner leads 232 is spaced below 50 micrometers (μm). Since the effect of replacing the bonding wires to eliminate the line arc can be achieved, especially when applied to multi-wafer stacking, the wafer stacking gap can be reduced, and bubbles are not easily generated in the wafer stacking gap. Therefore, more wafers can be stacked with the same package thickness as conventional to achieve a higher performance package. In addition, the present invention replaces the conventional wire bonding process with the above-mentioned special inner lead bonding (ILB), thereby further improving the overall packaging process efficiency.
本發明還揭示前述方法所使用之可撕式黏性軟板舉例說明於第5圖。一種可撕式黏性軟板230適用於半導體封裝之電性連接,該可撕式黏性軟板230之一黏性表面231係黏附有複數個可撓性內引腳232,該可撕式黏性軟板230之主體係為一UV黏性膠膜233。詳細而言,該些可撓性內引腳232係可為銅線,並且該些可撓性內引腳232之外圍包覆一金層232A(如第5圖所示),故能夠降低以往使用(金)銲線的材料成本。The present invention also discloses that the tear-off viscous flexible board used in the foregoing method is illustrated in FIG. A detachable viscous flexible board 230 is suitable for electrical connection of a semiconductor package. One of the viscous surfaces 231 of the detachable viscous flexible board 230 is adhered with a plurality of flexible inner leads 232. The main system of the viscous flexible sheet 230 is a UV adhesive film 233. In detail, the flexible inner leads 232 can be copper wires, and the outer periphery of the flexible inner leads 232 is covered with a gold layer 232A (as shown in FIG. 5), so that the conventional Material cost of using (gold) wire.
依據本發明之第二具體實施例,主要應用第一實施例所揭示之方法並進一步達到多晶片堆疊之電性連接方法,舉例說明於第6A至6G圖。在本實施例中,所揭示之步驟係接續於第一實施例之後,故該第一晶片220與該基板210係已藉由該些可撓性內引腳232達成電性連接。其中與第一實施例相同的主要元件將以相同符號標示,不再詳予贅述。According to the second embodiment of the present invention, the method disclosed in the first embodiment is mainly applied and the electrical connection method of the multi-wafer stack is further achieved, which is illustrated in FIGS. 6A to 6G. In this embodiment, the disclosed steps are continued after the first embodiment, so that the first wafer 220 and the substrate 210 have been electrically connected by the flexible inner leads 232. The same elements as those in the first embodiment will be denoted by the same reference numerals and will not be described in detail.
首先,如第6A圖所示,可設置一第二晶片350於該第一晶片220上,並以一覆線膠層360(Film Over Wire,FOW)形成於該第一晶片220與該第二晶片350之間,用以黏接該第一晶片220與該第二晶片350並局部包覆該些可撓性內引腳232。在本實施例中,該第一晶片220與該第二晶片350係可具有相同尺寸與功能,並且該第二晶片350之主動面351係設有複數個第二銲墊352。在黏晶過程中,由於該些可撓性內引腳232不會產生如同習知銲線的打線弧高,使得該覆線膠層360毋須太厚而能薄化,除了可減少材料使用量之外,更能降低整體的封裝高度。First, as shown in FIG. 6A, a second wafer 350 may be disposed on the first wafer 220, and formed on the first wafer 220 and the second by a Film Over Wire (FOW) 360. The first wafer 220 and the second wafer 350 are bonded between the wafers 350 and partially covered by the flexible inner leads 232. In this embodiment, the first wafer 220 and the second wafer 350 can have the same size and function, and the active surface 351 of the second wafer 350 is provided with a plurality of second pads 352. In the process of the die-bonding, since the flexible inner leads 232 do not have the arcing height as in the conventional bonding wire, the covering tape layer 360 is not too thick and can be thinned, in addition to reducing the amount of material used. In addition, the overall package height can be reduced.
如第6B圖所示,設置複數個第二凸塊353於該些第二銲墊352上。在本實施例中,該些第二凸塊353之材質係可選自於金(Au)。如第6C圖所示,在設置該些第二凸塊353之後,可另覆蓋一第二絕緣塗佈層380於該第二晶片350的主動面351並顯露出該些第二凸塊353,以供一第二可撕式黏性軟板370之黏附。在本實施例中,該第二絕緣塗佈層380與該絕緣塗佈層240皆可為絕緣材料(spacer),用以分別保護該第二晶片350之主動面351與該第一晶片220之主動面221,預防短路之情形發生。As shown in FIG. 6B, a plurality of second bumps 353 are disposed on the second pads 352. In this embodiment, the materials of the second bumps 353 may be selected from gold (Au). As shown in FIG. 6C, after the second bumps 353 are disposed, a second insulating coating layer 380 may be additionally disposed on the active surface 351 of the second wafer 350 to expose the second bumps 353. For adhesion of a second tearable flexible board 370. In this embodiment, the second insulating coating layer 380 and the insulating coating layer 240 may be a spacer for protecting the active surface 351 of the second wafer 350 and the first wafer 220, respectively. The active surface 221 prevents the occurrence of a short circuit.
如第6D圖所示,設置該第二可撕式黏性軟板370於該第二晶片350上,其中該第二可撕式黏性軟板370之一黏性表面371係黏附有複數個第二可撓性內引腳372。在設置時,該第二可撕式黏性軟板370係可更黏附至該第二絕緣塗佈層380。As shown in FIG. 6D, the second tearable flexible flexible sheet 370 is disposed on the second wafer 350, wherein one of the adhesive surfaces 371 of the second tearable flexible flexible sheet 370 is adhered to the plurality of Second flexible inner lead 372. When disposed, the second tearable flexible flexible sheet 370 can be more adhered to the second insulating coating layer 380.
如第6E圖所示,藉由該壓焊工具10,進行第三次壓焊步驟,以使該些第二可撓性內引腳372接合至該些第二凸塊353。如第6F圖所示,再藉由該壓焊工具10,進行第四次壓焊步驟,以使該些第二可撓性內引腳372接合至該些接指211。在完成以上壓焊步驟之後,表示該第二晶片350與該基板210已達成電性連接關係。As shown in FIG. 6E, a third pressure welding step is performed by the bonding tool 10 to bond the second flexible inner leads 372 to the second bumps 353. As shown in FIG. 6F, a fourth pressure welding step is performed by the bonding tool 10 to bond the second flexible inner leads 372 to the fingers 211. After the above pressure welding step is completed, it indicates that the second wafer 350 and the substrate 210 have reached an electrical connection relationship.
再如第6G圖所示,撕離該第二可撕式黏性軟板370而在該第二晶片350與該基板210之間留下該些第二可撓性內引腳372。在一較佳實施例中,在上述兩壓焊步驟之後與撕離該第二可撕式黏性軟板370之前,可另以紫外光照射方式降低該第二可撕式黏性軟板370對該些第二可撓性內引腳372的黏著力,使得該第二可撕式黏性軟板370從該些第二可撓性內引腳372上剝離。在另一變化實施例中,可再重覆上述之步驟達到更多層晶片堆疊,以提升產品性能。As shown in FIG. 6G, the second flexible adhesive flexible sheet 370 is peeled off to leave the second flexible inner leads 372 between the second wafer 350 and the substrate 210. In a preferred embodiment, the second tear-off viscous flexible board 370 may be further irradiated by ultraviolet light after the two pressure-bonding steps and before the second tear-off viscous flexible board 370 is peeled off. The adhesion of the second flexible inner pins 372 is such that the second tearable flexible flexible sheets 370 are peeled off from the second flexible inner leads 372. In another variant embodiment, the above steps can be repeated to achieve more layer wafer stacking to improve product performance.
依據本發明之第三具體實施例,另一種半導體封裝之電性連接方法舉例說明於第7A與7B圖。其中與第一實施例相同的主要元件將以相同符號標示,不再詳予贅述。According to a third embodiment of the present invention, another method of electrically connecting a semiconductor package is illustrated in FIGS. 7A and 7B. The same elements as those in the first embodiment will be denoted by the same reference numerals and will not be described in detail.
在本實施例中,如第7A圖所示,一可撕式黏性軟板430之黏性表面231除了黏附有該些可撓性內引腳232,更黏附有一引腳匯流排434,並且該引腳匯流排434係具有至少一延伸引腳434A,與該些可撓性內引腳232之內端並排。換言之,該引腳匯流排434與該些可撓性內引腳232係可黏附於同一表面(即該黏性表面231)。詳細而言,該些可撓性內引腳232係可包含往不同方向扇開之複數個第一側內引腳432A與複數個第二側內引腳432B,該引腳匯流排434係可穿過該些第一側內引腳432A與該些第二側內引腳432B之間的間隙。該可撕式黏性軟板430可設置於一晶片420上。再如第7B圖所示,該晶片420之主動面221設有複數個中央排列之銲墊222,可由複數個第一排銲墊422A與複數個第二排銲墊422B所構成。當該可撕式黏性軟板430設置於該晶片420時,該些第一側內引腳432A之內端係可對準於該些第一排銲墊422A,且該些第二側內引腳432B之內端係對準於該些第二排銲墊422B,以供壓焊接合。在本實施例中,該引腳匯流排434係位於該些第一排銲墊422A與該些第二排銲墊422B之間的排列間隙,該延伸引腳434A係可對準於其中一之該些第二排銲墊422B,可作為接地或電源之連接。In this embodiment, as shown in FIG. 7A, the viscous surface 231 of the tear-off viscous flexible board 430 is adhered to the flexible inner leads 232, and a pin bus 434 is adhered, and The pin bus bar 434 has at least one extension pin 434A that is juxtaposed with the inner ends of the flexible inner pins 232. In other words, the pin bus bar 434 and the flexible inner pins 232 can be adhered to the same surface (ie, the viscous surface 231). In detail, the flexible inner pins 232 can include a plurality of first side inner pins 432A and a plurality of second side inner pins 432B fanned in different directions, and the pin bus bar 434 can be Passing through the gap between the first side inner pin 432A and the second side inner pins 432B. The tearable flexible flexible sheet 430 can be disposed on a wafer 420. As shown in FIG. 7B, the active surface 221 of the wafer 420 is provided with a plurality of centrally arranged pads 222, which may be composed of a plurality of first row pads 422A and a plurality of second row pads 422B. The inner end of the first side inner lead 432A can be aligned with the first row of solder pads 422A, and the second side is disposed when the tearable adhesive flexible sheet 430 is disposed on the wafer 420. The inner end of the pin 432B is aligned with the second row of pads 422B for pressure bonding. In this embodiment, the pin bus bar 434 is located in the arrangement gap between the first row of pads 422A and the second row of pads 422B. The extension pins 434A can be aligned with one of them. The second row of pads 422B can be used as a ground or power connection.
以上所述,僅是本發明的較佳實施例而已,並非對本發明作任何形式上的限制,雖然本發明已以較佳實施例揭露如上,然而並非用以限定本發明,任何熟悉本項技術者,在不脫離本發明之技術範圍內,所作的任何簡單修改、等效性變化與修飾,均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
步驟1 提供一基板Step 1 provides a substrate
步驟2 設置一晶片於基板上Step 2 Set a wafer on the substrate
步驟3 設置凸塊於晶片之銲墊上Step 3 Set the bump on the pad of the wafer.
步驟4 覆蓋絕緣塗佈層於晶片之主動面Step 4 Cover the active surface of the insulating coating layer on the wafer
步驟5 設置可撕式黏性軟板於晶片上Step 5 Set the tear-off viscous soft board on the wafer
步驟6 進行第一次壓焊Step 6 Perform the first pressure welding
步驟7 進行第二次壓焊Step 7 Perform a second pressure welding
步驟8 撕離可撕式黏性軟板Step 8 tear off the tearable flexible board
10...壓焊工具10. . . Pressure welding tool
20...UV光照射器20. . . UV light illuminator
110...基板110. . . Substrate
111...接指111. . . Finger
120...第一晶片120. . . First wafer
121...主動面121. . . Active surface
122...第一銲墊122. . . First pad
130...第一銲線130. . . First wire bond
150...第二晶片150. . . Second chip
151...主動面151. . . Active surface
152...第二銲墊152. . . Second pad
160...覆線膠層160. . . Overlay layer
170...第二銲線170. . . Second wire
210...基板210. . . Substrate
211...接指211. . . Finger
220...第一晶片220. . . First wafer
221...主動面221. . . Active surface
222...第一銲墊222. . . First pad
223...第一凸塊223. . . First bump
230...可撕式黏性軟板230. . . Tearable flexible board
231...黏性表面231. . . Viscous surface
232...可撓性內引腳232. . . Flexible inner pin
232A...金層232A. . . Gold layer
233...UV黏性膠膜233. . . UV adhesive film
240...絕緣塗佈層240. . . Insulating coating
350...第二晶片350. . . Second chip
351...主動面351. . . Active surface
352...第二銲墊352. . . Second pad
353...第二凸塊353. . . Second bump
360...覆線膠層360. . . Overlay layer
370...第二可撕式黏性軟板370. . . Second tearable flexible board
371...黏性表面371. . . Viscous surface
372...可撓性內引腳372. . . Flexible inner pin
372A...金層372A. . . Gold layer
380...第二絕緣塗佈層380. . . Second insulating coating layer
420...晶片420. . . Wafer
422A...第一排銲墊422A. . . First row of pads
422B...第二排銲墊422B. . . Second row of pads
430...可撕式黏性軟板430. . . Tearable flexible board
432A...第一側內引腳432A. . . First side inner pin
432B...第二側內引腳432B. . . Second side inner pin
434...引腳匯流排434. . . Pin bus
434A...延伸引腳434A. . . Extension pin
第1圖:為習知的使用打線之多晶片堆疊結構之截面示意圖。Figure 1: Schematic cross-sectional view of a conventional wafer stack structure using wire bonding.
第2圖:依據本發明之第一具體實施例的一種半導體封裝之電性連接方法之流程方塊圖。2 is a flow block diagram showing an electrical connection method of a semiconductor package in accordance with a first embodiment of the present invention.
第3A至3I圖:依據本發明之第一具體實施例的半導體封裝之電性連接方法之元件截面示意圖。3A to 3I are schematic cross-sectional views showing the components of the electrical connection method of the semiconductor package in accordance with the first embodiment of the present invention.
第4A至4E圖:依據本發明之第一具體實施例在過程中依序對應第3E至3I圖之元件立體示意圖。4A to 4E are schematic perspective views of the components of the 3E to 3I drawings in the process according to the first embodiment of the present invention.
第5圖:依據本發明之第一具體實施例的半導體封裝之電性連接方法繪示其可撕式黏性軟板之截面局部放大圖。FIG. 5 is a partially enlarged cross-sectional view showing the electrical connection method of the semiconductor package according to the first embodiment of the present invention.
第6A至6G圖:依據本發明之第二具體實施例的半導體封裝之電性連接方法進行多晶片堆疊時之元件截面示意圖。6A to 6G are schematic cross-sectional views showing the components of the semiconductor package according to the second embodiment of the present invention when multi-wafer stacking is performed.
第7A與7B圖:依據本發明之第三具體實施例的另一種可撕式黏性軟板之底視圖與被貼附之晶片之上視圖。7A and 7B are views of a bottom view of another tear-off viscous flexible sheet according to a third embodiment of the present invention and an upper view of the attached wafer.
210...基板210. . . Substrate
211...接指211. . . Finger
220...第一晶片220. . . First wafer
221...主動面221. . . Active surface
222...第一銲墊222. . . First pad
223...第一凸塊223. . . First bump
230...可撕式黏性軟板230. . . Tearable flexible board
231...黏性表面231. . . Viscous surface
232...可撓性內引腳232. . . Flexible inner pin
233...UV黏性膠膜233. . . UV adhesive film
240...絕緣塗佈層240. . . Insulating coating
Claims (16)
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| TWI394219B true TWI394219B (en) | 2013-04-21 |
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| US10297566B2 (en) | 2017-01-25 | 2019-05-21 | Winbond Electronics Corp. | Semiconductor structure and manufacturing method thereof |
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|---|---|---|---|---|
| US5845766A (en) * | 1997-04-17 | 1998-12-08 | Matsushita Electric Industrial Co., Ltd. | Movable contact element for panel switch and method of manufacturing panel switch with movable contact element |
| US5986228A (en) * | 1998-02-13 | 1999-11-16 | Matsushita Electric Industrial Co., Ltd. | Movable contact unit for panel switch and panel switch using the same |
| US6768074B2 (en) * | 2001-03-08 | 2004-07-27 | Alps Electric Co., Ltd. | Easily peelable sheet having contact plates and switch device employing the same |
| US6906275B2 (en) * | 2001-11-15 | 2005-06-14 | Matsushita Electric Industrial Co., Ltd. | Movable contact unit, panel switch using the same and electronic equipment having the panel switch |
| TWI241695B (en) * | 2004-11-19 | 2005-10-11 | Ind Tech Res Inst | Structure of an electronic package and method for fabricating the same |
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|---|---|---|---|---|
| US5845766A (en) * | 1997-04-17 | 1998-12-08 | Matsushita Electric Industrial Co., Ltd. | Movable contact element for panel switch and method of manufacturing panel switch with movable contact element |
| US5986228A (en) * | 1998-02-13 | 1999-11-16 | Matsushita Electric Industrial Co., Ltd. | Movable contact unit for panel switch and panel switch using the same |
| US6768074B2 (en) * | 2001-03-08 | 2004-07-27 | Alps Electric Co., Ltd. | Easily peelable sheet having contact plates and switch device employing the same |
| US6906275B2 (en) * | 2001-11-15 | 2005-06-14 | Matsushita Electric Industrial Co., Ltd. | Movable contact unit, panel switch using the same and electronic equipment having the panel switch |
| TWI241695B (en) * | 2004-11-19 | 2005-10-11 | Ind Tech Res Inst | Structure of an electronic package and method for fabricating the same |
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| US10297566B2 (en) | 2017-01-25 | 2019-05-21 | Winbond Electronics Corp. | Semiconductor structure and manufacturing method thereof |
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