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CN101236909A - Chip packaging structure and packaging method thereof - Google Patents

Chip packaging structure and packaging method thereof Download PDF

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Publication number
CN101236909A
CN101236909A CNA2008100831601A CN200810083160A CN101236909A CN 101236909 A CN101236909 A CN 101236909A CN A2008100831601 A CNA2008100831601 A CN A2008100831601A CN 200810083160 A CN200810083160 A CN 200810083160A CN 101236909 A CN101236909 A CN 101236909A
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chip
wire
circuit board
gap
packaging structure
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谢其良
林圣惟
李哲毓
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CNA2008100831601A priority Critical patent/CN101236909A/en
Publication of CN101236909A publication Critical patent/CN101236909A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

本发明公开了一种芯片封装结构及其封装方法。该芯片封装方包括：(a)提供线路板，线路板上制作有一手指；(b)装设第一芯片于线路板上，此第一芯片具有至少一焊垫于其上表面；(c)形成至少一导线，由焊垫沿着第一芯片的上表面延伸并电性连接至手指，并且，此导线与第一芯片的上表面间具有空隙；(d)填充非导电胶至此空隙内，形成非导电胶层连接导线及第一芯片的上表面，并使导线及第一芯片的上表面的距离小于导线与第一芯片的上表面间原本的空隙；以及(e)形成封胶体覆盖第一芯片与导线。

The present invention discloses a chip packaging structure and a packaging method thereof. The chip packaging method comprises: (a) providing a circuit board, on which a finger is made; (b) installing a first chip on the circuit board, the first chip having at least one solder pad on its upper surface; (c) forming at least one wire, extending from the solder pad along the upper surface of the first chip and electrically connected to the finger, and a gap is formed between the wire and the upper surface of the first chip; (d) filling the gap with non-conductive glue to form a non-conductive glue layer connecting the wire and the upper surface of the first chip, and making the distance between the wire and the upper surface of the first chip smaller than the original gap between the wire and the upper surface of the first chip; and (e) forming a sealing glue body to cover the first chip and the wire.

Description

芯片封装结构及其封装方法 Chip packaging structure and packaging method thereof

技术领域technical field

本发明涉及一种芯片封装结构及其封装方法，尤其涉及一种利用引线结合(wire-bonding)的芯片封装结构及其封装方法。The invention relates to a chip packaging structure and a packaging method thereof, in particular to a chip packaging structure utilizing wire-bonding and a packaging method thereof.

背景技术Background technique

请参照图1A与1B所示，为典型引线结合(wire-bonding)的芯片封装结构10的剖面示意图与俯视示意图。如图中所示，此芯片封装结构10包括线路板120、芯片140与封胶体160。芯片140设置于线路板120上。芯片140上表面的边缘处制作有焊垫142。焊垫142透过导线150电性连接至线路板120表面的手指(finger)122。封胶体160覆盖芯片140与导线150以提供保护。Please refer to FIGS. 1A and 1B , which are a schematic cross-sectional view and a schematic top view of a typical wire-bonding chip package structure 10 . As shown in the figure, the chip package structure 10 includes a circuit board 120 , a chip 140 and an encapsulant 160 . The chip 140 is disposed on the circuit board 120 . Soldering pads 142 are formed at the edge of the upper surface of the chip 140 . The pad 142 is electrically connected to the finger 122 on the surface of the circuit board 120 through the wire 150 . The encapsulant 160 covers the chip 140 and the wires 150 to provide protection.

随着芯片140内电子元件密度的增加，焊垫142的数量也必须随之增加。因此，芯片140上表面中央位置的空间，也可能需要用来设置焊垫142。不过，设置焊垫142于芯片140上表面的中央位置，必然会增加连接焊垫142与手指122的导线150的长度。又，导线150长度的增加除了会提高短路(相邻导线150相接触)与断路的可能性，导线150与芯片140的上表面的距离也难以有效控制，而容易造成整体封装厚度的增加。As the density of electronic components in the chip 140 increases, the number of bonding pads 142 must also increase accordingly. Therefore, the space at the center of the upper surface of the chip 140 may also be used for arranging the bonding pad 142 . However, arranging the bonding pad 142 at the center of the upper surface of the chip 140 will inevitably increase the length of the wire 150 connecting the bonding pad 142 and the finger 122 . In addition, the increase of the length of the wire 150 will not only increase the possibility of short circuit (adjacent wires 150 contact) and open circuit, but also the distance between the wire 150 and the upper surface of the chip 140 is difficult to effectively control, which easily leads to an increase in the thickness of the overall package.

因此，本发明提供一种芯片封装结构及其封装方法，以解决焊垫设置于芯片上表面的中央位置时所面临的问题，并且可以确保芯片封装结构的可靠性，避免封装结构尺寸产生不必要的增加。Therefore, the present invention provides a chip packaging structure and a packaging method thereof, so as to solve the problems faced when the pads are arranged at the central position on the upper surface of the chip, and can ensure the reliability of the chip packaging structure and avoid unnecessary generation of packaging structure size. increase.

发明内容Contents of the invention

本发明的主要目的在于提供一种引线结合(wire-bonding)的芯片封装方法。此封装方法可以利用芯片上表面的中央位置设置焊垫，同时避免导线过长所容易衍生的短路、断路等问题。此外，本发明的封装方法亦可以使导线维持在芯片上表面一定距离之内，避免整个封装结构的尺寸产生不必要的增加。The main purpose of the present invention is to provide a wire-bonding chip packaging method. This packaging method can use the central position of the upper surface of the chip to set the welding pad, and at the same time avoid problems such as short circuit and open circuit that are easily caused by too long wires. In addition, the packaging method of the present invention can also keep the wires within a certain distance from the upper surface of the chip, avoiding unnecessary increase in the size of the entire packaging structure.

本发明提供一种芯片封装方法。此芯片封装方法包括：(a)提供线路板，线路板上制作有手指(finger)；(b)装设第一芯片于线路板上，此第一芯片具有至少一焊垫于其上表面；(c)形成至少一导线(bonding wire)，由焊垫沿着第一芯片的上表面延伸并电性连接至手指(finger)，并且，此导线与第一芯片的上表面间具有空隙；(d)填充非导电胶至此空隙内，以形成非导电胶层连接导线及第一芯片的上表面；以及(e)形成封胶体覆盖第一芯片与导线。The invention provides a chip packaging method. The chip packaging method includes: (a) providing a circuit board on which fingers are fabricated; (b) installing a first chip on the circuit board, the first chip having at least one solder pad on its upper surface; (c) forming at least one wire (bonding wire), extending from the pad along the upper surface of the first chip and electrically connected to the finger (finger), and there is a gap between the wire and the upper surface of the first chip; ( d) filling the gap with non-conductive glue to form a non-conductive glue layer connecting the wire and the upper surface of the first chip; and (e) forming an encapsulant to cover the first chip and the wire.

本发明并提供一种芯片封装结构。此芯片封装结构包括线路板、第一芯片、至少一导线、非导电胶层与封胶体。其中，线路板上具有手指。第一芯片装设于线路板上，并且，第一芯片具有至少一焊垫于其上表面。导线(bonding wire)是由焊垫沿着第一芯片的上表面延伸至线路板上的手指，并且，导线与第一芯片的上表面间具有空隙。非导电胶层填充于空隙内，以连接导线及第一芯片的上表面。封胶体覆盖第一芯片与导线。The invention also provides a chip packaging structure. The chip packaging structure includes a circuit board, a first chip, at least one wire, a non-conductive glue layer and a sealant. Wherein, there are fingers on the circuit board. The first chip is installed on the circuit board, and the first chip has at least one welding pad on its upper surface. The wire (bonding wire) is extended from the welding pad along the upper surface of the first chip to the finger on the circuit board, and there is a gap between the wire and the upper surface of the first chip. The non-conductive glue layer is filled in the gap to connect the wire and the upper surface of the first chip. The encapsulant covers the first chip and the wires.

关于本发明的优点与精神可以通过以下的发明详述及附图得到进一步的了解。The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

附图说明Description of drawings

图1A与1B为典型芯片封装结构的剖面与俯视示意图；1A and 1B are schematic cross-sectional and top views of typical chip packaging structures;

图2A至2G为本发明的芯片封装方法一优选实施例的一系列剖面示意图；以及2A to 2G are a series of cross-sectional schematic diagrams of a preferred embodiment of the chip packaging method of the present invention; and

图3为本发明的堆叠式多芯片封装结构一优选实施例的剖面示意图。FIG. 3 is a schematic cross-sectional view of a preferred embodiment of the stacked multi-chip package structure of the present invention.

附图标记说明Explanation of reference signs

芯片封装结构：10，200                线路板：120，220Chip package structure: 10,200 Circuit board: 120,220

手指：122，222                       芯片：140Finger: 122, 222 Chip: 140

封胶体：160，260                     焊垫：142，242，342Sealant: 160, 260 Solder pad: 142, 242, 342

导线：150，250，350                  第一芯片：240Wire: 150, 250, 350 The first chip: 240

非导电胶层：270，270’，270”，370   导电凸块：280Non-conductive adhesive layer: 270, 270’, 270”, 370 Conductive bump: 280

堆叠式多芯片封装结构：300            第二芯片：340Stacked multi-chip package structure: 300 Second chip: 340

具体实施方式Detailed ways

图2A至2F图为本发明的芯片封装方法一优选实施例的一系列示意图。首先，如图2A所示，提供线路板220。此线路板220上制作有至少一手指(finger)222。此手指可用以传递电信号至电路板(未示出)。随后，如图2B与2C所示，装设第一芯片240于线路板220上。此第一芯片240具有至少一焊垫242位于第一芯片240的上表面的中央位置。如图中所示，就一优选实施例而言，可设置两列焊垫242于第一芯片240上表面的中央位置。2A to 2F are a series of schematic diagrams of a preferred embodiment of the chip packaging method of the present invention. First, as shown in FIG. 2A , a wiring board 220 is provided. At least one finger 222 is formed on the circuit board 220 . The finger can be used to transmit electrical signals to a circuit board (not shown). Subsequently, as shown in FIGS. 2B and 2C , the first chip 240 is installed on the circuit board 220 . The first chip 240 has at least one pad 242 located at the center of the upper surface of the first chip 240 . As shown in the figure, for a preferred embodiment, two rows of bonding pads 242 may be disposed at the center of the upper surface of the first chip 240 .

接下来，如图2D所示，制作至少一导线(bonding wire)250由焊垫242沿着第一芯片240的上表面朝向第一芯片240的边缘处延伸，并电性连接至制作于线路板220上的手指(finger)222。值得注意的是，此导线250并未接触第一芯片240的上表面，而是与第一芯片240的上表面间保留有一空隙t1。Next, as shown in FIG. 2D , at least one wire (bonding wire) 250 is made to extend from the pad 242 along the upper surface of the first chip 240 toward the edge of the first chip 240, and is electrically connected to the circuit board made on the circuit board. Finger 222 on 220 . It should be noted that the wire 250 does not touch the top surface of the first chip 240 , but there is a gap t1 between the wire 250 and the top surface of the first chip 240 .

随后，如图2E所示，填充非导电胶层270’至此空隙t1内，以连接导线250及第一芯片240的上表面。就一优选实施例而言，可以由第一芯片240上表面的边缘处填充非导电胶进入空隙t1内，以形成此非导电胶层270’。适当控制空隙t1的大小，可以在导线250与第一芯片240的上表面间产生毛细现象，驱使非导电胶朝向第一芯片240上表面的中央位置流动，以增加非导电胶层270’的分布面积。Then, as shown in FIG. 2E , a non-conductive adhesive layer 270' is filled into the gap t1 to connect the wire 250 and the upper surface of the first chip 240. As for a preferred embodiment, the non-conductive glue layer 270' can be formed by filling the edge of the upper surface of the first chip 240 with non-conductive glue into the gap t1. Appropriately controlling the size of the gap t1 can generate a capillary phenomenon between the wire 250 and the upper surface of the first chip 240, driving the non-conductive glue to flow toward the center of the upper surface of the first chip 240, so as to increase the distribution of the non-conductive glue layer 270' area.

非导电胶的流动，除了可以增加非导电胶层270’与导线250以及第一芯片240的接触面积，使导线250可以稳固地粘着于第一芯片240的上表面，也有助于减少非导电胶的使用量。其次，如图2E与2F所示，由于非导电胶层270”的厚度也会随着非导电胶的流动而缩小，导线250与第一芯片240上表面的距离t2会小于原本导线250与第一芯片240间的空隙t1。因此，本封装方法有助于使导线250保持在芯片240上表面的一定距离范围内，避免整个封装结构的尺寸产生不必要的增加。就一优选实施例而言，使用本发明的芯片封装方法，可以使导线250与第一芯片240上表面的距离t2缩小至大致等于导线250的宽度。The flow of the non-conductive glue, in addition to increasing the contact area between the non-conductive glue layer 270' and the wire 250 and the first chip 240, makes the wire 250 firmly adhere to the upper surface of the first chip 240, and also helps to reduce the amount of non-conductive glue. usage. Secondly, as shown in Figures 2E and 2F, since the thickness of the non-conductive adhesive layer 270" will also shrink with the flow of the non-conductive adhesive, the distance t2 between the wire 250 and the upper surface of the first chip 240 will be smaller than the original wire 250 and the first chip 240. A gap t1 between the chips 240. Therefore, this packaging method helps to keep the wire 250 within a certain distance range on the upper surface of the chip 240, avoiding unnecessary increase in the size of the entire packaging structure. In terms of a preferred embodiment , using the chip packaging method of the present invention, the distance t2 between the wire 250 and the upper surface of the first chip 240 can be reduced to approximately equal to the width of the wire 250 .

随后，如图2G所示，形成封胶体260覆盖第一芯片240与导线250，而完成此芯片封装结构200。Subsequently, as shown in FIG. 2G , an encapsulant 260 is formed to cover the first chip 240 and the wires 250 , and the chip package structure 200 is completed.

本发明所制作的芯片封装结构200，具有非导电胶层270”将导线250粘着并固定至第一芯片240上表面，可以避免导线250过长而容易衍生的短路、断路等问题。同时，亦可以使导线250维持在芯片240上表面一定距离范围之内，避免整个封装结构的尺寸产生不必要的增加。The chip packaging structure 200 made by the present invention has a non-conductive adhesive layer 270" to adhere and fix the wire 250 to the upper surface of the first chip 240, which can avoid problems such as short circuit and open circuit that are easily derived from the wire 250 being too long. At the same time, The wire 250 can be kept within a certain distance from the upper surface of the chip 240 to avoid unnecessary increase in the size of the entire package structure.

本实施例中，导线250是由位于第一芯片240上表面的中央位置的焊垫242，朝向第一芯片240的边缘处延伸，再连接至位于线路板220表面的手指222。因此，本实施例的非导电胶层270大致是填充于导线250的中间部分与第一芯片240上表面间的空隙内。将导线250的中间部分粘着至第一芯片240的上表面，可以将导线250稳固地固定于芯片240上表面。此外，由第一芯片240的边缘处填入非导电胶以形成非导电胶层270”，除了可以使导线250维持在芯片240上表面一定距离范围之内，还可以避免导线250与芯片240相接触。In this embodiment, the wire 250 extends from the pad 242 located at the center of the upper surface of the first chip 240 toward the edge of the first chip 240 , and then connects to the finger 222 located on the surface of the circuit board 220 . Therefore, the non-conductive adhesive layer 270 in this embodiment is roughly filled in the gap between the middle portion of the wire 250 and the upper surface of the first chip 240 . Adhesive the middle part of the wire 250 to the upper surface of the first chip 240 can firmly fix the wire 250 on the upper surface of the chip 240 . In addition, the edge of the first chip 240 is filled with non-conductive glue to form a non-conductive glue layer 270 ″, which can not only keep the wire 250 within a certain distance from the upper surface of the chip 240, but also prevent the wire 250 from being in contact with the chip 240. touch.

前述本实施例为单芯片封装结构200的封装方法。不过亦不限于此。如图3所示，本发明的封装方法亦可适用于堆叠式多芯片封装结构300，图中是以一双芯片封装结构为例。如图中所示，第一芯片240位于上方的芯片。第二芯片340直接装设于线路板220上，而第一芯片240装设于第二芯片340的上表面。The foregoing embodiment is a packaging method of the single-chip packaging structure 200 . However, it is not limited to this. As shown in FIG. 3 , the packaging method of the present invention is also applicable to a stacked multi-chip packaging structure 300 , in which a two-chip packaging structure is taken as an example. As shown, the first die 240 is the upper die. The second chip 340 is directly installed on the circuit board 220 , and the first chip 240 is installed on the upper surface of the second chip 340 .

在本实施例中，第一芯片240具有至少一焊垫242于其上表面的中央位置。导线250由焊垫242沿着第一芯片240的上表面延伸至线路板220上的手指222。并且，非导电胶层270填充于导线250与第一芯片242的上表面间的空隙，以连接导线250及第一芯片240的上表面。In this embodiment, the first chip 240 has at least one bonding pad 242 at a central position on its upper surface. The wire 250 extends from the bonding pad 242 to the finger 222 on the circuit board 220 along the upper surface of the first chip 240 . Moreover, the non-conductive adhesive layer 270 fills the gap between the wire 250 and the upper surface of the first chip 242 to connect the wire 250 and the upper surface of the first chip 240 .

不过，本发明不限于适用于位于最上方的第一芯片240。如图中所示，第二芯片340的上表面必须制作导电凸块(bump)280电性连接至第一芯片240。导电凸块280通常是位于芯片上表面的边缘位置，因此，在第二芯片340上表面的中央位置仍留有空间可设置焊垫342。此焊垫342可再利用图2A至2F所示的芯片封装步骤，透过导线350电性连接至线路板220上的手指222，而此导线350可透过非导电胶层370连接至第二芯片340上表面。However, the present invention is not limited to be applicable to the first chip 240 located on the top. As shown in the figure, conductive bumps (bumps) 280 must be formed on the upper surface of the second chip 340 to be electrically connected to the first chip 240 . The conductive bumps 280 are usually located at the edge of the upper surface of the chip, therefore, there is still a space at the center of the upper surface of the second chip 340 for disposing the bonding pad 342 . The bonding pad 342 can be electrically connected to the finger 222 on the circuit board 220 through the wire 350 through the chip packaging steps shown in FIGS. chip 340 upper surface.

以上所述利用优选实施例详细说明本发明，而非限制本发明的范围，而且本领域技术人员皆能明了，适当而作些微的改变及调整，仍将不失本发明的要义所在，亦不脱离本发明的精神和范围。The above-mentioned preferred embodiments are used to describe the present invention in detail, rather than limit the scope of the present invention, and those skilled in the art can understand that appropriate minor changes and adjustments will still not lose the gist of the present invention, nor will they depart from the spirit and scope of the invention.

Claims (11)

1.一种芯片封装方法，包括：1. A chip packaging method, comprising: 提供线路板，该线路板上制作有手指；Provide a circuit board with fingers fabricated on the circuit board; 装设第一芯片于该线路板上，该第一芯片具有至少一焊垫于其上表面；Installing a first chip on the circuit board, the first chip has at least one pad on its upper surface; 形成至少一导线由该焊垫沿着该上表面延伸并电性连接至该手指，并且，该导线与该上表面间具有空隙；forming at least one wire extending from the pad along the upper surface and electrically connected to the finger, and there is a gap between the wire and the upper surface; 填充非导电胶至该空隙内，以形成非导电胶层连接该导线及该上表面；以及filling non-conductive glue into the gap to form a non-conductive glue layer connecting the wire and the upper surface; and 形成封胶体覆盖该第一芯片与该导线。An encapsulant is formed to cover the first chip and the wires. 2.如权利要求1所述的芯片封装方法，其中，该非导电胶由该上表面的边缘处填充入该空隙内。2. The chip packaging method as claimed in claim 1, wherein the non-conductive glue is filled into the gap from the edge of the upper surface. 3.如权利要求1所述的芯片封装方法，其中，形成该非导电胶层连接该导线及该上表面后，该导线与该上表面的距离小于该空隙。3. The chip packaging method according to claim 1, wherein after the non-conductive adhesive layer is formed to connect the wire and the upper surface, the distance between the wire and the upper surface is smaller than the gap. 4.一种芯片封装结构，包括：4. A chip packaging structure, comprising: 线路板，该线路板上具有手指；a circuit board with fingers; 第一芯片，装设于该线路板上，该第一芯片具有至少一手指于其上表面；a first chip mounted on the circuit board, the first chip has at least one finger on its upper surface; 至少一导线，由该手指沿着该上表面延伸至该手指，并且，该导线与该上表面间具有空隙；at least one lead extends from the finger to the finger along the upper surface, and there is a gap between the lead and the upper surface; 非导电胶层，填充于该空隙内，连接该导线及该上表面；以及a non-conductive adhesive layer, filled in the void, connecting the wire and the upper surface; and 封胶体，覆盖该第一芯片与该导线。The encapsulant covers the first chip and the wires. 5.如权利要求4所述的芯片封装结构，其中，该导线与该上表面的距离大致等于该导线的宽度。5. The chip package structure as claimed in claim 4, wherein the distance between the wire and the upper surface is approximately equal to the width of the wire. 6.如权利要求4所述的芯片封装结构，其中，该非导电胶层邻近于该上表面的边缘处。6. The chip packaging structure as claimed in claim 4, wherein the non-conductive adhesive layer is adjacent to an edge of the upper surface. 7.如权利要求4所述的芯片封装结构，其中，该焊垫位于该上表面的中央位置。7. The chip packaging structure as claimed in claim 4, wherein the bonding pad is located at the center of the upper surface. 8.如权利要求4所述的芯片封装结构，其中，该非导电胶层位于该导线的中间部分的下方。8. The chip packaging structure as claimed in claim 4, wherein the non-conductive adhesive layer is located under the middle portion of the wire. 9.如权利要求4所述的芯片封装结构，其中，该第一芯片为位于最上方的芯片。9. The chip packaging structure as claimed in claim 4, wherein the first chip is the uppermost chip. 10.如权利要求4所述的芯片封装结构，还包括第二芯片，装设于该线路板的上表面，该第一芯片装设于该第二芯片的上表面。10. The chip packaging structure as claimed in claim 4, further comprising a second chip mounted on the upper surface of the circuit board, the first chip mounted on the upper surface of the second chip. 11.如权利要求10所述的芯片封装结构，还包括多个导电凸块，形成于该第二芯片的上表面，该第二芯片透过该导电凸块电性连接至该第一芯片。11. The chip packaging structure as claimed in claim 10, further comprising a plurality of conductive bumps formed on the upper surface of the second chip, and the second chip is electrically connected to the first chip through the conductive bumps.
CNA2008100831601A 2008-03-07 2008-03-07 Chip packaging structure and packaging method thereof Pending CN101236909A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367172A (en) * 2012-03-27 2013-10-23 南亚科技股份有限公司 Bonding wire fixing method
CN103377952A (en) * 2012-04-13 2013-10-30 南亚科技股份有限公司 Bonding Wire Fixing Method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367172A (en) * 2012-03-27 2013-10-23 南亚科技股份有限公司 Bonding wire fixing method
CN103377952A (en) * 2012-04-13 2013-10-30 南亚科技股份有限公司 Bonding Wire Fixing Method

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