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TWI374536B - Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components - Google Patents

Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components Download PDF

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Publication number
TWI374536B
TWI374536B TW097108734A TW97108734A TWI374536B TW I374536 B TWI374536 B TW I374536B TW 097108734 A TW097108734 A TW 097108734A TW 97108734 A TW97108734 A TW 97108734A TW I374536 B TWI374536 B TW I374536B
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TW
Taiwan
Prior art keywords
die
package
board
contacts
back side
Prior art date
Application number
TW097108734A
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English (en)
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TW200901435A (en
Inventor
David J Corisis
J Michael Brooks
Choon Kuan Lee
Chin Hui Chong
Original Assignee
Micron Technology Inc
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Publication of TW200901435A publication Critical patent/TW200901435A/zh
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Publication of TWI374536B publication Critical patent/TWI374536B/zh

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    • H—ELECTRICITY
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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九、發明說明： 【發明所屬之技術領域】 本發明係關於封裝半導體器件。更明確言之本發明提 供封裝半導體器件之震置、封裝的半導體元件、製造封裝 半導體器件之裝置的方法，以及製造半導體元件之方法。 【先前技術】 半導體器件典型係製造在半導體晶圓上，或其他使用尖 端設備和實現可靠性高品質製造之程序之類型的工件上。 個別的晶粒（例如器件）-般包括積體電路及複數個耗合至 該等積體電路的焊墊。該等焊塾透過傳送至/自該等積體 電路的供應電壓、電信號及其他輸人/輸出參數，提供外 部接點的一陣列。該等焊塾通常非常小，且其典型上係配 置在密集陣列（在焊塾之間具有微細間距）中。該等晶粒相 當的精密且需要保護不受到環境影響和處理。所以，封裝 該等晶粒以保護該等晶粒，且比連接至一印刷電路板還^ 易地連接該等焊墊至較大端子的一陣列。該等封裝的半導 體疋件接著可電連接至許多類型產品的其他微電子器件或 ，……褒半導體晶粒的其一類型。陶究封裝與 上具有個別的陶瓷屋_分，甘曰‘ 肖无早兀’其具有一空腔、於該空腔中的 粒接點及電轉合至今笼θ私机 ^ 至該昶接點的外部端子。該等外部 子一般係位在該陶咨i; Μ 陶是早7C的外部側壁或背側上。 曰 疋位在該空腔中，以及蔣兮楚日 , 將μ荨日日粒上的該等焊墊電耦合 在該空腔中的該裳a私拉机 m 等日曰粒接點。-囊封件接著係置於該空, i29745.doc 1374536 中以覆蓋該晶粒。 陶究封裝對於許多應㈣有益的，但是其亦具有數個缺 點。陶㈣裝的其-缺點係，該等陶£單元一般係分別地 處理’而非為—可在晶圓處理設備中處理之晶圓形式。所 以’每-該等個別陶曼單元必須載入至用於封裝程序的托 盤中，且接著卸載用於隨後處理。此種處理係花費昂貴且 影響封裝程序的產出量。同樣地，與其他類型的封裝相
比’陶究封裝對於製造商而言係相對較昂貴的。因此，陶 瓷封裝具有數個缺點。 另一空腔型半導體封裝具有—層壓在—電路板上的聚合
物直立插卡(riser)。例如’韓國的景碩科技公司⑻咖S C0mpany)製造了 一包括一印刷電路板的非堆疊空腔封裝， 其於-側上具有複數個晶粒接點及於其他側上具有複數個 背側接點。該封裝進—步包括—沒有㈣至該印刷電路板 之電路系㈣上方板。該上方板具有界定該印刷電路板上 之工腔的開口 ’但是該上方板不包括任何電路系統或通 孔。一晶粒係黏著至由該上方板中的開口所形成之空腔中 的印刷電路板’且該晶粒上的焊墊係連接至該印刷電路板 上的晶粒接點。該空腔接著填有-聚合物或其他種類的囊 封件以囊封該晶粒。 雖然此種層壓封裝對於製造商而言係有益且相對較不昂 責的，但是其並不適合用於在高密度應用中堆疊封裝。例 如，此種層壓封裝無法使用在堆疊的組裝件中，因為這些 封裝沒有提供一選路來至/自上方封裝的功率及信號的電 < S ) 129745.doc 1374536 連接。因此，其需要發展—種使用用於製造具有完全受測 封裝之高密度堆疊的層壓電路板材料的空腔型封裝。 【實施方式】 Ο
以下將參考封裝的半導體元件、封裝半導體器件之裝 置、封裝半導體器件之方法以及製造封裝半導體器件之裝 置的方法說明本揭示内容之數個具體實施例的特定細節。 製造於半導體晶圓上的該等器件可包括基板，於基板上及/ 或基板内製造微電子器#、微機械器件'資料儲存元件、 光學器件、讀取/寫入元件及其他特冑。例如，可將 SRAM、DRAM(如 DDR/SDRAM)、㈣記•隐體（如 nand/ 記憶體）、處理器、成像器及其他類型的器件構造在半導 體晶圓上。雖然下文係相對半導體晶圓描述許多具體實施 例，但是製造在其他類型基板（例如介電基板或導電基板） 上的其他類型的器件亦在本發明的範疇内。此外，本發明 之其他數個具體實施例可具有不同組態、元件或程序而非 此部分中所述的組態、元件或程序。因此，熟知本技術者 人士將相應地理解本發明的其他具體實施例可具有額外的 兀件’或者還有更多的具體實施例可不具有以下參考圖b 7所示及描述的數個特徵及元件。 圖1係不意性說明根據本發明一具體實施例之一封裝的 半導體疋件1 00的斷面圖。在此具體實施例中，該半導體 兀件1〇〇包括一具有—第一基板112的基座n〇、一具有一 第二基板122的直立插卡12〇，以及一附接至該基座11〇的 半導體晶粒130。該第一基板112及該第二基板122可由聚 129745.doc 丄 3745,36 =材料:樹脂、聚石夕氧等等)、除了聚合材料以外的有機材 或疋其他合適的非陶究介電材料組成。例如，該第一 基板112及該第二基板122可由層壓的電路板材料組成。該 封裝之半導體元件100的數個具體實施例提供一具成本效 益的空腔型封裝，其由一合適用於堆疊的聚合材料組成。 在特定具體實施例中，例如，一堆疊組裝件可具有相同或 其他種類之封裝的半導體元件1〇〇附接至該直立插卡12〇的 頂端，以提供完全受測之封裝器件的高密度堆疊。 1在基座110的所述具體實施例中，該第一基板112具有一 刖側114及-背側i 15。該基座i⑺之所述具體實施例進一 步包括複數個晶粒接點丨丨6、於該背側丨丨5處之第一陣列第 -背側端子117’及於該背側115處之第二陣列第二背側端 子118。於圖丨所示之具體實施例中的該等晶粒接點1丨6係 位於或至少近接於該第一基板112的前側U4。然而，在其 他用於晶片上板（b0ard-0n-chip; BOC)組態的具體實施例 中，該等晶粒接點116可位在背側115，以下將詳細描述。 該基座no進一步包括第一互連119,其電耦合至該等晶粒 接點116，以對應第一背側端子117。該封裝的半導體元件 100亦可具有焊線132，其電連接晶粒130上的焊墊（未示出） 與該等晶粒捿點116 〇該等第互連119及該等焊線132可 因此載送該晶粒130及該等第一背側端子117之間的信號和 功率。 在圖1所示之直立插卡12〇的特定具體實施例中，該第二 基板122包括一第一側124及一第二側125。該第二基板122 129745.doc -9- 13745.36 的第一側124係藉由一黏著劑（圖！未示出），於該第一基板 U2和該弟一基板122之間的介面處，附接至該第一基板 112的前側114。該直立插卡12〇之所述具體實施例進一步 包括一界定一晶粒腔127的開口 126 ’其中該晶粒13〇係定 位於該晶粒腔127中。該直立插卡12〇可進一步包括複數個 位在该第二基板1 22之第二側1 25的正面接點1 28。該等正 面接點128提供用於在一封裝的元件上接觸焊球或其他類 型之電連接器的電端子，該封裝的元件係堆疊在該封裝之 半導體元件100的頂端上。 e玄封裝的半導體元件1〇〇可進一步包括複數個第二互連 1 4〇 ’其延伸穿過該基座11 〇及該直立插卡〗2〇。例如該 封裝的半導體元件1〇〇可具有一封裝貫穿孔141，其延伸穿 過該第一基板112的厚度及該第二基板122的厚度。該貫穿 孔141接著可至少部分地填有一導電材料，以形成該等第 一互連140(例如封裝貫穿互連；如〇1^ package jnterc〇nneets)。 4等第二互連140電麵合位在該第二基板122之第二側125 處的正面接點128，以對應位在該第一基板112之背側U5 處的第二背側端子11 8。該等第二互連14〇提供一封裝堆疊 選路，以傳送功率及電信號至/自堆疊在圖1所述之該封裝 的半導體元件100之頂端上的另一封裝的半導體元件（未示 出）。該等第二互連140亦可載送用於圖！該封裝的半導體 元件100中所示之晶粒130的功率及/或電信號。 該封裝的半導體元件1〇〇可進一步包括一於該腔127中的 保護性材料1 50，以覆蓋該晶粒1 3〇及該等焊線1 32。可使 129745.doc 1374536 用針狀刀心、刻板印花（stenciling)、模製或其他合適 =術來沈積該保護性材料15〇。該保護性材料15〇通常係 物或其他覆蓋該晶粒130及該等輝線132的合適材 料該保遵性材料i 5〇的上表面通常係共面或低於該第二 基板122的第二側125。’然而，該保護性材料15G的上表面 可ώ出超過該第二側125，只要該保護性材料15〇不會干擾 到任何可堆疊在該封裝的半導體元件丨⑽之頂端上的封裝 即可。 ^
圖A 2G說明封裝半導體器件之方法的一特定具體實施 例的階段。圖2八說明該方法的一階段m板 21〇(例如基座面板）具有一介電核心212、一前側213、一在 該前側213的第-導電層214、—背側215及—在該背側215 的第二導電層216。該介電核心212可為-聚合物、非聚合 有機材'料’或另一合適的非陶宪介電㈣。該第一導電層 214及該第二導電層216可為銅或其他合適的導電材料。圖 2B說明該第一板210的後續階段，其中第-開口218係透過 該第-導電層214、該介電核心212及該第二導電層216而 形成。該等第一開口218可藉由鑽孔、蝕刻、雷射切割、 水力噴射，或其他合適的技術形成。例如，該等開口 218 可使用本技術已知的機械鑽孔或雷射鑽孔形成。 圖2C說明該第一板21〇於該方法的一階段，其中第一互 連220係形成在該等第一開口218中，以電耦合該第一導電 層至該第二導電詹216。該等第—互連咖可藉由電鑛 材料至該等第一開口 218之側壁上而形成，如本技術已 129745.doc 1374536 知。例如，該等第-互連220可包括電錄在該等第一開口 218之側壁上的銅。圖2D說明該方法的另一階段其中該 第一導電層214已經圖案化及㈣以形成該第—板21〇之前 側213上的導電跡線217，及該第二層216已經圖案化及姓 刻以形成該第一板21〇之背側215上的導電跡線219。一焊 料遮罩230或其他類型的介電元件亦可形成在該等開口218 之間的區域t。如下文更詳細所描述，該焊料遮罩23〇在 一晶粒所定位之處提供一晶粒附接點，且該焊料遮罩可填 滿該等第一開口 21 8中的開放容積。 圖2E說明該方法的一後續階段，其中一第二板25〇係附 接至該第一板210。該第二板250可包括一第二基板252、 一第一侧254、一第二侧256及一開口 258。該開口 258可在 一先前程序中藉由衝壓較大孔穿過該第二板250而形成。 該開口 25 8係與該焊料遮罩230上的晶粒附接點對準，以形 成其中一晶粒可以定位（圖2E未示出）的一空腔260。該第 二板250可相應地為一直立插卡面板或直立插卡板，其形 成該凸出高於該晶粒的直立插卡。該第二板250可進一步 包括該第二側256上經圖案化的導電跡線262。 該第二板250係藉由一黏著劑270附接至該第一板21〇。 在圖2E所述的具體實施例中，該第二板250的第一側254係 藉由該黏著劑270附接至該第一板2 1 〇的前側2 13。該黏著 劑270可先預先附著至該第二板250的第一側254或第一板 210的前側213。在許多應用中，該第一板21〇包括複數個 封裝區域’其各包括一晶粒附接點，及該第二板2 5 0包括 129745.doc -12- 裝的7G件。在數個具體 争廬押實知例中，於切割該裝置200以避 免處理用於測試之個 , 钌裒之刚，該裝置200係在一連續 條狀體中，可測試個別封 裒的半導體兀件。在一替代性具 體實％例中，在測試個
Sta M s J封裝的半導體元件之前沿著線S- S切割該裝置200 ,然後 q M m I 個别的封裝元件載入至一用於測 忒的托盤中。在任一情 / ’僅有良品封裝（known-g〇〇d-
Packages)可在被堆疊 來。 疋黏著至一電路板之前被識別出 該裝置20〇的許多且>|*香_1^/| α實施例可明顯地比陶瓷空腔型封 、較便宜地實行。首先， ^ ^ ^ 複數個日日粒可以黏著至一條狀形 工、义置200，以消除轉移個別处^^_ 砂1固⑴工腔型早兀至/自處理托盤 太^ °此顯著地減少與空腔型封裝關連的時間及製造成 X裝置2GG的许多具體實施例亦可相對地較不昂貴， 為该封裝可自聚合材料或其他合適的非㈣介電材料製 例可Γ裝置200及該封裝之半導體元件_的許多具體實施 裝。目應地提供一適用於堆疊且具成本效益的空腔型封 亦二、置〇〇及該封裝之半導體元件100的數個具體實施例 備上具有咖C接點組態，用於使用現存設 備H式及堆疊該個別封裝的半導體元件ι〇〇。此進—牛 增加用於製造半導體器件之該裝置及該封裝的半導體 π件100之數個具體實施例的效益。 _ k裝置200的數個具體實施例亦可實現該等封裝的半導 體元件的具成本效益測試，因為當該裝置200係-條狀形 129745.doc 晶粒。更明確言之，該條狀體可以 以避免必須轉移個別封裝至/自該 ，該等封裝的器件可更有效率地受 圖3 A係製造一封世_ 料丰㈣料之裝置的方法綱之-具 =施的流程圖。該方法可包括附接一直立插卡板
式時可測試該等封裝的 一測試盤的圖案配置， 等測試盤。就本身言之 測試。 接至二至一基座板之前側(步驟31〇)。該直立插卡板係附 2至該基座板，使得該直立插卡板中的個別開口形成與該 f座板的相對應個別封裝區對準的晶粒腔。該基座板可且 有晶粒接點、在該基座板之背側處的第一背側端子，以及 :該基座板之背側處的第二背側端子。該等晶粒接點可電 合至該等第一背側端子。該方法3〇〇可進一步包括形成 子數個封裝貫穿孔’其延伸穿過該直立插卡板及該基座板 (步驟320)。另外，該方法3⑽可進—步包括沈積—導電材 ^於4等封裝貫穿孔巾（步驟33())。料電材料可形成封裝 穿互連其將該直立插卡板之第二側的前側接點電耗合 至該基座板之背側處的相對應第二背側端子。 泣圖3B係說明製造半導體元件之方法州―具體實施例的 抓程圖。在一具體實施例中，該方法340可包括提供一其 中欲封裝有複數個晶粒的裝置（步驟35〇)。該裝置可包括— 第一板，其具有一前側、—背側、晶粒接點陣列、電Μ 至該等晶粒接點之第—㈣端子陣列、第：背側端子陣 列，以及複數個個別封裝區。該等個別封裝區可具有該等 晶粒接點的一陣列、該等第一背侧端子的一陣列，以=該 129745.doc
• 16 · < S 等第二背側端子的一陣列。兮 干a該裝置可進一步包括一篥一 板，其具有一層壓在該第一板儿 — 側、穿過該第二板與個別的 乐— 二側處的正面接點陣列。於 第 π該等正面接點係藉由封裝貫穿互連(其延伸穿過: 板及該第二板)電搞合至該等第二背側端子。該方： :可進一步包括定位半導體晶粒於該等空驟 360)，及電耦合該等晶粒 驟 粒至5亥第一板之相對應晶粒接點（步 驟3 70)。該方法亦可包括 中(牛驟、呆護性材料至該等晶粒腔 中(步驟38〇)，以覆蓋在該等空腔中的該等晶粒。接著可切 割該具有第-板及第二板的裝置，以彼此分離個別 的半導體元件。 、 圖4係示意性說明一堆疊組聚件彻的斷面圖，其具有一 第一封裝元件刚a及一堆疊在該第—封裝元件购上的第
一封裝元件1 00b。該笛一 4+壯_ /iL 弟封裝TL件1 00a及該第二封裝元件 可類似或相同於上述參考圖i之該封裝的半導體元件 ▲因此圖1及圖4中的相似參考數字可代表相似元 人莫封裝7°件1〇〇a可具有複數個第一連接器402， 如焊球，其輕合i兮笪@ 至該4第一背側端子117。該第一封裝元 件100a亦可包括額外的笛 頻卜的第一連接器404，其耦合至該等第 二背側端子m。然而’該等連接器4〇4為可選的，且不必 在許少/、體實施例中。該第二封裂元件】_可包括複 數個第二連接g , , u , 如~球’其附接至該第二封裝元件 100b之背側上的马·楚# _ # 的〜荨第一貪側端子118 ^該第二封裝元件 129745.doc •17- 1374536 祕的第二連接器406係連接至該第-封裝元件1〇〇a的正 面2點128。一側填滿或其他類型的保護性材料可插在該 第一封裝元件_和該第二封裝^件祕之間。於操作 中1疊組裝件400中的晶粒至封裝選路的路線如箭號41〇 v 另外，可發生該第二元件10〇b至該第一封裝元件 、 1〇〇a的選路，如箭號420所示。 、 ® 5不意性說明一根據用於覆晶應用之另體實施例 • 的堆疊組裝件500。該堆疊組裝件5〇〇包括一第一封裝元件 5心及-第二封裝元件51〇b。該第一封裝半導體元件51〇丑 及该第二封裝半導體元件5 10b可類似於上述的封裝的半導 體几件100。然而，該等晶粒13〇係覆晶晶粒，其使用覆晶 連接而非線結合而連接至該等晶粒接點。就本身而言，該 等晶粒接點116係定位在欲由該晶粒13〇所覆蓋之晶粒附接 點處。 圖6示意性說明一根據用於晶片上板應用之另一具體實 • 施例的堆疊組裝件。在此具體實施例中，該堆疊組裝件 6〇〇包括一第一封裝元件61〇a，其具有一晶片上板設計； . 及一第二封裝元件610b，其亦具有一晶片上板設計。更明 確。之，與圖1所述的晶粒1 3 0相比，該等晶粒1 3 〇係倒轉 的’使得在晶粒上的該等焊墊13丨係分別線結合至該第一 封裝元件61〇a之基座板6123之背側上的晶粒接點U6及該 第二封裝元件61 Ob之基座板612b之背側上的晶粒接點 116。參考該第一封裝的半導體元件6l〇a，該基座板612a 具有一開口 61 4a或槽孔，其透過自該等焊墊131延伸至該 (S ) I29745.doc 1374536 等晶粒接點m的焊線132。同樣地，該基座板_可且有 -槽孔6Mb。因此，自該等晶粒接點116的第一互連可為 沿著該基座板612a之背側延伸而非透過如圖〗之封裝的半 導體元件⑽中所示之該基座板的跡線。該晶片上板封裝 元件可相應地排除該基座板之前側的金屬化。 、 圖7說明-包括上述參考圖卜6所述之封裝的半導體元件 任何其中-個的系統7〇〇。更明確言之，上述參考圖Μ所 述之半導體元件的任何其中_個可併人任何無數個較大及/ 或更複雜的系統’及該系統僅為此一系統的代表性範 「例。該系統700可包括一處理器7〇1、一記憶體7呵如 SRAM DRAM、快閃冗憶體或其他記憶體裝置）、輸入/輸 出器件703及/或子系統及其他元件7〇4。該等封裝的半導 體元件可包括在圖7所示的权& - # + 所不的任何兀件内。所得的系統700可 執行任何各種不同的計算、處理、儲存、感測、成像及/ 或其他功能。因此，該系站& 通糸統700可為（非限制）一電腦及/或 其他資料處理器’例如，—桌上型電腦、膝上型電腦、網 際網路應用產品、手样剤哭放 λ ^ 。 于得型益件、多處理器系統、基於處理 器或可程式化的消費者電子產品、網路電腦及/或迷你電 腦。用於此等系統的合適手持型器件包括掌上型電腦、穿 戴式電腦、蜂巢式電話或行動電話、個人數位助理等等。 該系統700可進一步為一昭 _ .'、、邳機燈，或其他輻射感測 器、词服器及關連司月U :^ ,上，， / ㈣q服子系統及/或任何顯示裝置。在此 種糸統中’個別的晶粒可包括成像器陣列，如CMOS成像 盗。該系統7〇0的元件可予以裝載在一單一單元中，或分 129745.doc 19 13/4536 佈在夕重互連單元上（例如 一 m 处幻通網路）。該系統700的 疋件可因此包括局部及/或 /通端°己憶體儲存器件，及任何 各種不同的電腦可讀媒體。 從前述内容可明白，儘瞢 .^ΒΒ 篮g本文已基於扰明之目的而說明 本發月之特定具體實施例 離本發明之精神警二：丁各種修改而不致背 ，、“例如，任何前述具體實施例的特 ^例可以結合或替代其他具體實施例中的元件。 ”動么^中所允相早數或複數名詞亦可分別包括複數或 S #纟除#子巧”或"係表示限制在排除關於兩 或多個項目之清單之其他項目之僅有一個單—項目的意 心，否則纽-清單中，，或"的使用係意謂著包括⑷任何在 -清單中的單—項目、⑻所有在該清單中的項目, 任何在該清單中之項目的結合。另外，上文揭示内容中所 使用的名詞"包括"係意謂著包括至少列舉的特徵，以致不 排除任何更大數量的相同特徵及/或額外類型的特徵或元 件。因此，本發明僅受限於所附申請專利範圍。 【圖式簡單說明】 圖Η系說明根據本發明—具體實施例之料的半導體元 件的斷面圖。 圖2 A - G係說明根據本發明一具體實施例製造封裝的半 導體元件之方法階段的斷面圖。 圖2H係根據本發明一具體實施例之複數個封裝的半導體 元件的俯視圖。 圖3A及3B係說明根據本發明之具體實施例之方法的流 129745.doc •20· ^/4536 程圖。 的半導體元 裝的半導體 封裝的半導 半導體元件 圖4係說明根據本發明一具體實施例之封裝 件的一堆疊組裝件的示意性斷面圖。 圖5係說明根據本發明另一具體實施例之封 70件的一堆疊組裝件的示意性斷面圖。 圖6係說明根據本發明又另一具體實施例之 體元件的一堆疊組裝件的示意性斷面圖。 圖7係併有根據本發明具體實施例之封農的 之一系統的示意圖。 【主要元件符號說明】 100 封裝的半導體元件 100a 第一封裝元件 100b 第二封裝元件 110 基座 112 第一基板 114 第一基板之前側 115 第一基板之背側 116 晶粒接點 117 第一背側端子 118 第二背側端子 119 第一互連 120 直立插卡 122 第二基板 124 第二基板之第一側 129745.doc -21 · 1374536
125 第二基板之第二側 126 開口 127 晶粒腔 128 正面接點 130 半導體晶粒 131 焊墊 132 焊線 140 第二互連 141 封裝貫穿孔 150 保護性材料 200 經組裝裝置 210 第一板 212 介電核心 213 第一板之前側 214 第一導電層 215 第一板之背側 216 第二導電層 217 導電跡線 218 第一開口 219 導電跡線 220 第一互連 230 焊料遮罩 250 第二板 252 第二基板 129745.doc -22- 1374536
254 第二基板之第一側 256 第二基板之第二側 258 開口 260 空腔 262 圖案化的導電跡線 270 黏著劑/開口 272 側壁 274 第二互連 281 第一焊料遮罩 282 開口 283 第二焊料遮罩 284 開口 291 第一背側端子 292 第二背側端子 294 正面接點 296 晶粒接點 297 鎳層 298 金層 299 個別封裝區 400 堆疊組裝件 402 第一連接器 404 額外連接器 406 第二連接器 500 堆疊組裝件 129745.doc -23 · 1374536 5 10a 第一封裝元件 510b 第二封裝元件 600 堆疊組裝件 610a 第一封裝元件 610b 第二封裝元件 612a 基座板 612b 基座板 614a 開口 614b 槽孔 700 系統 701 處理器 702 記憶體 703 輸入/輸出器件 704 子系統及其他元件 129745.doc -24-

Claims (1)

1374536 Η年5月7日修(更)正本客〇971〇8734號專利申請案 ___文申請專利範圍替換本(κπ Λ Jk*» ^ JtAr · 十、申請專利範圍： 年3月） 1. 一種封裝半導體器件之裝置，其包括： -第一板’其具有一前側；一背側；晶粒接點陣列； 電耦合至該等晶粒接點之第一背側端子陣列； ，禾一责側 端子陣列；及複數個個別封裝區，該複數個個別封裝區 具有該等晶粒接點之一陣列、該等第一背側端子之二品 列及該等第二背側端子之一陣列；以及 弟一板’其具有
增您在琢第一板之該前
側；-第二側；界定晶粒腔的開口，其透過該第二板與 個別的封裝區對準；及在該第二侧處的正面接點陣歹卜、 其藉由延伸穿過該第一板及該第二板的互連電輕合至該 等第二背側端子；及 其中該第-板進-步包括第一互連，其電輕合該等晶 粒接點與相對應的第一背側端子，且其中延伸穿過該第 一板及該第二板的該等互連係第二互連。 2.如吻求項!之裝置，#中該第一板及該第二板具 合核心。 π W 3. 4. 5. 如明求項1之裝置’其中延伸穿過該第一板及該第二板 之該等互連係連續的封裝貫穿互連。 月求項1之裝置’其中該第一板包括一第一印刷電路 板且該第二板包括一第二印刷電路板。 •項1之裝置，其巾該等個別的封裝區及該等晶粒 ^係配置成條狀’ ^其中個別的晶粒腔係藉由切割條狀 體上的線道而分離。 I29745-10I0307.doc 1374536 6. 如請求項1之裝置’其中該等晶粒接點係位在該第一板 之該前側處。 7. 如凊求項1之裝置，其中該第一板進一步包括複數個槽 孔，使得一槽孔係位在個別的封裝區，且其中該等晶粒 接點係以陣列配置在該第一板相鄰該等槽孔的第二側。 8· 一種封裝半導體器件之裝置，其包括： 一基座面板，其具有一前側及一背側，其中該基座面 板包括一聚合材料； 一直立插卡面板，其具有一附接至該基座面板之該前 侧的第一侧、一第二側及複數個界定晶粒腔之開口，其 中該直立插卡面板包括一聚合材料； 在該基座面板處的晶粒接點陣列； 在該基座面板之該背侧處的第一背側端子陣列； 第一互連，其電耦合該等晶粒接點至該等第一背側端 子； 在該直立插卡面板之該第二側處的正面接點陣列； 在該基座面板之該背側處的第二背侧端子陣列；以及 第二互連，其延伸穿過該基座面板及該直立插卡面 板，其中該等第二互連電耦合該等正面接點至該等第二 背側端子。 一 9·如請求項8之裝置，其中該基座面板包括一第一印刷電 路板，該直立插卡面板包括一第二印刷電路板，及該等 開口在該第一印刷電路板中包括數個衝孔。 10.如請求項9之裝置’纟中該基座面板包括一第一印刷電 129745-1010307.doc 1374536
路板’該直立插卡面板進一步包括一具有一黏著劑附著 在該第一側的第二印刷電路板，及該等開口在該第一印 刷電路板及該黏著劑中包括數個衝孔。 11.如請求項9之裝置，其中該等第二端子包括連續的封裝 貫穿端子，其從該直立插卡面板的該第二側延伸至該基 座面板的該背側。 土 12_如：求項8之裝置，其中該基座面板及該直立插卡面板
界定一具有複數個晶粒腔的條狀體，該複數個晶粒腔係 藉由切割線道而分離。 13. —種封裝的半導體元件，其包括： 一基座，其具有一第一聚合基板，包括一前側及一背 側；晶粒接點；在該背側處之第一背側端子之一第一陣 列；在該背側處之第二背側端子之一第二陣列；及第一 互連，其電耦合該等晶粒接點與該等第一背側端子；， 一直立插卡，其具有一第二聚合基板包括一第一側 及-第二側；-開口 ；及在㈣二側處之正面接點·其 中該第一側係附接至該第一聚合基板之該前側，且該開 口界定一晶粒腔； 透過該第-聚合基板及該第二聚合基板的第二互連電 揭合該等正面接點至相對應的第4側端子；以及 在該晶粒腔中之一晶粒，其中該晶粒具有一電耦合至 該等晶粒接點的積體電路。 進一步包括一第二封 的該第二側上，其中 14·如請求項Π之封裝的半導體元件， 裝的半導體元件堆疊在該直立插卡 129745-J0I0307.doc 1374536 該第二封裝的半導體元件具有電連接器附接至該等正面 接點。 κ如請求項u之封裝的半導體㈣，其_晶粒接點係位在 該基座之該前側處，且該晶粒具有線結合至晶粒接點的 焊墊。 ’ 如請求項u之封裝的半導體元件，其中該等晶粒接點係 位在該基座之該前側處，及該晶粒具有覆晶附接至該等 晶粒接點的焊墊。 17.如請求項13之封裝的半導體元件，其中該基座進一步包 括-槽孔’且該等晶粒接點係位在該基座之該背侧處， 及其中該晶粒具有面對該槽孔的焊墊，且藉由延伸穿過 該槽孔的焊線而線結合至該晶粒接點。 18·如請求項13之封裝的半導體元件，進一步包括在該晶粒 腔中之一保護性材料。 19. 一種製造一封裝半導體器件之裝置的方法，其包括： 附接一直立插卡板之一第一側至一基座板之一前侧， 其中藉由該直立插卡板中的個別開口形成晶粒腔，其與 該基座板之相對應的個別封裝區對準，且其中該基座板 具有晶粒接點及在該基座板之一背側上電耦合 粒接點的第一背側端子； ^ BB 形成複數個封裝貫穿孔，其延伸穿過該直立插卡板及 該基座板；以及 沈積一導電材料在該等封裝貫穿孔中，其中該導電材 料形成數個封裝貫穿互連，其電耦合該直立插卡板之一 I29745-I010307.doc 1374536 第二側處的正面接點至該基座板之-背側上的相對應第 二背側端子。 20.如明求項19之方法’其中在附接該直立插卡板至該基座 板之前，該方法進-步包括：附接-黏著劑至該直立插 卡板㈣H及衝_等開口穿過該直立插卡板及 該黏著劑》 21·如請求項19之方法，其中該基座板包括-第-印刷電路 板1直立插卡板包括__第二印刷電路板，及其中該方 法進纟包括.對準該直立插卡板_mi㈣㈣ 基座板的該等第二背側端子，及將該直立插卡板的該第 -側及該基座板的該前側朝一黏著劑按壓。 22. 如請求項21之方法’其中形成該等封裝貫穿孔包括：將 數個孔鑽孔穿過該直立插卡板及該基座板。 23. 如請求項19之方法，其中： 該方法進一步包括：制·進兮 對皁該直立插卡板的該等前側接 點與該基座板的該等第二背側端子，及將該直立插卡板 的二第債1及該基座板的該前側朝一黏著劑按壓；以及 形成該等封裝貫穿孔包括：將數個孔鑽孔穿過相對應 對的前側接點及第二背側端子。 ， 24. 如s青求項19之方法，其中： Γ法進一步包括：對準該直立插卡板的該等前側接 點與該基座板的該等第二背 貪側端子，及將該直立插卡板 ^貝及該基座板的該前側朝-黏著劑按壓； 形成該等封裝貫穿？丨& & , μ 匕括.將數個孔鑽孔穿過相對應 129745-1010307.doc 1374536 對的前側接點及第二背側端子；以及 沈積一導電材料於該等封裝貫穿孔中包括：電鍍一金 屬至該等孔中。 25·如請求項19之方法，其中： 在附接該直立插卡板至該基座板之前，該方法進一步 包括：在該直立插卡板之該第二側上形成電路系統、附 接黏著劑至該直立插卡板的該第一側，及衝壓該開口 穿過該直立插卡板及該黏著劑；以及 附接該直立插卡板至該基座板包括：將在該直立插卡 板之該第一側的該黏著劑朝該基座板之該前側按壓，同 時將該等開口對準相對應的個別封裝區。 26. 如凊求項25之方法，其中在該第二側之該等前側接點相 對於該基座板之相對應的第二背側端子係疊置的，且形 成該等貫穿孔包括：鑽孔該等前側接點處的孔，其延伸 至相對應的背側接點。 27. 如凊求項26之方法’其中沈積該導電材料於該等貫穿孔 中包括：電鍍一金屬至該等孔中。 28· —種製造半導體元件之方法，其包括： 提供一其中欲封裝有複數個晶粒的裝置，該裝置包 第-板，其具有-前側；__背側；晶粒.接點陣列； 電麵合至該等晶粒接點之第—背側端子陣列；帛二背 端子陣列；及複數個個別封梦F，# # & & 貝1 j钌屐&，該複數個個別封裝區 具有該等晶粒接點之一陣列 '嗜黧 、 干N这等第一背側端子陣列之 129745.1〇l〇3〇7.doc 陣列及該等第二背側端子之一陣列；以及 I第一板，其具有一壓在該第一板之該前側之第一 側’-第二側；界定晶粒腔的開口，其透過該第二板與 個别的封裝區對準；及在該第二側處的正面接點陣列， 其藉由延伸穿過㈣—板及該第二板的封裝貫穿互連而 電耦合至該等第二背側端子； 定位半導體晶粒於該等晶粒腔中； 電輕合該等晶粒上的焊塾至該第一板的相對應晶粒接 點；以及 沈積保護性材料至該等晶粒腔中。 29.如睛求項28之方法，其中電麵合該等晶粒上的該等焊塾 至該等aa粒接點包括：線結合該等焊墊至該等晶粒接 3〇.如請求項28之方法， 至該等晶粒接點包括 點。 其中電耗合該等晶粒上的該等焊塾 :覆晶黏著該等焊墊至該等晶粒接 31.如請求項28之方法，其中： δ第板具有槽孔，且該等晶粒接點係以陣列配置在 該第一板近接於該等槽孔之背側處； 該等晶粒具有一作用側附接至該第一板的前表面，使 得該等晶粒上的焊塾係與-相對應的槽孔對準；以及 電耦合該等晶粒上的該等焊墊 形成延伸穿過該等槽孔的焊線， 塾延伸至該專晶粒接點。 至該等晶粒接點包括： 其中該等槽孔自該等垾 129745-1010307.doc 1374536 32·如請求項28之方法，.隹 .^ , 切自丨# Μ ^ ,匕括在該等個別封裝區之間 J該第一板及該第二板，其中個別之封裝的半導體元 件係彼此分離。 衣扪平等體70 33. 如請求項32之方法， 半導體元禆，》 〜匕括測試該等個別之封裝的 ，僅互相堆疊良品封裝的半導體元件。 34. 如請求項33之方法 等篮7"件 其中堆疊包括·，電耦合一第一 之半導體元件之前侧接點與一第二封裝之 相對應的第二背側端子，其中該第二封裝之 件: 係堆叠在該第一封裝之半導體元件上。 疋 35. 如請求項28之方法，迨一丰— > 上 二板以決定良品封裝之/二㈣該第一板及該第 體元件。㈣之則’測試該等個別之封裝的半導 %如請求項以方法，進—步包括在該等 切割該第-板及該第二板，及僅互相堆叠良？ 導體元件。 $艮时封裝的半 37.如請求項36之方法，|由給晶 其中堆疊包括：電耦合— 之半導體元件之前侧接點與-第二封裝之半導：：：裝 相對應的第二背側端子，體兀件之 ^疋第一封裝之丰遂躺__从 係堆疊在該第一封裝之半導體元件上。 疋牛 129745-1010307.doc 1374536 -- 第097108734號專利申請案 /W年3月7日修(更)正替換頁中文圖式替換頁(101年3月)
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WO2008112643A3 (en) 2008-12-18
CN101632175B (zh) 2012-02-22
US20100279466A1 (en) 2010-11-04
SG146460A1 (en) 2008-10-30
KR20090122283A (ko) 2009-11-26
US7759785B2 (en) 2010-07-20
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KR101407773B1 (ko) 2014-07-02
US20080224298A1 (en) 2008-09-18

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