1277747 玫、發明說明： 【發明所屬之技術領域】 : 本發明係有關於一種高速半導體元件測試裝置 ： 及其測試方法。 【先前技術】 DDR (Double Data Rate) SDRAM 是一種以 • SDRAM為基礎發展而來的記憶體技術。不同於 SDRAM同步隨機存取記憶體在每個電腦時脈周期只 φ 能支援一個資料運作，DDR SDRAM可以在每個時脈 周期執行兩個資料運作。因此，加倍了記億體的頻寬 也提高資料的傳輸量。因此，DDR SDRAM記憶體已 廣泛應用於電腦系統平台内，包括桌上型電腦、工作 站、伺服器、筆記型電腦、攜帶型、電腦網路及通訊 產品等，成為記憶體技術的主流產品。隨著技術的進 步，DDR SDRAM記憶體的資料率（Data Rate)已由 200/266MHz晉昇為5 3 3/6 6 7MHz，未來更可能進一步 提昇至800MHz/l .066GHz之境。因此，頻率的提昇 對於測試技術也是一項難鉅的挑戰。 請參照圖一，所示為應用於DDR SDRAM記憶體 一測試系統1的示意圖。如圖一所示，測試系統1主 要包括一測試機1 0，例如：此測試機1 0可是由愛德 萬公司所產製之Advantest 5 592/5 593測試機，主要 是用以產生測試型樣（t e s t p a 11 e r η)之用。此測試機1 〇 概可區分為數個測試站（station)，若測試機 10是 Advantest 5592/5593測試機，則提供有兩個測試站 1 2和1 4。每個測試站1 2和1 4分別連接至個別的測 試治具（fixture) 1 6和1 8，即如圖一所示。 5 1277747 請參照圖二，所示為測試治具1 6的示意圖。如圖 二所示，測試治具1 6包括：一測試頭（test head) 20、 一共用電路模組（common motherboard) 22、一插座模 組（socket board) 24等。測試頭20内具有驅動器和 比較器等元件，作為訊號驅動和比較之用。共用電路 模組22内具有接線（coaxial cable)，作為連接電路模 組22與插座模組24之用。插座模組24内具插座電 路板（Socket Board PCB)與插座連接器，用以固定積 體電路元件（1C)。待測元件，或以 DUT稱之）係插置於插座模組24上，為簡明起見，圖 二僅繪不兩個待測元件26A與26B，實則若以 Advantest 5 592/5 593測試機為例，則待測元件可為 64個、甚至咼達128個。由於圖二僅供示意之用， 表不測試頭20與共用電路模組22呈電性耦接、以及 共用電路模組22與插座模組24呈電性麵接。 由於待測兀件26A與26B的接腳（pin)概可區分 為輸入端（丨叫1^1^11)或輸入/輪出端（1/〇1)111)兩類。請 參照圖二，所不為應用於輸入端之習知測試裝置3的 電路不意圖。此應用於輸入端之習知測試裝置3係設 置於圖二測試治具1 6内，此測試裝置3主要包括一 驅動器（driver) 30，此驅動器3〇經由一接腳32 a連 接至待測元件26A某一輸入端，同時經由另一接腳 32 B連接至待測元件26β某一輸入端。換言之，待 測元件26A與26B均由驅動器3〇所驅動控制。 但是，DDR SDRAM記憶體的輸入/輸出端有4、 8、16位兀的差異，圖三之連接方式可適用於4個輸 入/輸出位το或8個輸入/輪出位元的ddr SDRAM記 憶體的測試，卻無法用於测試16個輸入/輸出位元的 DDR SDRAM記憶體。若於16位元之應用，即便需 6 1277747 如圖四將接腳3 2B浮接（floating)，也就是驅動器3 Ο 僅能對應於一個待測元件26Α。此時，由於浮接接腳 3 2 Β之阻抗（i m p e d a n c e)很大，驅動器3 0所傳輸的信 號將有明顯的反射效應（reflection)發生，影響測試的 準確性，而隨著信號的頻率越高，反射效應會更為嚴 〇 請參照圖五，所示為應用於輸入/輸出端之習知測 試裝置5的電路示意圖。此應用於輸入端之習知測試 裝置5係設置於圖二測試治具16内，此測試裝置5 主要包括：驅動器5 0、開關5 1、電阻5 2、電壓終端 器（v ο 11 a g e t e r m i n a 1) 5 3、比較器 5 4、開關 5 5、電阻 5 6、電壓終端器5 7等。驅動器5 0之輸入端接收測試 型樣（test pattern) PAT，輸出端經由輸入/輸出接腳 59A連接至待測元件26A。換言之，驅動器50僅對 應一個待測元件26A。開關5 1、電阻52、電壓終端 器53等串接於驅動器致能信號/DRE與接地點之間。 比較器54連接至輸入/輸出接腳59A，若有資料自輸 入/輸出接腳59A讀出時，比較器54會判別出此資料 為邏輯高準位或邏輯低準位。而開關5 5、電阻5 6、 電壓終端器5 7等係串接於比較器5 4輸入端與接地點 之間。當於寫入模式下，開關5 1和5 5經由OUTL信 號之控制呈關閉狀態，而致能信號/DRE為邏輯低準 位（logic low)，用以致能驅動器 50，致使驅動器50 輸出端輸出測試型樣信號 PAT ;同時致能信號/DRE 禁能開關5 8 ;當於讀取模式下，開關5 1和5 5經由 OUTL信號之控制呈開啟狀態，致能信號/DRE為邏輯 高準位（logic high)，禁能驅動器50、致能開關58， 使電阻 5 2和電壓終端器5 3耦接至輸入/輸出接腳 59A，由比較器54判別出此讀出資料為邏輯高準位與 7 1277747 邏輯低準位中之一者。同理，應用於待測元件 26B 之輸入/輸出端測試裝置亦與圖五所揭示者相同或類 似。換句話說，待測元件26A與26B無法共用同一 個驅動器。 習知有針對16位元DDR SDRAM記憶體者，另 外設計測試治具，則使用者（通常是記憶體元件製造 廠或測試廠）必須另行購買測試治具，以一套測試治 具動辄以新台幣數千萬元計，實則是種資源的耗費。 【發明内容】 本發明之主要目的係在提供一種半導體元件測 試裝置及其方法，僅需對原有的測試治具最些微的改 良，即可應用於4、8、或16位元輸入/輸出位元的半 導體元件測試，可以減省記憶體元件製造廠或測試廠 對於機器設備的投資成本。 為達成上述之目的，本發明可藉由提供一種半導 體元件測試裝置，來測試一待測元件。根據本發明之 測試裝置包括：一對輸入接腳，待測元件耦接至等輸 入接腳中之一者；一第一導線，係耦接於等輸入接腳 間；一第二導線，係耦接於等輸入接腳間；一驅動器， 經由一第三導線耦接至第一導線；以及一終端器，經 由一第四導線耦接至第二導線。 再者，本發明尚提供一種半導體元件測試裝置， 用以測試一待測元件。根據本發明之測試裝置包括： 一第一輸入/輸出接腳與一第二輸入/輸出接腳，待測 元件耦接至第一輸入/輸出接腳；一匯流排，具有複 數導線，等導線中之一者耦接於第一輸入/輸出接腳 與第二輸入/輸出接腳間；一驅動器，當於輸入模式 下耦接至第一輸入/輸出接腳；一第一終端器，當於 8 1277747 輸出模式下搞接至第一輸入/輸出接腳；一比較器， 耦接至第二輸入/輸出接腳；以及一第二終端器，當 於輸出模式下柄接至第二輸入/輸出接腳。 【實施方式】 為能讓 貴審查委員能更瞭解本發明之技術内 容，特舉若干較佳具體實施例說明如下。 請參照圖六，所示為根據本發明應用於輸入端之 測試裝置6的電路示意圖。此應用於輸入端之測試裝 置6係設置於圖二測試治具1 6内，此測試裝置6主 要包括一驅動器（driver) 60、電阻63、以及電壓終端 器64。此驅動器60之輸入端用以接收測試型樣信號 PAT、其輸出端經由導線61連接至導線62，導線61 與導線62連接處為節點620。電壓終端器64串接於 電阻6 3與接地點之間，而電阻6 3經由導線6 5連接 至導線6 6，導線6 5與導線6 6連接處為節點6 6 0。導 線62和66是並接於輸入接腳67A和67B間。導線 62區分為子導線621和622，分別連接至輸入接腳 67A和67B。導線66區分為子導線661和662，亦分 別連接至輸入接腳67A和67B。接腳67A連接至待 測元件26A某一輸入端，接腳67 B連接至待測元件 2 6B某一輸入端。換言之，待測元件26 A與26B均由 驅動器6 0所驅動控制。 因此，縱使DDR SDRAM記憶體的輸出端有4、8、 16位元的差異，當於4或8位元之應用，輸入接腳 67A和67B可分別插置待測元件26A和26B ;當於 16位元之應用，可使輸入接腳67A或67B浮接，如 圖六般將待測元件 26B移除即可。由於圖七之導線 62和66並接，並設置有電壓終端器64，若適當調整 9 1277747 導線61與6 5之阻抗，使與電阻6 3阻值或驅動器6 Ο 内阻值R相當，則將可大幅降低因輸入接腳67Β浮 接所產生的反射效應。較佳而言，子導線621與622 之長度相當、以及子導線661與662之長度相當的 話，能有同樣傳遞延遲（propagation delay)時間而可 降低反射效果；更佳而言，子導線621、622、661與 662約略相等。 請參照圖七，所示為根據本發明應用於輸入/輸出 端之測試裝置7的電路示意圖。此應用於輸入端之測 試裝置7係設置於圖二測試治具1 6内，此測試裝置 7主要包括：驅動器70、開關71、電阻72、電壓終 端器73、比較器74、開關75、電阻76、電壓終端器 7 7等。驅動器7 0之輸入端接收測試型樣（t e s t p a 11 e r η ) PAT，輸出端經由輸入/輸出接腳79A連接至待測元件 26A。開關71、電阻72、電壓終端器73等串接於驅 動器致能信號/DRE與接地點之間。比較器74連接至 輸入/輸出接腳79B。而開關75、電阻76、電壓終端 器77等係串接於比較器74輸入端與接地點之間。輸 入/輸出接腳79A與79B間，係以導線91 1予以連接。 當於寫入模式下，開關71和75經由OUTL信號之控 制呈關閉狀態，而致能信號/DRE呈邏輯低準位致能 驅動器7 0，致使驅動器7 0以輸出端輸出測試型樣信 號PAT，同時致能信號/DRE禁能開關78 ;當於讀取 模式下，開關7 1和75經由OUTL信號之控制呈開啟 狀態，致能信號/DRE呈邏輯高準位禁能驅動器70， 致能開關78，使電阻72與電壓終端器73耦接至輸 入/輸出接腳79A，而電阻76與電壓終端器77耦接 至輸入/輸出接腳79B，由比較器74判別出此讀出資 料為邏輯高準位與邏輯低準位中之一者。根據本發 1277747 明，驅動器70、開關71、電阻72以及電壓終端器 73設於靠近輸入/輸出接腳79A側，而比較器74、開 關7 5、電阻7 6、以及電壓終端器7 7設於靠近輸入/ 輸出接腳79B側。圖七中，待測元件26B係以虛線 繪示，表示此時輸入/輸出接腳79B所連接之待測元 件2 6B接腳為空腳。 請參照圖八，所示為根據本發明應用於輸入/輸出 端之測試裝置8的電路示意圖。此應用於輸入端之測 試裝置8係設置於圖二測試治具1 6内，此測試裝置 8主要包括：驅動器8 0、開關8 1、電阻8 2、電壓終 端器83、比較器84、開關85、電阻86、電壓終端器 8 7等。驅動器8 0之輸入端接收測試型樣（test pattern) PAT，輸出端經由輸入/輸出接腳89B連接至待測元件 2 6B。開關81、電阻82、電壓終端器83等串接於驅 動器致能信號/DRE與接地點之間。比較器84連接至 輸入/輸出接腳89A。而開關85、電阻86、電壓終端 器8 7等係串接於比較器84輸入端與接地點之間。輸 入/輸出接腳89A與89B間，係以導線921予以連接。 當於寫入模式下，開關81和85經由OUTL信號之控 制呈關閉狀態，而致能信號/DRE呈邏輯低準位致能 驅動器8 0，致使驅動器8 0以輸出端輸出測試型樣信 號PAT，同時致能信號/DRE禁能開關88 ;當於讀取 模式下，開關8 1和85經由OUTL信號之控制呈開啟 狀態，致能信號/DRE呈邏輯高準位禁能驅動器80， 致能開關88，使電阻82與電壓終端器83耦接至輸 入/輸出接腳89B，而電阻86與電壓終端器87耦接 至輸入/輸出接腳89A，由比較器84判別出此讀出資 料為邏輯高準位與邏輯低準位中之一者。根據本發 明，驅動器8 0、開關81、電阻8 2以及電壓終端器 1277747 83設於靠近輸入/輸出接腳89B側，而比較器84、開 關8 5、電阻8 6、以及電壓終端器8 7設於靠近輸入/ 輸出接腳89A側。圖八中，待測元件26A係以虛線 ' 繪示，表示此時輸入/輸出接腳89A所連接之待測元 ， 件26A接腳為空腳。 請參照圖九，所示為圖七與圖八之待測元件26A 與2 6 B的連接方式示意圖。如圖九所示，匯流排91 連接於待測元件26A之輸入/輸出端D[0:7]與待測元 件26B之輸入/輸出端D[8:15]之間，匯流排92連接 | 於待測元件26A之輸入/輸出端D[8:15]與待測元件 26B之輸入/輸出端 D[0:7]之間。更進一步說明，即 待測元件26A之輸入/輸出端D0、D1、D2、D3、D4、 D5、D6、D7分別連接至待測元件26B之輸入/輸出 端 D8、D9、DIO、Dll、D12、D13、D14、D15，而 待測元件26A之輸入/輸出端D8、D9、DIO、D11、 D 1 2、D 1 3、D 1 4、D 1 5分別連接至待測元件26B之輸 入 / 輸出端 DO、Dl、D2、D3、D4、D5、D6、D7。例 如：圖七所示之導線9 1 1屬於匯流排9 1中之一者， 可以是由待測元件26A之〇〇接腳連接至待測元件 . 2 6 B之D 8接腳，若此時待測元件2 6 A和2 6 B為4或 8位元者，D [ 8 : 1 5 ]為空腳位，故以虛線表示待測元件 2 6 B。又如圖八所示之導線9 2 1屬於匯流排9 2中之— 者，可以是由待測元件26A之D8接腳連接至待剛元 件26B之DO接腳，若此時待測元件26A和26B為4 或8位元者，D [ 8 : 1 5 ]屬空腳位，故以虛線表示待剩 元件26A。 請參照圖十，所示為待測元件26A和26B為16 位元時，D [ 8 : 1 5 ]不是空腳位，則待測元件2 6 A和2 6 B 必須擇一移除。如圖十，即便是將待測元件 26B移 1277747 除，僅供示例之用。 據此，縱使DDR SDRAM記憶體的輸丨 16位元的差異，當於4或8位元之應用 接腳79A/89A與79B/89B可分別插置待 和26B，即如圖九所示；當於16位元之 輸入/輸出接腳79A/89A或79B/89B —者 十般將待測元件26B移除即可。 綜上所陳，本發明無論就目的、手段 在均顯示其迥異於習知技術之特徵，懇1 委員明察，早曰賜准專利，俾嘉惠社會， 惟應注意的是，上述諸多實施例僅係為了 舉例而已，本發明所主張之權利範圍自應 範圍所述為準，而非僅限於上述實施例。 【圖式簡單說明】 圖一係顯示為應用於DDR SDRAM記憶體 1的不意圖， 圖二係顯示為圖一測試治具的示意圖； 圖三係顯示為應用於輸入端之習知測試 不意圖， 圖四係顯示將圖三某一接腳浮接的示意圖 圖五係顯示為應用於輸入/輸出端之習知 電路不意圖， 圖六係顯示根據本發明應用於輸入端之 電路不意圖， 1 3 ϋ端有4、8、 ，輸入/輸出 測元件26 A 應用，可使 浮接，如圖 及功效，在 青 貴審查 實感德便。 便於說明而 以申請專利 一測試系統 裝置的電路 測試裝置的 測試裝置的 1277747 圖七係顯示根據本發明應用於輸入/輸出端之測試裝 置的電路不意圖， 圖八係顯示根據本發明應用於輸入/輸出端之測試裝 置的電路示意圖； 圖九係顯示圖七與圖八之待測元件連接方式示意 圖；以及 圖十將圖九某一待測元件移除的不意圖。 【圖號說明】 10〜測試機；12、14〜測試站；16、18〜測試治具；20〜 測試頭；22〜共用電路模組；24〜插座模組；26A、26B〜 待測元件；32A/32B、67A/67B〜輸入接腳；59A、 79A/79B、89A/89B〜輸入 /輸出接腳；30、50、60、70、 80〜驅動器；51、55、58、71、75、78、81、85、88〜 開關；52、56、63、72、76、82、86〜電阻；53、57、 64、73、77、83、87〜電壓終端器；54、74、84〜比較 器；以及，9 1、9 2〜匯流排。1277747 玫, the invention description: [Technical Field of the Invention]: The present invention relates to a high-speed semiconductor component testing device: and a test method thereof. [Prior Art] DDR (Double Data Rate) SDRAM is a memory technology developed based on SDRAM. Unlike SDRAM synchronous random access memory, which supports only one data operation per computer clock cycle, DDR SDRAM can perform two data operations per clock cycle. Therefore, doubling the bandwidth of the billions also increases the amount of data transferred. Therefore, DDR SDRAM memory has been widely used in computer system platforms, including desktop computers, workstations, servers, notebook computers, portable computers, computer networks and communication products, and has become the mainstream product of memory technology. With the advancement of technology, the data rate of DDR SDRAM memory has been upgraded from 200/266MHz to 5 3 3/6 6 7MHz, and it is more likely to further increase to 800MHz/l.066GHz in the future. Therefore, the increase in frequency is also a difficult challenge for test technology. Referring to Figure 1, there is shown a schematic diagram of a test system 1 applied to a DDR SDRAM memory. As shown in FIG. 1 , the test system 1 mainly includes a test machine 10 . For example, the test machine 10 is an Advantest 5 592/5 593 test machine manufactured by Advantest, and is mainly used for generating a test type. For example (testpa 11 er η). This test machine 1 can be divided into several test stations. If the test machine 10 is an Advantest 5592/5593 test machine, two test stations 12 and 14 are provided. Each test station 12 and 14 is connected to individual test fixtures 16 and 18, respectively, as shown in Figure 1. 5 1277747 Please refer to Figure 2, which shows a schematic diagram of the test fixture 16. As shown in FIG. 2, the test fixture 16 includes a test head 20, a common motherboard 22, a socket board 24, and the like. The test head 20 has components such as drivers and comparators for signal driving and comparison. The shared circuit module 22 has a coaxial cable for connecting the circuit module 22 and the socket module 24. The socket module 24 has a socket board (PCB) and a socket connector for fixing the integrated circuit component (1C). The component to be tested, or DUT, is inserted into the socket module 24. For the sake of simplicity, only two components 26A and 26B to be tested are depicted in Fig. 2. In fact, the Advantest 5 592/5 593 tester is used. For example, the number of components to be tested can be 64 or even up to 128. As shown in FIG. 2, the test head 20 is electrically coupled to the shared circuit module 22, and the shared circuit module 22 is electrically connected to the socket module 24. Since the pins of the components 26A and 26B to be tested can be divided into two types: an input terminal (calling 1^1^11) or an input/rounding terminal (1/〇1) 111. Referring to Figure 2, the circuit of the conventional test device 3 applied to the input terminal is not intended. The conventional test device 3 applied to the input end is disposed in the test fixture 16 of FIG. 2. The test device 3 mainly includes a driver 30 connected to the test via a pin 32 a. An input of component 26A is coupled to an input of component under test 26β via another pin 32B. In other words, the elements to be tested 26A and 26B are both driven and controlled by the driver 3''. However, the input/output terminals of the DDR SDRAM memory have a difference of 4, 8, and 16 bits. The connection mode of Figure 3 can be applied to the ddr SDRAM memory of 4 input/output bits το or 8 input/round bits. The test was not able to test the DDR SDRAM memory of 16 input/output bits. For 16-bit applications, even if 6 1277747 is required to float the pin 3 2B as shown in Figure 4, the driver 3 Ο can only correspond to one component 26 to be tested. At this time, since the impedance of the floating pin 3 2 很大 is large, the signal transmitted by the driver 30 will have a significant reflection effect, which affects the accuracy of the test, and the frequency of the signal increases. High, the reflection effect will be more severe. Referring to Figure 5, a schematic circuit diagram of a conventional test device 5 applied to the input/output terminals is shown. The conventional test device 5 applied to the input end is disposed in the test fixture 16 of FIG. 2. The test device 5 mainly includes: a driver 50, a switch 5 1 , a resistor 5 2, and a voltage terminator (v ο 11 agetermina 1 5 3, comparator 5 4, switch 5 5, resistor 5 6, voltage terminator 5 7 and so on. The input terminal of the driver 50 receives the test pattern PAT, and the output terminal is connected to the device under test 26A via the input/output pin 59A. In other words, the driver 50 corresponds to only one of the elements 26 to be tested. The switch 5 1 , the resistor 52 , the voltage terminator 53 , and the like are connected in series between the driver enable signal /DRE and the ground. The comparator 54 is connected to the input/output pin 59A. If data is read from the input/output pin 59A, the comparator 54 determines whether the data is a logic high level or a logic low level. The switch 5 5 , the resistor 5 6 , the voltage terminator 5 7 , etc. are connected in series between the input end of the comparator 54 and the ground point. In the write mode, switches 5 1 and 5 5 are turned off via the control of the OUTL signal, and the enable signal /DRE is logic low to enable the driver 50 to cause the output of the driver 50 output. Test pattern signal PAT; simultaneous enable signal / DRE disable switch 5 8; when in read mode, switches 5 1 and 5 5 are turned on via OUTL signal control, enable signal / DRE is logic high level (logic high), the disable driver 50, the enable switch 58, the resistor 52 and the voltage terminator 53 are coupled to the input/output pin 59A, and the comparator 54 determines that the read data is a logic high level. One of the logical low levels with 7 1277747. Similarly, the input/output terminal test device applied to the device under test 26B is also the same as or similar to that disclosed in FIG. In other words, the elements to be tested 26A and 26B cannot share the same driver. It is known that for 16-bit DDR SDRAM memory, in addition to designing test fixtures, users (usually memory component manufacturers or test plants) must purchase test fixtures separately, with a set of test fixtures. The NT$10 million is actually the cost of resources. SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor device testing device and method thereof, which can be applied to 4, 8, or 16 bit input/output only with the slightest improvement of the original test fixture. The semiconductor component testing of the bit can reduce the investment cost of the memory component manufacturer or tester for the machine equipment. To achieve the above object, the present invention can test a device under test by providing a semiconductor component testing device. The test device according to the present invention includes: a pair of input pins, the device to be tested is coupled to one of the input pins; a first wire is coupled between the input pins; and a second wire is Coupled between the input pins; a driver coupled to the first wire via a third wire; and a terminator coupled to the second wire via a fourth wire. Furthermore, the present invention further provides a semiconductor component testing apparatus for testing a component to be tested. The testing device according to the present invention comprises: a first input/output pin and a second input/output pin, the device under test is coupled to the first input/output pin; a bus bar having a plurality of wires, etc. One of the two is coupled between the first input/output pin and the second input/output pin; a driver coupled to the first input/output pin when in the input mode; a first terminator Connected to the first input/output pin in the 8 1277747 output mode; a comparator coupled to the second input/output pin; and a second terminator connected to the second input in the output mode / Output pin. [Embodiment] In order to enable the reviewing committee to better understand the technical contents of the present invention, a number of preferred embodiments will be described below. Referring to Figure 6, there is shown a circuit diagram of a test apparatus 6 applied to an input terminal in accordance with the present invention. The test device 6 applied to the input terminal is disposed in the test fixture 16 of Fig. 2. The test device 6 mainly includes a driver 60, a resistor 63, and a voltage terminator 64. The input of the driver 60 is for receiving the test pattern signal PAT, the output thereof is connected to the wire 62 via the wire 61, and the wire 61 is connected to the wire 62 as the node 620. The voltage terminator 64 is connected in series between the resistor 63 and the ground point, and the resistor 63 is connected to the wire 6 via the wire 65, and the junction of the wire 6 5 and the wire 66 is the node 6 60. Wires 62 and 66 are connected in parallel between input pins 67A and 67B. The wires 62 are divided into sub-wires 621 and 622 which are connected to the input pins 67A and 67B, respectively. The wires 66 are divided into sub-wires 661 and 662, which are also connected to input pins 67A and 67B, respectively. The pin 67A is connected to an input terminal of the device to be tested 26A, and the pin 67B is connected to an input terminal of the device to be tested 26B. In other words, the elements to be tested 26 A and 26B are both driven and controlled by the driver 60. Therefore, even if the output of the DDR SDRAM memory has a difference of 4, 8, or 16 bits, when applied to 4 or 8 bits, the input pins 67A and 67B can respectively insert the elements 26A and 26B to be tested; For 16-bit applications, the input pins 67A or 67B can be floated, and the device under test 26B can be removed as shown in FIG. Since the wires 62 and 66 of FIG. 7 are connected in parallel and the voltage terminator 64 is provided, if the impedance of the wires 9 and 17 5 of the 9 1277747 is appropriately adjusted so as to be equivalent to the resistance of the resistor 63 or the internal resistance R of the driver 6 The reflection effect caused by floating of the input pin 67Β can be greatly reduced. Preferably, if the lengths of the sub-wires 621 and 622 are equivalent, and the lengths of the sub-wires 661 and 662 are equivalent, the same propagation delay time can be used to reduce the reflection effect; more preferably, the sub-wire 621, 622, 661 and 662 are approximately equal. Referring to Figure 7, there is shown a circuit diagram of a test apparatus 7 applied to an input/output terminal in accordance with the present invention. The test device 7 applied to the input end is disposed in the test fixture 16 of FIG. 2. The test device 7 mainly includes: a driver 70, a switch 71, a resistor 72, a voltage terminator 73, a comparator 74, a switch 75, and a resistor. 76, voltage terminator 7 7 and so on. The input terminal of the driver 70 receives the test pattern (t e s t p a 11 e r η ) PAT, and the output terminal is connected to the device under test 26A via the input/output pin 79A. The switch 71, the resistor 72, the voltage terminator 73, and the like are connected in series between the driver enable signal /DRE and the ground. The comparator 74 is connected to the input/output pin 79B. The switch 75, the resistor 76, the voltage terminator 77, and the like are connected in series between the input terminal of the comparator 74 and the ground. Between the input/output pins 79A and 79B, the wires 91 1 are connected. When in the write mode, the switches 71 and 75 are turned off via the control of the OUTL signal, and the enable signal /DRE is enabled to the logic low level enable driver 70, causing the driver 70 to output the test pattern signal PAT at the output. At the same time, the enable signal/DRE disable switch 78; when in the read mode, the switches 7 1 and 75 are turned on by the control of the OUTL signal, and the enable signal /DRE is in the logic high level disable driver 70, enabling The switch 78 couples the resistor 72 and the voltage terminator 73 to the input/output pin 79A, and the resistor 76 and the voltage terminator 77 are coupled to the input/output pin 79B. The comparator 74 determines that the read data is One of the logic high level and the logic low level. According to the present invention, the driver 70, the switch 71, the resistor 72, and the voltage terminator 73 are disposed on the side close to the input/output pin 79A, and the comparator 74, the switch 75, the resistor 76, and the voltage terminator 7 7 are provided. Close to the input/output pin 79B side. In Figure 7, the component to be tested 26B is shown by a broken line, indicating that the component to be tested 2 6B connected to the input/output pin 79B is an empty pin. Referring to Figure 8, there is shown a circuit diagram of a test apparatus 8 applied to an input/output terminal in accordance with the present invention. The test device 8 applied to the input end is disposed in the test fixture 16 of FIG. 2. The test device 8 mainly includes: a driver 80, a switch 8 1 , a resistor 8 2, a voltage terminator 83, a comparator 84, and a switch. 85, resistor 86, voltage terminator 8 7 and so on. The input terminal of the driver 80 receives the test pattern PAT, and the output terminal is connected to the device under test 2 6B via the input/output pin 89B. The switch 81, the resistor 82, the voltage terminator 83, and the like are connected in series between the driver enable signal /DRE and the ground. Comparator 84 is coupled to input/output pin 89A. The switch 85, the resistor 86, the voltage terminator 8 7 and the like are connected in series between the input terminal of the comparator 84 and the grounding point. Between the input/output pins 89A and 89B, the wires 921 are connected. In the write mode, the switches 81 and 85 are turned off via the control of the OUTL signal, and the enable signal /DRE is enabled in the logic low level enable driver 80, causing the driver 80 to output the test pattern signal PAT at the output. At the same time, the enable signal/DRE disable switch 88; when in the read mode, the switches 8 1 and 85 are turned on by the control of the OUTL signal, and the enable signal /DRE is in the logic high level disable driver 80, enabling The switch 88 couples the resistor 82 and the voltage terminator 83 to the input/output pin 89B, and the resistor 86 and the voltage terminator 87 are coupled to the input/output pin 89A. The comparator 84 determines that the read data is One of the logic high level and the logic low level. According to the present invention, the driver 80, the switch 81, the resistor 8 2, and the voltage terminator 1277747 83 are disposed on the side close to the input/output pin 89B, and the comparator 84, the switch 85, the resistor 86, and the voltage terminator 8 7 Set to the side close to the input/output pin 89A. In Fig. 8, the component to be tested 26A is indicated by a broken line ', indicating the element to be tested to which the input/output pin 89A is connected at this time, and the leg of the piece 26A is an empty pin. Referring to FIG. 9, a schematic diagram of the connection manner of the components 26A and 26B to be tested in FIG. 7 and FIG. As shown in FIG. 9, the bus bar 91 is connected between the input/output terminal D[0:7] of the device under test 26A and the input/output terminal D[8:15] of the device under test 26B, and the bus bar 92 is connected | Between the input/output terminal D[8:15] of the device under test 26A and the input/output terminal D[0:7] of the device under test 26B. Further, the input/output terminals D0, D1, D2, D3, D4, D5, D6, and D7 of the device under test 26A are respectively connected to the input/output terminals D8, D9, DIO, D11, and D12 of the device to be tested 26B. D13, D14, D15, and the input/output terminals D8, D9, DIO, D11, D1 2, D1 3, D1 4, D 1 5 of the device under test 26A are respectively connected to the input of the element to be tested 26B/ Output terminals DO, Dl, D2, D3, D4, D5, D6, D7. For example, the wire 9 1 1 shown in FIG. 7 belongs to one of the bus bars 9 1 , and may be connected to the device to be tested by the connecting pin of the component to be tested 26A. The D 8 pin of the 2 6 B, if When the components to be tested 2 6 A and 2 6 B are 4 or 8 bits, D [ 8 : 15 ] is an empty pin, so the element to be tested 2 6 B is indicated by a broken line. The wire 9 2 1 shown in FIG. 8 belongs to the bus bar 9 2 , and may be a DO pin connected to the D8 pin of the component 26A to be tested, and the component to be tested 26A at this time. And 26B is 4 or 8 bits, and D [8:15] is an empty pin, so the remaining component 26A is indicated by a broken line. Referring to FIG. 10, when the components to be tested 26A and 26B are 16 bits, and D [8:15] is not an empty pin, the components to be tested 2 6 A and 2 6 B must be removed. As shown in Figure 10, even if the component to be tested 26B is moved 1277747, it is for example only. Accordingly, even if the DDR SDRAM memory has a difference of 16 bits, when the 4 or 8 bit application pins 79A/89A and 79B/89B can be respectively inserted and 26B, as shown in FIG. When the 16-bit input/output pin 79A/89A or 79B/89B is used, the element to be tested 26B is removed. To sum up, the present invention shows its characteristics different from those of the prior art in terms of purpose and means. Members of the Committee are aware of the patents granted to them, and they should pay attention to the above-mentioned embodiments. The scope of the claims is intended to be limited only by the scope of the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic view showing the application to the DDR SDRAM memory 1. Figure 2 is a schematic diagram showing the test fixture of Figure 1. Figure 3 is a schematic view showing the application to the input. FIG. 4 is a schematic diagram showing the schematic diagram of floating a certain pin of FIG. 3 as a conventional circuit applied to the input/output terminal. FIG. 6 is a schematic diagram showing the circuit applied to the input terminal according to the present invention. 1 3 The end has 4, 8, and the input/output measuring component 26 A application can make the floating connection, as shown in the figure and the effect, in the Qinggui review real feelings. 1277747, which is a test device for a circuit test device of a patent application test system device, is shown in FIG. 7 is a circuit diagram showing a test device applied to an input/output terminal according to the present invention, and FIG. 8 is a diagram showing application to an input according to the present invention. FIG. 9 is a schematic diagram showing the connection mode of the device to be tested in FIG. 7 and FIG. 8; and FIG. 10 is a schematic view showing the removal of a component to be tested in FIG. [Description of the number] 10~ test machine; 12, 14~ test station; 16, 18~ test fixture; 20~ test head; 22~ shared circuit module; 24~ socket module; 26A, 26B~ ; 32A/32B, 67A/67B~ input pin; 59A, 79A/79B, 89A/89B~ input/output pin; 30, 50, 60, 70, 80~ driver; 51, 55, 58, 71, 75 , 78, 81, 85, 88~ switch; 52, 56, 63, 72, 76, 82, 86~ resistor; 53, 57, 64, 73, 77, 83, 87~ voltage terminator; 54, 74, 84 ~ Comparator; and, 9 1, 9 2 ~ bus.