TW201939511A - Memory testing device and memory testing method using the same - Google Patents

Abstract

A memory testing device and a memory testing method using the same is disclosed. The memory testing device is used to test a memory. The memory has a plurality of first I/O pins and a plurality of second I/O pins. The memory testing device includes a first wiring bus, an I/O bus, an I/O tester module bus, and a second wiring bus. The plurality of first I/O pins are electrically and parallelly connected to the first wiring bus. The first wiring bus is electrically connected to the I/O bus. The first wiring bus is electrically and parallelly connected to the I/O tester module bus through the I/O bus. There are nodes between the first wiring bus and the I/O bus. The plurality of second I/O pins are electrically and parallelly connected to the nodes through the second wiring bus.

Description

Memory test device and test method

The invention relates to a testing technology, in particular to a memory testing device and a testing method thereof.

The memory system is designed and assembled into various electronic products, like double data rate (DDR) synchronous dynamic random access memory (SDRAM) is one of the dynamic random access memory (DRAM), which can support double Data rate, that is, data is transmitted on the rising and falling edges of the DQ data strobe frequency (DQS) signal to increase the data rate. With the progress of technology, DDR SDRAM has developed into DDR2 and DDR3, and even DDR4. Its data rate has increased from 166/200 MHz (333/400 Mbps) of DDR to 400 MHz / 800 Mbps of DDR2, exceeding 666MHz / of DDR3 1.333 Gbps, even higher data rates in the near future. As the frequency increases, the test machine needs a higher test speed to test the corresponding memory.

For example, the Advantest T5503 tester produced by Advantest can supply multiple DUTs to test in parallel and generate the required test pattern signals. The test equipment must be specially designed and implemented to transmit and read data. Fetch operations to access DUTs. Generally, a test device includes a test head, a common motherboard, and a socket module. The test head has different components, such as a driver for driving signals and a comparator for comparing signals. The common motherboard has wiring, such as a coaxial cable or a printed circuit board, for electrically connecting the circuit module and the socket module. The socket module includes a printed circuit board, which has a plurality of sockets, and is tested by physically loading and electrically connecting the DUTs. Generally, the common motherboard and the socket module can be integrated into a single component. As shown in Figure 1, a conventional test device includes two test structures for testing a memory 10 with 16 I / O pins of DQ 0-7 and DQ 8-15. Each test structure It includes an I / O module bus 12, a terminal module bus 14, an I / O bus 16 and a terminal bus 18. The I / O pins of DQ 0 ~ 7 are connected to one of the I / O buses 16, and the I / O pins of DQ 8 ~ 15 are connected to the other I / O bus 16, the two I / O buses The bus 16 is connected to the two I / O module buses 12 respectively. In other words, the conventional technique requires two test structures to test a single 16-bit memory. If there are 256 16-bit memories to be tested, 512 test structures are required. These test structures are usually purchased by memory manufacturers or test houses, but because a device can cost more than a million dollars, a complete set of test equipment is considered rather uneconomical.

In order to overcome the above problems, the present invention provides a memory testing device and a testing method thereof, so as to solve the shortcomings of the conventional technology.

The main purpose of the present invention is to provide a memory test device and a test method thereof, which electrically connect the first wire bus and the second wire bus to the same I / O bus. Compared with the prior art, the present invention doubles the production amount of test memory, such as 16-bit memory or 32-bit memory, and reduces the equipment investment cost of memory manufacturers and test institutions.

To achieve the above object, the present invention provides a memory testing device for testing a memory, and the memory has a plurality of first I / O pins and a plurality of second I / O pins. The memory testing device includes There is a first wire bus, an I / O bus, an I / O tester module bus, and a second wire bus. The first wire bus is electrically connected to the first I / O pins in parallel, and the I / O bus is electrically connected to the first wire bus. The plurality of nodes are located between the first wire bus and the I / O bus, for example, one node is located between a pin of the first wire bus and a channel of the corresponding I / O bus. The I / O tester module bus is electrically connected to the first wire bus in parallel through the I / O bus, the second wire bus is connected in parallel to the node and the second I / O pins.

In one embodiment of the present invention, the memory test device further includes a terminal module bus, which is electrically connected side by side to the I / O bus through a terminal bus.

In one embodiment of the present invention, the I / O tester module bus is adjacent to the terminal module bus.

In an embodiment of the present invention, the first wire bus further includes a plurality of first conductive wires, the second wire bus further includes a plurality of second conductive wires; the I / O bus bar further includes a plurality of I / O conductive wires, and the terminal The bus further includes a plurality of terminal conductive wires, the I / O tester module bus further includes a plurality of I / O tester modules, and the terminal module bus further includes a plurality of terminal modules; the node, the first I / O O pins, the second I / O pins, the first conductive wires, the second conductive wires, the I / O conductive wires, the terminal conductive wires, and the I / O test machine modules The number of groups and these terminal modules is equal.

In one embodiment of the present invention, the first conductive lines of the first conductive line bus and the second conductive lines of the second conductive line bus are both the same length.

In one embodiment of the present invention, the number of the first I / O pins is eight, and the number of the second I / O pins is also eight.

In one embodiment of the present invention, four of the first I / O pins are activated and the other four are deactivated, and the second I / O pins are all Is disabled.

In one embodiment of the present invention, the first I / O pins and the second I / O pins are both enabled.

In one embodiment of the invention, the first I / O pins are enabled and the second I / O pins are disabled.

In one embodiment of the present invention, the aforementioned I / O tester module further includes an I / O driver and an I / O receiver. The I / O driver is electrically connected to a control terminal and the I / O conductive line of the I / O bus, and the control terminal receives a drive enable signal or a drive disable signal. When the I / O driver receives the drive through the control terminal When the enable signal is enabled, the I / O driver uses the I / O conductive line that drives the enable signal and passes through the I / O bus, the first conductive line of the first conductive bus, and the second conductive line of the second conductive bus. A test pattern signal is transmitted to the first I / O pin and the second I / O pin of the memory; when the I / O driver receives the driving disable signal through the control terminal, the I / O driver uses the driving disable signal To stop transmitting the test pattern signal. The above I / O receiver is electrically connected to the I / O conductive line of the I / O bus, and passes through the first I / O pin, the second I / O pin, and the first conductive line of the first wire bus The second conductive line of the second wire bus and the I / O conductive line of the I / O bus read the data of the memory.

In one embodiment of the present invention, the terminal module further includes an electronic switch, a voltage source, and a resistor. The electronic switch is electrically connected to the control terminal and the terminal conductive wire of the terminal bus; the voltage source is provided with a direct current (DC) power supply; the resistance is electrically connected between the voltage source and the electronic switch. When the electronic switch receives the drive through the control terminal When the enable signal is enabled, the drive enable signal closes the electronic switch, so that the voltage source is not connected to the terminal conductive wire of the terminal bus; and when the electronic switch receives the drive disable signal through the control terminal, the drive disable signal turns on the electronic switch , So that the voltage source is electrically connected to the terminal conductive line of the terminal bus.

In one embodiment of the present invention, the memory system is a synchronous dynamic random access memory (SDRAM), double data rate (DDR), DDR2, DDR3, DDR4, or low-power DDR4.

The invention also provides a memory test method. First, a memory is provided. The memory has a plurality of first I / O pins and a plurality of second I / O pins. The first I / O pins pass through a first wire bus and an I / O. The bus is electrically connected to the corresponding I / O tester module bus, and the second I / O pins are electrically connected to the corresponding I / O through a second wire bus and the I / O bus. O tester module bus; when a write mode is tested, a test pattern signal is transmitted from the I / O tester module bus to the first I / O pins and the second I / O pins of the memory O pin. When testing a read mode, the I / O tester module bus is used to read the data of the memory from the first I / O pins and the second I / O pins.

In one embodiment of the present invention, the I / O tester module bus described above reads data from the memory at the same time.

In one embodiment of the present invention, the I / O tester module bus described above sequentially reads the memory data according to the two chip select (CS) signals.

In one embodiment of the present invention, the I / O bus is electrically connected to a terminal module bus through a terminal bus.

As in one embodiment of the present invention, the I / O tester module bus is adjacent to the terminal module bus.

In an embodiment of the present invention, the first wire bus further includes a plurality of first conductive wires, the second wire bus further includes a plurality of second conductive wires, the I / O bus bar further includes a plurality of I / O conductive wires, and the terminal The bus bar further includes a plurality of terminal conductive wires, the I / O test machine module bus further includes a plurality of I / O test machine modules, and the terminal module bus further includes a plurality of terminal modules. The first I / O pins, the second I / O pins, the first conductive wires, the second conductive wires, the I / O conductive wires, the terminal conductive wires, the The number of I / O tester modules and these terminal modules are equal.

In one embodiment of the present invention, the number of the first I / O pins is eight, and the number of the second I / O pins is also eight.

In one embodiment of the present invention, the memory may be a synchronous dynamic random access memory (SDRAM), double data rate (DDR), DDR2, DDR3, DDR4, or low-power DDR4.

In the following, detailed descriptions are provided by specific embodiments in conjunction with the accompanying drawings to make it easier to understand the purpose, technical content, and effects achieved by the present invention.

The accompanying drawings are used to explain the embodiments of the present invention in detail. These drawings are simplified schematic diagrams, and only the structure or method is used to illustrate the related elements and combination relationships of the present invention. Therefore, the elements shown in the drawings It is not based on the actual implementation of the number, shape, size and other proportions. Some dimensions and other related dimensions are exaggerated or simplified to provide a clearer description. The actual implementation of the number, shape or size ratio can be optional design and configuration, and the detailed component layout may be more complicated.

According to an embodiment of the present invention, a memory test device is proposed, in which different input / output (I / O) devices or test modules are respectively shown in FIG. 2, FIG. 5, and FIG. 6. Referring to FIG. 2, a memory testing device for testing a memory 20 is implemented in a test fixture. The memory 20 includes, but is not limited to, a synchronous dynamic random access memory (SDRAM), a Double data rate (DDR), a DDR2, a DDR3, a DDR4, or a low-power DDR4 memory. The memory 20 has a plurality of first input / output (I / O) pins DQ 0 to 7 and a plurality of second I / O pins DQ 8 to 15. In the exemplary embodiment, the first The number of I / O pins DQ 0 to 7 is eight, and the number of the second I / O pins DQ 8 to 15 is eight. These first I / O pins DQ 0 to 7 and the first Two I / O pins DQ 8 ~ 15, so that the first I / O pins DQ 0 ~ 7 and the second I / O pins DQ 8 ~ 15 are electrically connected to a die of the memory 20 . The memory test device includes a first wire bus 22, an I / O bus 24, an I / O tester module bus 26, a second wire bus 28, and a terminal module bus (terminator bus 30 and a terminating bus 32. The first I / O pins DQ 0 ~ 7 are electrically connected to the first wire bus 22, and the second I / O pins DQ 8 ~ 15 are electrically connected to the second wire bus 28, The first wire bus 22 is electrically connected to the I / O bus 24, and both the first wire bus 22 and the second wire bus 24 are electrically connected in parallel to the 8-node 34, and the 8-node 34 is connected through I The / O bus 24 is electrically connected in parallel to the I / O tester module bus 26, and the I / O bus is electrically connected in parallel to the terminal module bus 30 through the terminal bus 32. In the exemplary embodiment, the I / O tester module bus 26 is adjacent to the terminal module bus 30 to effectively shorten the length of the terminal bus 32.

The first wire bus 22 includes a plurality of first conductive wires, the second wire bus 28 includes a plurality of second conductive wires, the I / O bus 24 includes a plurality of I / O conductive wires, and the terminal bus 32 includes A plurality of terminal conductive wires, the I / O tester module bus 26 includes a plurality of I / O tester modules 36, and the terminal module bus 30 includes a plurality of terminal modules 38, the I / O testers The module 36 and the terminal module 38 are hardware circuits. Each I / O tester module includes an I / O driver 40 and an I / O receiver 42. Each terminal module 38 includes an electronic switch 46, a voltage source 48 and a resistor 50. The nodes 34, the first I / O pins DQ 0 to 7, the second I / O pins DQ 8 to 15, the first conductive wires and the second wires of the first wire bus 22 The second conductive lines of the bus 28, the I / O conductive lines of the I / O bus 24, the terminal conductive lines of the terminal bus 32, the I / O tester modules 36, and the The number of terminal modules is equal to each other.

The I / O driver 40 is an I / O conductive line electrically connected to a control terminal 44 and the I / O bus bar 24. The control terminal 44 can receive a driving enable signal E or a driving disable signal D. When the I / O driver 40 receives the driving enable signal E through the control terminal 44, the I / O driver 40 uses the driving enable signal E to receive and transmit a test pattern signal PAT to the first I / O interface of the memory 20. One of pins DQ 0 ~ 7 and second I / O pins DQ 8 ~ 15; the transmission of the test pattern signal PAT is through the I / O conductive wire of the I / O bus 24 and the first wire bus 22 The first conductive line and the second conductive line of the second wire bus 28. In this embodiment, the first conductive line of the first wire bus 22 and the second conductive line of the second wire bus 28 have the same length to achieve the same timing skew. Therefore, from I The test pattern signal PAT sent from the / O tester module bus 26 can be received by the I / O pins DQ 0 ~ 7 and DQ 8 ~ 15 at the same time without time delay to achieve signal synchronization. When the I / O driver 40 receives the driving disable signal D through the control terminal 44, the I / O driver uses the driving disable signal D to stop transmitting the test pattern signal PAT. The I / O receiver 42 is electrically connected to the I / O conductive line of the I / O bus 24, and passes through one of the first I / O pins DQ 0 to 7, and the second I / O pin DQ 8 to 15 One, the first conductive line of the first wire bus 22, the second conductive line of the second wire bus 28, and the I / O line of the I / O bus 24 to read the data of the memory 20.

The electronic switch 46 is electrically connected to the control terminal 44 and the terminal conductive wire; the voltage source 48 is provided with a direct current (DC) power source; the resistor 50 is electrically connected between the voltage source 48 and the electronic switch 46. When the electronic switch 46 receives the driving enable signal E through the control terminal 44, the driving enable signal E will turn off the electronic switch 46, so that the voltage source 48 is not connected to the terminal conductive line of the terminal bus 32; When the terminal 44 receives the driving disabling signal D, the driving disabling signal D turns on the electronic switch 46 so that the voltage source 48 is electrically connected to the terminal conductive line of the terminal bus 32.

The following describes the memory test method operated by the memory test device. First, a memory 20 is provided. The first I / O pins DQ 0 to 7 are electrically connected to the corresponding I / O tester module bus through the first wire bus 22 and the I / O bus 24. 26, and the second I / O pins DQ 8 to 15 are electrically connected to the corresponding I / O tester module bus 26 through the second wire bus 28 and the I / O bus 24.

When testing the x16 write mode, the I / O driver 40 receives the driving enable signal E through the control terminal 44 and transmits the test pattern signal PAT from the I / O driver 40 of the I / O tester module bus 26 to the memory 20 For the first I / O pins DQ 0 to 7 and the second I / O pins DQ 8 to 15, the test pattern signal PAT will be written into the memory 20. When the electronic switch 46 receives the driving enable signal E through the control terminal 44, the driving enable signal E will turn off the electronic switch 46, so that the voltage source 48 is not connected to the terminal conductive line of the terminal busbar 32.

When testing the x16 read mode, a chip select (CS) signal in the memory is activated, and the I / O driver 40 receives the driving disabling signal D through the control terminal 44 to stop transmitting the test pattern signal PAT. At this time, from these The data of the memory 20 of the first I / O pins DQ 0 ~ 7 and the second I / O pins DQ 8 ~ 15 will be synchronized by the I / O receiver 42 of the I / O tester module bus 26. Read. When the electronic switch 46 receives the driving disabling signal D through the control terminal 44, the driving disabling signal D turns on the electronic switch 46, so that the voltage source 48 is electrically connected to the terminal conductive line of the terminal bus bar 32.

Alternatively, another x16 read mode can be selected. The memory 20 includes two sub-memories electrically connected to the first I / O pins DQ 0 to 7 and the second I / O pins DQ 8 to 15 respectively. In another x16 reading mode, the two chip selection signals respectively set in the two sub-memory of this memory 20 will be sequentially activated, and the I / O driver 40 receives the driving disabling signal D through the control terminal 44 to stop Send the test pattern signal PAT. According to the two chip selection signals, the data of the memory 20 will be sequentially read by the I / O receiver 42 of the I / O tester module bus 26. When the electronic switch 46 receives the driving disabling signal D through the control terminal 44, the driving disabling signal D turns on the electronic switch 46, so that the voltage source 48 is electrically connected to the terminal conductive line of the terminal bus bar 32. Under this condition, the I / O receiver 42 of the I / O tester module bus 26 will read the data of one of the sub-memory through the first I / O pins DQ 0 ~ 7. After that, I The I / O receiver 42 of the I / O tester module bus 26 will read the data of another sub-memory through the second I / O pins DQ 8 ~ 15.

The present invention electrically connects the first wire bus 22 and the second wire bus 28 to the same I / O bus 24, and uses the same test fixture to test a single 16-bit memory. If there are 256 16-bit memories to be tested, the present invention requires 256 test fixtures. Compared with the general technology of FIG. 1, the present invention doubles the through-put of the test memory and reduces the equipment investment cost of the memory manufacturer or the test organization.

In this embodiment, the memory 20 has eight I / O circuits, and each I / O circuit is electrically connected to a first I / O pin and a second I / O pin respectively. Take the first I / O pin DQ 0 and the second I / O pin DQ 8 as examples. Please refer to FIG. 3 and FIG. 4, the first I / O pin DQ 0 and the second I / O Pin DQ 8 is electrically connected to an I / O circuit 52. The I / O circuit 52 includes a first P-channel metal oxide semiconductor field effect transistor (PMOSFET) 54, a first resistor 56, a second resistor 58, A first N-channel metal oxide semiconductor field effect transistor (NMOSFET) 60, a second PMOSFET 62, a third resistor 64, a fourth resistor 66, and a second NMOSFET 68. The base and source of each of the first PMOSFET 54, the first NMOSFET 60, the second PMOSFET 62, and the second NMOSFET 68 are electrically connected to each other, and the gates of the first PMOSFET 54 and the first NMOSFET 60 are electrically connected together The gates of the second PMOSFET 62 and the second NMOSFET 68 are also electrically connected together. The sources of the first PMOSFET 54 and the second PMOSFET 62 are electrically connected to the high voltage VDDQ, the source of the first NMOSFET 60 and the second NMOSFET 68. The pole is grounded. The first I / O pin DQ 0 is electrically connected to the drain of the first PMOSFET 54, the first resistor 56, the second resistor 58, and the drain of the first NMOSFET 60, and the second I / O pin DQ 80 is electrically Connected to the drain of the second PMOSFET 62, the third resistor 64, the fourth resistor 66, and the drain of the second NMOSFET 68. The first I / O pin DQ 0 and the second I / O pin DQ 8 are electrically connected to the voltage source 48 through a resistor 50 and electrically to the I / O receiver 42. The voltage source 48 has VDDQ / 2 DC voltage, but the present invention is not limited to this. The voltage source 48 may selectively have a DC voltage of VDDQ or a terminal voltage. The I / O receiver 42 includes two comparators 70, which are electrically connected to the first I / O pin DQ 0 and the second I / O pin DQ 8. The comparators 70 each receive a high-level voltage VH. And a low level voltage VL.

Regardless of the I / O receiver 42, the voltage source 48, and the resistor 50, the data independently selected from the first I / O pin DQ 0 and the second I / O pin DQ 8 can be logic high levels, Logic low level or tri-state logic level. The first I / O pin DQ 0 and the second I / O pin DQ 8 can output a test voltage VN to the I / O receiver 42. The test voltage VN can be one of V1, V2, V3, V4, and V5. One is transmitted to the I / O receiver 42. When the first I / O pin DQ 0 and the second I / O pin DQ 8 have two logic high outputs correspondingly, the test voltage VN can be a voltage V1; when the first I / O pin DQ 0 and The second I / O pin DQ 8 has a logic high output and a high impedance output correspondingly. The test voltage VN can be a voltage V2. When the first I / O pin DQ 0 and the second I / O pin DQ 8 Correspondingly has a logic high output and a logic low output. The test voltage VN can be a voltage V3. When the first I / O pin DQ 0 and the second I / O pin DQ 8 have a corresponding logic low output and high Impedance output, the test voltage VN can be voltage V4; when the first I / O pin DQ 0 and the second I / O pin DQ 8 have two logic low outputs correspondingly, the test voltage VN can be a voltage V5 . The comparator 70 compares the test voltage VN with the high-level voltage VH and the low-level voltage VL to generate a first signal S1 and a second signal S2. The I / O receiver 42 may generate a first signal S1 and a second signal S2. The two signals S2 determine the logic states of the first I / O pin DQ 0 and the second I / O pin DQ 8.

Please refer to FIG. 5. When the first I / O pins DQ 0 to 7 are enabled and the second I / O pins DQ 8 to 15 are disabled, the memory test device of the present invention can Implemented in x8 I / O devices or test mode. The first I / O pins DQ 0 to 7 are electrically connected to the memory 20, and the second I / O pins DQ 8 to 15 are not electrically connected to the memory 20, as shown in FIG. 5. It is shown that the second wire bus 28 is drawn with a dashed line, and the second I / O pins DQ 8 to 15 corresponding to the memory 20 are shielded.

In the x8 write mode, the I / O driver 40 receives the driving enable signal E through the control terminal 44 and transmits the test pattern signal PAT from the I / O driver 40 of the I / O tester module bus 26 to the memory 20 The first I / O pins DQ 0 ~ 7, and then the test pattern signal PAT is written into the memory 20. When the electronic switch 46 receives the driving enable signal E through the control terminal 44, the driving enable signal E will turn off the electronic switch 46, so that the voltage source 48 is not connected to the terminal conductive line.

In the x8 read mode, the I / O driver 40 receives the driving disabling signal D through the control terminal 44 to stop transmitting the test pattern signal PAT from the memory 20 data of the first I / O pins DQ 0 ~ 7 It will be read by the I / O receiver 42 of the I / O tester module bus 26. The electronic switch 46 receives the driving disabling signal D through the control terminal 44. The driving disabling signal D turns on the electronic switch 46, so that the voltage source 48 is electrically connected to the terminal conductive line.

Please refer to Fig. 6, when the first I / O pins DQ 0 ~ 3 are enabled, and the first I / O pins DQ 4 ~ 7 and the second I / O pins DQ 8 ~ When disabled, the memory test device of the present invention can be implemented in x4 I / O device or test mode. The first I / O pins DQ 0 ~ 3 are electrically connected to the chip of the memory 20, and the first I / O pins DQ 4 ~ 7 and the second I / O pins DQ 8 ~ 15 is not electrically connected to the chip of the memory 20, therefore, the four first conductive wires of the second wire bus 28 and the first wire bus 22 are drawn by dotted lines, and correspond to the first of the memory 20 The I / O pins DQ 4 ~ 7 and the second I / O pins DQ 8 ~ 15 will be masked.

In the x4 write mode, the I / O driver 40 receives the driving enable signal E through the control terminal 44 and transmits the test pattern signal PAT from the I / O driver 40 of the I / O tester module bus 26 to the memory 20 The first I / O pins DQ 0 ~ 3, and then the test pattern signal PAT is written into the memory 20. When the electronic switch 46 receives the driving enable signal E through the control terminal 44, the driving enable signal E will turn off the electronic switch 46, so that the voltage source 48 is not connected to the terminal conductive line.

In the x4 read mode, the I / O driver 40 receives the driving disabling signal D through the control terminal 44 to stop transmitting the test pattern signal PAT from the memory 20 data of the first I / O pins DQ 0 ~ 3 It will be read by the I / O receiver 42 of the I / O tester module bus 26. The electronic switch 46 receives the driving disabling signal D through the control terminal 44. The driving disabling signal D turns on the electronic switch 46, so that the voltage source 48 is electrically connected to the terminal conductive line.

In summary, the present invention can be implemented in various I / O devices or test modes, such as x4, x8, or x16, without changing the test fixture. Furthermore, the present invention is not limited to the universal x16 I / O device or test mode. When the number of conductive wires of each wire busbar is increased from 8 to 16, the x32 I / O device or test mode can also be used for testing. 32-bit memory.

The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand and implement the content of the present invention. When the scope of the patent of the present invention cannot be limited, Any equal changes or modifications made according to the spirit disclosed in the present invention should still be covered by the patent scope of the present invention.

10‧‧‧Memory

12‧‧‧I / O module bus

14‧‧‧Terminal module bus

16‧‧‧I / O bus

18‧‧‧terminal bus

20‧‧‧Memory

22‧‧‧First conductor bus

24‧‧‧I / O bus

26‧‧‧I / O tester module bus

28‧‧‧Second conductor bus

30‧‧‧Terminal module bus

32‧‧‧terminal bus

34‧‧‧node

36‧‧‧I / O Tester Module

38‧‧‧Terminal Module

40‧‧‧I / O driver

42‧‧‧I / O receiver

44‧‧‧Control terminal

46‧‧‧Electronic Switch

48‧‧‧Voltage source

50‧‧‧ resistance

52‧‧‧I / O circuit

54‧‧‧The first P-channel metal oxide semiconductor field effect transistor

56‧‧‧first resistor

58‧‧‧Second resistor

60‧‧‧The first N-channel metal oxide semiconductor field effect transistor

62‧‧‧Second P-channel metal oxide semiconductor field effect transistor

64‧‧‧Third resistor

66‧‧‧Fourth resistance

68‧‧‧Second N-channel metal oxide semiconductor field effect transistor

70‧‧‧ Comparator

DQ 0 ~ 7‧‧‧‧I / O pin

DQ 8 ~ 15‧‧‧Second I / O pin

FIG. 1 is a schematic circuit diagram of a general-purpose memory testing device. FIG. 2 is a schematic circuit diagram of a memory test device when read / write x16 I / O devices or I / O pins in a test mode according to an embodiment of the present invention. FIG. 3 is a circuit diagram illustrating an I / O circuit corresponding to one of the first I / O pin and the second I / O pin and a tester according to an embodiment of the present invention. FIG. 4 is a waveform diagram of a test voltage according to the present invention. FIG. 5 is a schematic circuit diagram of a memory test device when read / write x8 I / O devices or I / O pins in a test mode according to an embodiment of the present invention. FIG. 6 is a schematic circuit diagram of a memory test device when read / write x4 I / O devices or I / O pins in a test mode according to an embodiment of the present invention.

Claims (10)

A memory testing device is used to test a memory. The memory has a plurality of first input / output (I / O) pins and a plurality of second I / O pins. The memory testing device includes: a first A wire bus, electrically connected to the first I / O pins; an I / O bus, electrically connected to the first wire bus, and between the first wire bus and the I / O bus There are nodes between them; an I / O tester module bus, which is electrically connected to the first wire bus through the I / O bus; and a second wire bus, which is electrically connected to the node and the Wait for the second I / O pin. The memory testing device according to the first item of the claim further includes a terminal module bus, which is electrically connected to the I / O bus through a terminal bus. The memory testing device according to claim 2, wherein the first wire bus further includes a plurality of first conductive wires, the second wire bus further includes a plurality of second conductive wires, and the I / O bus bar further includes: Including a plurality of I / O conductive wires, the terminal bus further includes a plurality of terminal conductive wires, the I / O tester module bus further includes a plurality of I / O tester modules, and the terminal module bus further includes a plurality of Terminal module; the node, the first I / O pins, the second I / O pins, the first conductive lines, the second conductive lines, the I / O conductive lines, the The number of terminal conductive wires, the number of I / O tester modules, and the number of terminal modules are equal. The memory testing device according to item 3 of the claim, wherein the number of the first I / O pins is eight and the number of the second I / O pins is eight; If four of the I / O pins are enabled and the other four are disabled, the second I / O pins are disabled; or the first I / O pins and the second I / O pins are disabled. The I / O pins are all enabled; or when the first I / O pins are enabled, the second I / O pins are disabled. The memory testing device described in claim 3, wherein the I / O tester module further includes: an I / O driver electrically connected to a control terminal and the I / O of the I / O bus Conductive line, and the control end receives a drive enable signal or a drive disable signal. When the I / O driver receives the drive enable signal through the control terminal, the I / O driver uses the drive enable signal and A test pattern signal is transmitted to the memory through the I / O conductive line of the I / O bus, the first conductive line of the first conductive bus, and the second conductive line of the second conductive bus. The first I / O pin and the second I / O pin; and when the I / O driver receives the driving disable signal through the control terminal, the I / O driver uses the driving disable signal to Stop transmitting the test pattern signal; and an I / O receiver, electrically connected to the I / O conductive line of the I / O bus, and through the first I / O pin and the second I / O connector Pin, the first conductive line of the first wire bus, the second conductive line of the second wire bus, and the I / O conductive line of the I / O bus read the Memory data. The memory test device according to item 5 of the claim, wherein the terminal module further includes: an electronic switch electrically connected to the control terminal and the terminal conductive wire of the terminal bus; a voltage source having a constant A DC power source; and a resistor electrically connected between the voltage source and the electronic switch. When the electronic switch receives the driving enable signal through the control terminal, the driving enable signal turns off the electronic switch. So that the voltage source is not connected to the terminal conductive line of the terminal bus; and when the electronic switch receives the driving disabling signal through the control terminal, the driving disabling signal turns on the electronic switch to make the voltage source electrically The terminal conductive line connected to the terminal bus. The memory testing device according to claim 1, wherein the memory system is synchronous dynamic random access memory (SDRAM), double data rate (DDR), DDR2, DDR3, DDR4, or low-power DDR4. A memory testing method includes: providing a memory, the memory having a plurality of first I / O pins and a plurality of second I / O pins, the first I / O pins converging through a first wire; And an I / O bus are electrically connected to a corresponding I / O tester module bus, and the second I / O pins are electrically connected to the I / O bus through a second wire bus To the corresponding I / O tester module bus; when testing a write mode, transmitting a test pattern signal from the I / O tester module bus to the first I / Os of the memory O pins and the second I / O pins; and when testing a read mode, using the I / O tester module bus from the first I / O pins and the second I / O pins The / O pin reads data from the memory. The memory testing method according to claim 8, wherein in the step of reading the data by the I / O tester module bus, the I / O tester module bus is simultaneously or Read the data of the memory in sequence. The memory testing method according to item 8 of the claim, wherein the I / O bus is electrically connected to a terminal module bus through a terminal bus.