200935521 九、發明說明 【發明所屬之技術領域】 本發明係關於薄膜電晶體（TFT)及其製造方法，更 詳言之’係關於具備由微結晶矽構成的通道層之薄膜電晶 ' 體及其製造方法。 【先前技術】 φ 作爲適用於顯示裝置之發光元件之一例，已知有具有 有機化合物的薄膜層積構造之有機EL (電致發光）發光 元件（OLED )。有機EL發光元件，係薄膜之自發光型元 件，因爲具有低驅動電壓、高解析度、高視角、以即可顯 示全彩之優異特徵，所以有種種應用檢討促進其實用化。 例如，對於可攜終端機、產業用計測器、家庭用電視等之 應用。 於EL發光之控制，有在各畫素設置TFT作爲驅動電 〇 晶體之主動矩陣方式。圖1顯示使用於主動矩陣方式之從 前之有機EL發光元件。有機EL發光元件100，具備具 有：玻璃基板101、玻璃基板101上之閘極電極102、閘 極電極102上之閘極絕緣層103、閘極絕緣層103上之本 質（intrinsic)非晶矽層（a-Si)層104、本質a-Si層104上之 η型a-Si層105、η型a-Si層105上之源極電極106及汲 極電極107之TFT110。此外，有機EL發光元件1〇〇進而 具備：TFT 110上之層間絕緣層121、層間絕緣層121上 之下部電極，且通過貫孔122與汲極電極1〇7連接的下部 -4- 200935521 電極123、下部電極123上之有機發光層124、及有機發 光層124上之透明電極125。 玻璃基板101亦可爲塑膠等絕緣基板。閘極電極102 藉由光蝕刻法等被圖案化爲所希望的形狀。材料爲鉻等金 屬，膜厚爲25nm程度。閘極絕緣層103係藉由濺鍍法形 成的SiN、Si02、SiNxOy等絕緣體。膜厚爲l〇〇nm程度。 本質a-Si層104係藉由電漿CVD法堆積50nm程度，η型 a-Si層105係藉由電漿CVD法等堆積l〇nm程度。源極電 極106及汲極電極107，係於η型a-Si層105上將鉻等藉 由濺鍍而蒸鍍25nm程度後，使用光蝕刻法圖案化爲所要 的形狀而得。η型a - S i層1 0 5係以如此得到的源極電極 106以及汲極電極107之鉻圖案作爲遮罩，圖案化成爲與 源極電極106以及汲極電極107相同的尺寸。此時要注意 本質a-Si層104不要被削入是很重要的。 有機EL發光元件100，如以下所述地動作。當影像 訊號（未圖示）被傳來時，於控制1C或者控制用 TFT (均未圖示）被變換爲適切的控制訊號，被傳至閘極電極 102。該訊號超過TFT 110的閾値時，TFT 110的通道層 之本質a-Si層104成爲導通狀態，汲極電極107的電位 接近源極電極106的電位。源極電極106藉由配線（未圖 示）成爲接地電位，此外透明電極12 5，藉由配線（未圖 示）被連接於5V等之電位。亦即，於有機發光層124之 兩端間被施加5V之電位，而發出光。又，TFT 110不止 於有機EL也可作爲LCD用。 200935521 圖2僅顯示圖1之有機EL發光元件所具備之a_Si TFT。a-Si TFT 110其通道層藉由a-Si所構成，不需要 L T P S (低溫多晶矽）所必要的多結晶化製程。此外，使 用a-Si TFT的場合，能夠以4枚光蝕刻遮罩形成TFT， 單位成本之表現優良。因此，大面積化很容易，參差不齊 也很少，而且具有能以低成本來製造的優點。然而，a_Si TFT 110有以下2個缺點。使電流流動而驅動時，會有閾 φ 値變動畫質劣化的這一點’以及移動度很小使電流流動的 能力很低’爲了提高驅動的有機EL的畫質或者爲了提高 精細度，必須要使畫素尺寸縮小，但是TFT的尺寸不能 夠太過縮小，在畫素尺寸上有個界限這一點。使用a-Si TFT的話移動度爲〇.5cm2/Vs以下，但爲了驅動有機EL 發光元件之TFT的移動度，最好是icm2/vs以上，特別 是在與閘極絕緣層之界面最好是1 cm2/Vs以上。 以上的缺點只要在通道層使用多結晶矽即可減低，但 〇 是藉由a- S i構成通道層的優點則無法得到。在此，如 a-Si太陽電池業者自很久以前即已知道的，應該可以利用 藉由選擇a-Si層形成的製程條件而形成微結晶化之a_Si 。然而’使用此技術製造被使用於有機EL發光元件的 TFT並沒有成功例。 例如，在非專利文獻1，顯示，藉由P E C V D (電漿化 學氣相沈積）法形成被微結晶化的a-Si亦即微結晶砂之 TFT之例。於圖3顯示該例。TFT3 00，具備：玻璃基板 1 〇 1、玻璃基板1 0 1上之閘極電極1 02、閘極電極1 〇2上 -6 - 200935521 之閘極絕緣層103、閘極絕緣層l〇3上之微結晶矽層層 304、微結晶矽層304上之η型a-Si層105、η型a-Si層 105上之源極電極106及汲極電極1〇7。TFT3 00即使通道 層不是a-Si而是微結晶矽，但還是有閾値變動的缺點， ' 而且移動度比a- S i還要小。非專利文獻1之作者群，發 ' 現其理由在於使微結晶矽成膜之PECVD的製程條件，在 與閘極絕緣層103之界面附近的區域304A，有200埃 φ ( A )程度是成爲a-Si。總之，通道層並不是由充分微結 晶化的a-Si所構成。 此外，於非專利文獻2，具備藉由微結晶矽構成通道 層的TFT之顯示器，克服a-Si之缺點，顯示適於大型顯 示器應用，但是此微結晶矽，係使a-Si經過以雷射進行 退火處理等複雜的步驟而製作的。此外，亦有記載著此微 結晶矽之結晶分率爲7 0 %。 此外，於專利文獻1，記載著作爲在矽之氮化物層上 〇 形成微結晶矽層的方法，在形成微結晶矽層之前’對矽之 氮化物層施以電漿處理（參照專利文獻1之段落002 1〜 0023 )。雖有記載根據此方法的話可以比a-Si層更往微 結晶矽層的微結晶化上前進（參照專利文獻段落 0024)，但是結晶分率，顯示例如在以氫氣爲反應氣體之 電漿處理的場合約爲50%，使用其他反應氣體的場合約爲 70%前後之結果（參照專利文獻1段落0029〜003 1 )。此 由非專利文獻1之見解可知，在與絕緣層（矽之氮化物 層）之界面附近的區域不被微結晶化，仍是a-Si。 -7- 200935521 此外，在專利文獻2，記載著以氫氣稀釋率200以上 之條件形成矽膜，將氫氣稀釋率變更爲2〜100，藉由在 先前形成的矽膜上繼續成膜而形成微結晶矽層之方法（參 照專利文獻2段落0030)，但顯示結晶分率最高也只有 ' 70%之結果（參照專利文獻2段落0042 )。專利文獻3也 ' 有相同的揭示。 本發明係有鑑於這樣的問題點而完成者，其第1目的 φ 在於提供廉價地製造具備由微結晶矽所構成的通道層之薄 膜電晶體。 此外，其第2目的在於提供驅動中的閾値變動很小且 移動度高，廉價之薄膜電晶體。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) and a method of fabricating the same, and more particularly to a thin film electro-crystal body having a channel layer composed of microcrystalline germanium and Its manufacturing method. [Prior Art] φ As an example of a light-emitting element suitable for a display device, an organic EL (electroluminescence) light-emitting element (OLED) having a thin film laminated structure of an organic compound is known. The organic EL light-emitting element, which is a self-luminous element of a thin film, has an excellent feature of displaying a full color because of its low driving voltage, high resolution, and high viewing angle. Therefore, various application reviews have been promoted to promote its practical use. For example, applications for portable terminals, industrial meters, home televisions, and the like. In the control of EL illumination, there is an active matrix method in which TFTs are provided as driving electromagnets in respective pixels. Fig. 1 shows a prior art organic EL light-emitting element used in an active matrix mode. The organic EL light-emitting device 100 includes a glass substrate 101, a gate electrode 102 on the glass substrate 101, a gate insulating layer 103 on the gate electrode 102, and an intrinsic amorphous germanium layer on the gate insulating layer 103. The (a-Si) layer 104, the n-type a-Si layer 105 on the intrinsic a-Si layer 104, the source electrode 106 on the n-type a-Si layer 105, and the TFT 110 of the drain electrode 107. Further, the organic EL light-emitting element 1 further includes an interlayer insulating layer 121 on the TFT 110, a lower electrode on the interlayer insulating layer 121, and a lower-4-200935521 electrode connected to the drain electrode 1〇7 through the through hole 122. 123. The organic light-emitting layer 124 on the lower electrode 123 and the transparent electrode 125 on the organic light-emitting layer 124. The glass substrate 101 may be an insulating substrate such as plastic. The gate electrode 102 is patterned into a desired shape by photolithography or the like. The material is a metal such as chromium, and the film thickness is about 25 nm. The gate insulating layer 103 is an insulator such as SiN, SiO 2 or SiN x O y formed by sputtering. The film thickness is about 10 nm. The intrinsic a-Si layer 104 is deposited by a plasma CVD method to a thickness of about 50 nm, and the n-type a-Si layer 105 is deposited by a plasma CVD method or the like to a degree of about 10 nm. The source electrode 106 and the drain electrode 107 are formed by depositing chromium or the like on the n-type a-Si layer 105 by sputtering to a thickness of about 25 nm, and then patterning it into a desired shape by photolithography. The n-type a - S i layer 1 0 5 is patterned by the chrome pattern of the source electrode 106 and the drain electrode 107 thus obtained, and is patterned to have the same size as the source electrode 106 and the drain electrode 107. It is important to note at this point that it is important that the a-Si layer 104 is not cut. The organic EL light-emitting element 100 operates as described below. When a video signal (not shown) is transmitted, the control 1C or the control TFT (none of which is shown) is converted into an appropriate control signal and transmitted to the gate electrode 102. When the signal exceeds the threshold of the TFT 110, the a-Si layer 104 of the channel layer of the TFT 110 is turned on, and the potential of the drain electrode 107 is close to the potential of the source electrode 106. The source electrode 106 is grounded by a wiring (not shown), and the transparent electrode 12 is connected to a potential of 5 V or the like by wiring (not shown). That is, a potential of 5 V is applied between both ends of the organic light-emitting layer 124 to emit light. Further, the TFT 110 can be used as an LCD not only for the organic EL. 200935521 FIG. 2 shows only the a_Si TFT provided in the organic EL light-emitting element of FIG. 1. The channel layer of the a-Si TFT 110 is composed of a-Si, and does not require a polycrystallization process necessary for L T P S (low temperature polysilicon). Further, when an a-Si TFT is used, the TFT can be formed by four photo-etching masks, and the performance per unit cost is excellent. Therefore, the large area is easy, the unevenness is small, and the advantage is that it can be manufactured at low cost. However, the a_Si TFT 110 has the following two disadvantages. When the current is caused to flow and is driven, there is a threshold φ 値 动画 动画 动画 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The size of the pixel is reduced, but the size of the TFT cannot be too narrow, and there is a limit in the size of the pixel. When the a-Si TFT is used, the mobility is 〇.5 cm 2 /Vs or less. However, in order to drive the mobility of the TFT of the organic EL light-emitting element, it is preferably icm 2 /vs or more, particularly in the interface with the gate insulating layer. 1 cm2/Vs or more. The above disadvantages can be reduced by using polycrystalline ruthenium in the channel layer, but 〇 is not obtained by the advantage of a-S i forming a channel layer. Here, as a-Si solar cell manufacturers have known for a long time, it should be possible to form micro-crystallized a_Si by using process conditions formed by selecting an a-Si layer. However, the use of this technique for manufacturing a TFT used for an organic EL light-emitting element has not been successful. For example, Non-Patent Document 1 shows an example in which a microcrystallized a-Si, that is, a microcrystalline sand TFT is formed by a P E C V D (plasma chemical vapor deposition) method. This example is shown in FIG. The TFT3 00 has a glass substrate 1 〇1, a gate electrode 102 on the glass substrate 110, a gate electrode 1 〇2, a gate insulating layer 103 of -6 - 200935521, and a gate insulating layer 103. The microcrystalline germanium layer 304, the n-type a-Si layer 105 on the microcrystalline germanium layer 304, the source electrode 106 on the n-type a-Si layer 105, and the drain electrode 1〇7. TFT3 00 has the disadvantage of a threshold 値 variation even if the channel layer is not a-Si but a microcrystalline ,, and the mobility is smaller than a-S i . In the author group of Non-Patent Document 1, the reason is that the process conditions of PECVD for forming a microcrystalline germanium film are 200 Å (A) in the region 304A near the interface with the gate insulating layer 103. a-Si. In summary, the channel layer is not composed of a-Si which is sufficiently micro-crystallized. Further, in Non-Patent Document 2, a display having a TFT which constitutes a channel layer by microcrystalline yttrium overcomes the disadvantage of a-Si and is suitable for a large-sized display application, but this microcrystalline yttrium causes a-Si to pass through a thunder It is produced by performing complicated steps such as annealing treatment. Further, it is also described that the crystallinity of the microcrystalline cerium is 70%. Further, Patent Document 1 describes a method in which a microcrystalline germanium layer is formed on a nitride layer of germanium, and a plasma treatment is performed on a nitride layer of germanium before forming a microcrystalline germanium layer (see Patent Document 1). Paragraph 002 1~ 0023). Although it is described that this method can advance toward the microcrystallization of the microcrystalline enamel layer than the a-Si layer (refer to paragraph 0024 of the patent document), the crystallization fraction shows, for example, plasma treatment using hydrogen as a reaction gas. The case is about 50%, and the case where other reaction gases are used is about 70% (see Patent Document 1, paragraphs 0029 to 003 1). As is apparent from the knowledge of Non-Patent Document 1, the region in the vicinity of the interface with the insulating layer (the nitride layer of germanium) is not microcrystallized, and is still a-Si. -7-200935521 Further, Patent Document 2 discloses that a ruthenium film is formed under the conditions of a hydrogen dilution ratio of 200 or more, and the hydrogen dilution ratio is changed to 2 to 100, and the film formation is continued by forming a film on the previously formed ruthenium film. The method of crystallizing the ruthenium layer (refer to paragraph 0030 of Patent Document 2) shows that the crystallization fraction is the highest as the result of '70% (refer to paragraph 0042 of Patent Document 2). Patent Document 3 also has the same disclosure. The present invention has been made in view of such a problem, and a first object of the present invention is to provide a thin film transistor having a channel layer made of microcrystalline germanium at low cost. Further, a second object of the present invention is to provide a thin film transistor which is small in variation in driving and has high mobility and is inexpensive.
[專利文獻1]日本專利特開2007-221137號公報 [專利文獻2]日本專利特開平6- 1 9670 1號公報 [專利文獻3]日本專利特開平8- 1 48690號公報 [非專利文獻 1]C. Y. Wu et al，“The Structure of ❹ Hydrogenated M i c ro c r y s t al 1 i n e Silicon ( μ c - S i: H) TFT[Patent Document 1] Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. ]CY Wu et al, "The Structure of ❹ Hydrogenated M ic ro cryst al 1 ine Silicon ( μ c - S i: H) TFT
Deposited by PECVD,” IDW’06, pp. 765-768 [非專利文獻 2]T. Arai et al, “Micro Silicon Technology for Active Matrix OLED Display,” SID07 DIGEST, p. 1370 【發明內容】 爲了達成這樣的目的，本發明之第1態樣，係薄膜電 晶體之製造方法’其特徵爲包含：於閘極絕緣層之形成 -8 - 200935521 後，將前述閘極絕緣層之表面按預先決定之時間通以氫氣 進行電漿處理之電漿處理步驟，及在前述電漿處理步驟之 繼續中，於前述閘極絕緣層上，導入原料氣體形成藉由微 結晶矽構成的通道層之通道層形成步驟。 ' 此外，本發明之第2態樣，係如第1態樣，特徵爲前 ' 述預先決定的時間，係於前述通道層形成步驟，導入原料 氣體得到一定的粒子尺寸以上的微結晶矽的前處理時間。 φ 此外，本發明之第3態樣，係如第2態樣，特徵爲進 而包含：於絕緣基板上，形成閘極電極以及前述閘極電極 上之前述閘極絕緣層之步驟，及於前述通道層上，形成η 型非晶矽層以及前述η型非晶矽層上之金屬電極之步驟。 此外，本發明之第4態樣，係如第2態樣，特徵爲進 而包含：於絕緣基板上，形成閘極電極以及前述閘極電極 上之前述閘極絕緣層之步驟，及於前述通道層上，形成ρ 型非晶矽層以及前述Ρ型非晶矽層上之金屬電極之步驟。 φ 此外，本發明之第5態樣，係薄膜電晶體之製造方 法，其特徵爲包含：於閘極絕緣層之形成後，於前述閘極 絕緣層上形成籽晶（seed)之籽晶形成步驟，及將前述閘極 絕緣層與前述籽晶的表面按預先決定之時間通以氫氣進行 電漿處理之電漿處理步驟，及在前述電漿處理步驟之繼_ 中，於前述閘極絕緣層與前述籽晶上，導入原料氣體形成 藉由微結晶矽構成的通道層之通道層形成步驟。 此外，本發明之第6態樣，係如第5態樣，特徵爲前 述預先決定的時間，係於前述通道層形成步驟，導入原料 -9 - 200935521 氣體得到一定的粒子尺寸以上的微結晶矽的前處理時間。 此外，本發明之第7態樣，係如第6態樣，特徵爲前 述籽晶形成步驟，係包含：於前述閘極絕緣層上，使以氫 氣稀釋的原料氣體進行電漿分解，形成上層部成爲微結晶 ' 矽的膜厚以上之籽晶用矽層之籽晶用矽層形成步驟，及圖 ' 案化前述籽晶用矽層，形成點圖案或線圖案之籽晶的圖案 化步驟。 φ 此外，本發明之第8態樣，係如第7態樣，特徵爲於 前述電漿處理步驟之前，進而包含雷射照射前述籽晶的胃 射照射步驟。 此外，本發明之第9態樣，係如第6態樣，特徵爲前 述籽晶形成步驟，係包含：於前述閘極絕緣層上形成溝g (trench)，使以氫氣稀釋的原料氣體進行電漿分解，將上 層部成爲微結晶矽的膜厚以上之籽晶用矽層埋入前述溝渠 之之籽晶用矽層形成步驟，及蝕刻前述籽晶用矽層，胃％ 〇 前述溝渠內殘留前述籽晶用矽層而形成籽晶的蝕刻歩驟。 此外’第1 0態樣，係如第9態樣，特徵爲前述溝渠 的大小爲表面積爲〇·5μπι平方以上3·5μιη平方以下，深 度在1 OOnm以上。 此外，本發明之第1 1態樣，係如第9態樣，特徵爲 於前述電漿處理步驟之前’進而包含雷射照射前述释晶的 雷射照射步驟。 此外’本發明之第12態樣，係如本發明之第1丨熊 樣’特徵爲前述溝渠的大小爲表面積爲〇·5μΙη平方以上 -10- 200935521 3μιη平方以下，深度在30nm以上。 此外，本發明之第13態樣，係如本發明之第1至第 12態樣之任一，特徵爲前述原料氣體，係较氫化物之氣Deposited by PECVD," IDW'06, pp. 765-768 [Non-Patent Document 2] T. Arai et al, "Micro Silicon Technology for Active Matrix OLED Display," SID07 DIGEST, p. 1370 [Summary of the Invention] A first aspect of the present invention is a method for producing a thin film transistor characterized by comprising: after forming a gate insulating layer -8 - 200935521, the surface of the gate insulating layer is determined at a predetermined time a plasma treatment step of plasma treatment by hydrogen gas, and a channel layer formation step of introducing a source gas on the gate insulating layer to form a channel layer composed of microcrystalline germanium in the continuation of the plasma treatment step Further, the second aspect of the present invention is characterized by the first aspect, characterized in that the predetermined time is described in the channel layer forming step, and the raw material gas is introduced to obtain a microcrystal having a constant particle size or more. The pre-processing time is φ. Further, the third aspect of the present invention is the second aspect, characterized by further comprising: forming a gate electrode and the gate electrode on the insulating substrate. a step of forming a gate insulating layer, and forming a n-type amorphous germanium layer and a metal electrode on the n-type amorphous germanium layer on the channel layer. Further, the fourth aspect of the present invention is as in the second The aspect further includes the steps of: forming a gate electrode and the gate insulating layer on the gate electrode on the insulating substrate, and forming a p-type amorphous germanium layer on the channel layer and the foregoing germanium type The step of forming a metal electrode on the amorphous germanium layer. φ In addition, the fifth aspect of the invention is a method for manufacturing a thin film transistor, comprising: after the formation of the gate insulating layer, the gate insulating layer a seed crystal forming step of forming a seed, and a plasma processing step of treating the surface of the gate insulating layer and the seed crystal with a plasma at a predetermined time by using a hydrogen gas, and processing the plasma In the step _, a channel layer forming step of forming a channel layer composed of microcrystalline germanium on the gate insulating layer and the seed crystal is introduced into the gate insulating layer. Further, the sixth aspect of the present invention is as described in 5 aspect, feature The predetermined time is the pretreatment time of the microcrystal enthalpy of a predetermined particle size or more by introducing the raw material -9 - 200935521 into the channel layer forming step. Further, the seventh aspect of the present invention is as the sixth The seed crystal forming step is characterized in that: on the gate insulating layer, the raw material gas diluted with hydrogen is subjected to plasma decomposition to form a seed crystal having a thickness of more than 10 μm of the upper layer The seed layer of the enamel layer is formed by a ruthenium layer forming step, and the patterning step of forming a seed crystal of a dot pattern or a line pattern by forming the ruthenium layer for the seed crystal. Further, the eighth aspect of the present invention is characterized in that, in the seventh aspect, the step of irradiating the seed crystal by the laser irradiation is further included before the plasma treatment step. According to a ninth aspect of the present invention, in the sixth aspect, the seed crystal forming step includes forming a trench g on the gate insulating layer to perform a raw material gas diluted with hydrogen. The plasma is decomposed, and the upper layer is a film thickness of the microcrystalline yttrium or more, and the seed layer is formed by the ruthenium layer for burying the seed crystal layer in the trench, and the ruthenium layer for the seed crystal is etched. An etching step of forming a seed crystal by using the tantalum layer to form a seed crystal remains. Further, the '10th aspect is a ninth aspect, and the size of the trench is such that the surface area is 〇·5 μπι square or more and 3·5 μιη square or less, and the depth is 100 nm or more. Further, the first aspect of the present invention is the ninth aspect, characterized in that the laser irradiation step of the laser irradiation is performed before the plasma treatment step. Further, the twelfth aspect of the present invention is characterized in that the first raccoon-like feature of the present invention is such that the size of the trench is 〇·5 μΙη square or more -10-200935521 3 μιη square or less, and the depth is 30 nm or more. Further, the thirteenth aspect of the invention is characterized by any one of the first to twelfth aspects of the invention, characterized in that the raw material gas is a gas of a hydride.
Hrftl 體。 此外’本發明之第14態樣’係具備：絕緣基板、前 ' 述絕緣基板上的閘極電極、前述閘極電極上的閘極絕緣 膜、前述閘極絕緣膜上的通道層、前述通道層上的非晶砂 φ 層、及前述非晶矽上的金屬電極之薄膜電晶體。前述通道 層，由與前述閘極絕緣層之界面起，到與前述非晶砂層之 界面爲止，係由微結晶矽所構成。 此外’本發明之第1 5態樣’係如本發明之第1 4態 樣，特徵爲前述非晶矽層，係η型非晶矽層。 此外’本發明之第1 6態樣’係如本發明之第14態 樣，特徵爲前述非晶矽層，係ρ型非晶矽層。 此外’本發明之第17態樣’係具備：絕緣基板、前 ❹ 述絕緣基板上的閘極電極、前述閘極電極上的閘極絕緣 膜、前述閘極絕緣膜上的通道層、前述通道層上的非晶矽 層、及前述非晶矽上的金屬電極之薄膜電晶體，其特徵 爲··前述通道層，係藉由申請專利範圍第iK；!〗項之任一 ' 項之製造方法所製造。 根據本發明，使閘極絕緣層之表面以氫氣充滿而以電 漿活化，藉由在該狀態導入矽氫化合物而電漿分離，可以 廉價地製造從與閘極絕緣層之界面具備藉由微結晶矽所構 成的通道層之薄膜電晶體。這樣的薄膜電晶體，驅動中之 -11 - 200935521 閾値變動很小且移動度高。 【實施方式】 以下，參照圖面詳細說明本發明之實施型態。對相同 於前述圖面所示之構成要素者，賦予同一符號。 (實施形態1 ) 圖4係相關於本發明之薄膜電晶體。薄膜電晶體 400，具備··玻璃基板101 (相當於「絕緣基板」）、玻 璃基板101上之閘極電極102、閘極電極102上之閘極絕 緣層103、閘極絕緣層103上之本質微結晶矽層層404 (相當於「通道層」）、本質微結晶矽層404上之η型 a-Si層105、η型a-Si層105上之源極電極106及汲極電 極107、保護層408。保護層408係以濺鍍、CVD等形成 之 Si02、SiN 等。 薄膜電晶體400，其本質微結晶矽層404，從與閘極 絕緣層103之界面起至與η型a-Si層105之界面爲止係 藉由本質微結晶矽所構成，與從前結晶分率低’於與閘極 絕緣層103之界面係a-Si者有所不同。本發明之薄膜電 晶體係其驅動中之閾値變動很小且移動度很高者將在後述 之實施例揭示。 薄膜電晶體400所具備之本質（intrinsic)微結晶矽層 404可以由如下之方式形成。在閘極絕緣層103之形成 後，將閘極絕緣層1 03之表面，跨預定時間使氫氣流過而 -12- 200935521 進行電漿處理。接著，在繼續電漿處理的期間，導入原料 氣體使由本質微結晶所構成的本質微結晶層404形成於閘 極絕緣層103上。微結晶矽，譬如說在氫之大海中使矽活 化而凝聚形成的，所以此方法，使閘極絕緣層（103)之 表面布滿氫而活化，在該狀態下導入矽者，可以從與閘極 絕緣層之界面廉價地製造具備藉由微結晶矽所構成的通道 層之薄膜電晶體。此於非晶質TFT之製造裝置，可以藉 由改變a-Si層形成之製程條件而實施。原料氣體，係僅 由Si與Η所構成的矽氫化合物之氣體，例如係單矽烷、 二矽烷或三矽烷。適切者爲單矽烷（SiH4)氣體。 又，於圖4顯示η型a-Si層105，但亦可爲p型a-Si 層。通道層，顯示藉由本質微結晶矽所構成者，亦可而被 摻雜者。 實施例1 -1 φ 製作圖4所示之薄膜電晶體。閘極絕緣層103之電漿 處理，係將玻璃基板 101加熱至 20(TC ，使氫氣以 300mTorr之壓力條件120sccm之流量流入，以50mW/cm2 施加27MHz之高頻進行30分鐘程度。加熱溫度亦可爲 1 00 °C〜3 00 t。本質微結晶矽層404在不關掉電漿處理而 繼續之狀態下以5Sccm導入SiH4氣體形成薄膜。成膜時 間以膜厚成爲2 5 Onm程度的方式調整，爲3 0分鐘程度。 接著形成50〜lOOnm之a-Si層105。 評估此 TFT之特性，移動度爲 3cm2/Vs，閾値爲 -13- 200935521 3.2V。此外，微結晶之粒子尺寸爲29nm。這樣的移動度 對不是a-Si而是結晶分率極高的微結晶矽而言係被預期 之値，所以可知只要適切進行使用氫氣之電漿處理而形成 本質微結晶矽的話，可以從閘極絕緣層之界面立刻形成微 _ 結晶矽。此外，對此TFT以Vgs = 30V、60°C之條件評估 ' 閾値變動時，經過1 0 0 〇小時後變動値爲〇. 4 3 V相當的 小，在信賴性上也沒有問題。 φ 其次，針對使用氫之電漿處理的條件加以檢討。圖5 顯示微結晶矽的粒子尺寸與電漿處理之前處理時間及頻率 之關係。此係針對前述之實施例與改變電漿處理的條件而 製作的樣品來測定粒子尺寸之結果。可知頻率隨著 13.56MHz、27MHz、66MHz、100MHz 而增力口，對閘極絕 緣層之前處理時間很短的情況下，粒子尺寸即會飽和。 此處所謂「前處理時間」係對閘極絕緣層之電漿處理 的時間。亦即，爲了提高生產率，最好以更高頻進行電漿 馨 處理。作爲微結晶砂粒子尺寸超過10〜20nm的話移動度 超過3cm2/Vs，對TFT的驅動而言是充分的，所以可以用 粒子尺寸超過20nm的時間來作爲評估生產率的一個參 考。頻率爲13.56MHz的場合導入SiH4氣體前必須要30 分鐘之氫氣處理，但在100MHz的場合該前處理時間可以 縮短爲8分鐘程度。 最後，圖6顯示粒子尺寸與電漿處理之電漿處理時間 以及功率之關係。使功率亦即供產生電漿而投入的高頻電 力提高至 20mW/cm2、50mW/cm2、100mW/cm2 的話，在很 -14- 200935521 短的前處理時間’可以使閘極絕緣層的表面成爲可形成具 有必要的粒子尺寸之微結晶矽的狀態’可以提高生產率。 藉由如此般適當選擇電漿處理的頻率與功率，可以藉 由預先決定的前處理時間形成具有一定粒子尺寸的微結晶 砂。 ' 又，前述粒子尺寸係藉由粉末X線繞射法來測定。 亦即，使用X線繞射圖案所示之峰値之繞射角α、半高 φ 寬Β以及測定波長λ的話，粒子尺寸以下式表示。 t=0.9X/Bcosa 粒子尺寸，較佳者爲20〜30 nm。 此外，前述流量單位「seem」係標準狀態（latm、25 °C )下規格化的單位，意思爲standard cc/miη。 實施例1-2 將實施例1-1之η型a-Si層105製作爲ρ型a-Si層 〇 之薄膜電晶體。此TFT移動度爲2.7cm2/Vs，閾値爲 3.1V。粒子尺寸，與實施例1相同。評估可信賴性的結 果，閾値變動爲〇·3 9V相當地小，並不會有問題。 (實施形態2 ) 相關於實施型態2之薄膜電晶體，具有與相關於實施 型態1的薄膜電晶體相同的構造，但其製造方法不同。 薄膜電晶體400所具備之本質（intrinsic)微結晶砍層 404’在實施型態2可以由如下之方式形成。在閘極絕緣 -15- 200935521 層103形成後，電漿分解以氣氣稀釋的原料氣體，形成一 定膜厚以上之籽晶用矽層。籽晶用矽層’如非專利文獻1 所揭示的，在與閘極絕緣層1〇3之界面附近之區域有未被 微結晶化的可能性，以至少上層部係微結晶化矽的方式選 ' 擇膜厚。其次，藉由光蝕刻法圖案化此籽晶用矽層，形成 點圖案（dot pattern)或者線圖案（line pattern)。其次， 將點圖案或者線圖案以及閘極絕緣層1〇3之表面，跨預定 φ 時間使氫氣流過而進行電漿處理。接著，在繼續電漿處理 的期間，導入原料氣體使由本質微結晶所構成的本質微結 晶層404形成於閘極絕緣層103上。本質微結晶矽層404 形成後，籽晶其全體成爲微結晶矽。此製造方法，於非晶 質TFT之製造裝置，可以藉由改變a-Si層形成之製程條 件而實施。原料氣體，係僅由Si與Η所構成的矽氫化合 物之氣體，例如係單矽烷、二矽烷或三矽烷。適切者爲單 矽烷（SiH4)氣體。 參 又，於圖4顯示η型a_Si層105，但亦可與實施型態 1同樣’爲P型a-Si層。通道層，顯示藉由本質微結晶矽 所構成者，亦可而被摻雜者。 實施例2-1 以實施型態2之製造方法製作圖4所示之薄膜電晶 體。籽晶用矽層係藉由電漿分解而形成的，將玻璃基板 101加熱至 200 °C ，使氫氣以 3 00mTorr之壓力條件 120sccm之流量流入，使SiH4氣體以5sccm流入，以 -16 - 200935521 5 OmW/cm2施加27MHz之高頻而進行的。加熱溫度亦可爲 1 0 0 °C ~ 3 0 0 °c ° 籽晶之圖案化，通常藉由光蝕刻法進行。圖7之 (A)係籽晶（seed)之圖案化後之側面圖，（B)係圖案化 點圖案（dot pattern)時之平面圖，（C)係圖案化線圖案時 ' 之平面圖。圖7(b)之點係以矩形表示，但爲圓形的場合於 後述之測定也可得到同樣的效果。寬幅爲 0 ，膜厚爲z = 30nm，間隔爲\ν = 50μιη。點圖案的場合之Xi 方向的點間隔，爲與間隔w相同之値。點圖案701或線 圖案702以及閘極絕緣層103之電漿處理，係將玻璃基板 101加熱至 200 °C ，使氫氣以 300mTorr之壓力條件 120sccm之流量流入，以50mW/cm2施加27MHz之高頻進 行3分鐘程度。加熱溫度亦可爲1〇〇 °C〜300 °C。本質微 結晶矽層404在不關掉電漿處理而繼續之狀態下以5sCCm 導入SiH4氣體形成薄膜。成膜時間以膜厚成爲250nm程 〇 度的方式調整，爲30分鐘程度。接著形成50〜l〇〇nm之 η 型 a-Si 層 1 05。 評估此TFT之特性’移動度爲3.3cm2/Vs ’閾値爲 3.0V。此外，微結晶之粒子尺寸爲29nm。這樣的移動度 對不是a-Si而是結晶分率極高的微結晶矽而言係被預期 之値，所以可知只要適切進行使用氫氣之電漿處理而形成 本質微結晶矽的話’可以從閘極絕緣層之界面立刻形成微 結晶矽。此外，對此TFT以 Vgs = 30V、60°C之條件評估 閾値變動時，經過1〇〇〇小時後變動値爲〇.4V相當的小’ -17- 200935521 在信賴性上也沒有問題。此外，在使用雷射退火之LTPS 技術所製作之TFT會見到的洩漏電流也不產生。 圖8顯示點圖案的籽晶大小與微結晶矽層的粒子尺寸 之關係。間隔w爲50μηι。隨著點圖案（籽晶用矽層）之 厚度爲 20nm、30nm、50nm地增加，粒子尺寸也增加。 又，籽晶用矽層之成膜時間以1至1.2 A /s之速率爲參 考，爲3至10分鐘。 φ 圖9顯示點圖案的間隔w與微結晶矽層的粒子尺寸 之關係。寬幅爲xi=yi = 2pm。膜厚z爲20nm的場合，可 知增加間隔w的話，微結晶矽之粒子尺寸急速降低。粒 子尺寸之參差不齊，係點間隔w於50〜75 μιη的範圍，於 膜厚ζ爲20nm的場合，平均粒子尺寸達到30〜50%，但 是在點厚度z爲30〜50nm的場合，良好地被控制在平均 粒子尺寸之10%程度。 點圖案及線圖案之配置，只要不與閘極電極102重疊 ❹ 就不會對TFT的特性有不良影響。 其次，針對使用氫之電漿處理的條件加以檢討。圖 10顯示微結晶矽的粒子尺寸與電漿處理之前處理時間及 頻率之關係。此係針對前述之實施例與改變電漿處理的條 件而製作的樣品來測定粒子尺寸之結果。寬幅爲 Χι=Υι = 2μιη，膜厚爲z = 30nm，間隔爲νν = 50μιη。可知頻率 隨著 13.56MHz、27MHz、66MHz、100MHz 而增加，對閘 極絕緣層之前處理時間很短的情況下，粒子尺寸即會飽 和。針對不設籽晶而製作的樣品，比較顯示微結晶矽之粒 -18- 200935521 子尺寸與電漿處理之前處理時間及頻率之關係之圖5與使 用實施型態2的製造方法之圖1〇的結果，可知藉由籽晶 的存在可以使前處理時間縮短到1 / 1 〇以下。 實施例2-2 ' 形成圖7所示之點圖案及線圖案後，對其進行準分子 雷射（ 550nm)之照射。照射500mJ/cm2以上的話，於接 U 下來敘述之測定二者得到同樣的結果。 圖1 1顯示籽晶的厚度z與粒子尺寸之關係。間隔w 爲 50μΐη。隨著厚度 z 由 5nm、10nm、20nm、50nm 逐漸 增大，粒子尺寸也變大，厚度z爲lOnm以上超過20nm 充分被微結晶化。與圖8比較的話，可知藉由進行雷射照 射能夠以更小的厚度z微結晶化。 圖12顯示點圖案的間隔w與微結晶矽層的粒子尺寸 之關係。寬幅爲Χι=Υι=2μιη。可知厚度z爲lOnm以上粒 Q 子尺寸超過20nm，間隔w直到75μιη程度爲止微結晶性 都沒有問題。在點圖案的情況會有z = 5nm時爲50%程 度，z=10nm以上時爲10%程度之粒子尺寸的參差不齊， 但是替代點圖案而使用線圖案的話，分別被改善爲20%程 度與5%程度。 (實施形態3) 相關於實施型態3之薄膜電晶體，與實施型態1及2 同樣係圖4所示的構造，但其製造方法不同。於閘極絕緣 19- 200935521 層103之形成後，於閘極絕緣層i〇3上藉由光蝕刻法等形 成一定大小之溝渠。亦可按壓壓模而形成。接著電漿分解 以氫氣稀釋的原料氣體，以溝渠被埋入的方式形成籽晶用 矽層。接著，蝕刻籽晶用矽層，僅於溝渠內殘留籽晶用矽 層而形成籽晶。籽晶，如非專利文獻1所揭示的，在與閘 _ 極絕緣層1〇3之界面附近之區域有未被微結晶化的可能 性，以至少上層部係微結晶化矽的方式選擇溝渠的深度。 φ 其次，將籽晶及閘極絕緣層103之表面，跨預定時間使氫 氣流過而進行電漿處理。接著，在繼續電漿處理的期間， 導入原料氣體使由本質微結晶所構成的本質微結晶層404 形成於閘極絕緣層1 03上。除了活化界面以外，藉由預先 設置上層部爲微結晶矽之籽晶，可以廉價地製造具備由與 閘極絕緣層之界面起藉由微結晶矽構成的通道層之薄膜電 晶體。此製造方法，於非晶質TFT之製造裝置，可以藉 由改變a-Si層形成之製程條件而實施。原料氣體，係僅 ❷ 由Si與Η所構成的矽氫化合物之氣體，例如係單矽烷、 二矽烷或三矽烷。適切者爲單矽烷（SiH4)氣體。 實施例3 -1 製作圖4所示之薄膜電晶體。圖13爲溝渠之側面 圖。條件爲 χ = 2μιη，y=100nm，λν = 50μιη。好晶用砂層係 藉由電漿分解而形成的，將玻璃基板101加熱至200 °C， 使氫氣以300mTorr之壓力條件120sccm之流量流入，使 SiH4氣體以5sccm流入，以50mW/cm2施加27MHz之高 -20- 200935521 頻而進行的。堆積了 ο.ίμηι程度。加熱溫度亦可爲ioot 〜300。(：》籽晶用矽層之蝕刻，係導入以氬氣稀釋的四氟 甲烷氣體，藉由電漿蝕刻而進行。於溝渠以外之區域最好 是閘極絕緣層103外露於表面’觀察閘極絕緣層103上之 光吸收資料而控制蝕刻。籽晶1201以及閘極絕緣層103 ' 之電漿處理，係將玻璃基板101加熱至200°C，使氫氣以 300mTorr之壓力條件120sccm之流量流入，以50mW/cm2 φ 施加27MHz之高頻進行3分鐘程度。加熱溫度亦可爲 100 °C〜300 °C。本質微結晶矽層404在不關掉電漿處理而 繼續之狀態下以5sccm導入SiH4氣體形成薄膜。成膜時 間以膜厚成爲2 5 0nm程度的方式調整，爲30分鐘程度。 接著形成50〜100nm之η型a-Si層105。 評估此TFT之特性，移動度爲3.2cm2/VS，閾値爲 2.9V。此外，微結晶之粒子尺寸爲26nm。這樣的移動度 對不是a-Si而是結晶分率極高的微結晶矽而言係被預期 〇 之値，所以可知只要適切進行使用氫氣之電漿處理而形成 本質微結晶矽的話，可以從閘極絕緣層之界面立刻形成微 結晶矽。此外，對此TFT以Vgs = 30V、60°C之條件評估 閾値變動時，經過1 0 0 0小時後變動値爲0.4 1 V相當的 小，在信賴性上也沒有問題。 圖14顯示溝渠的寬幅X與微結晶矽層的粒子尺寸之 關係。間隔w爲5〇μπΐ。深度爲50nm的場合，寬幅X爲 1 μιη程度時取得最大値，此時之粒子尺寸爲1 2nm。另一 方面y爲l〇〇nm的場合’當X超過〇.5μηι的話粒子尺寸 -21 - 200935521 超過20nm，即使增加x粒子尺寸的減低 3. 5 μιη的話粒子尺寸變小。 圖15顯示溝渠的深度y與微結晶矽層 關係。X爲〇·5μπι以上，粒子尺寸之對y的 ' 同的傾向，y超過lOOnm的話粒子尺寸不會 • 變。 此外關於間隔w進行種種調查。在進行 φ 5μιη<κ<200μιη之範圍，任一場合均得到與 相同的數據。此外，即使不避開閘極電極而 上部形成溝渠的場合，也不會有問題。這表 機配置，沒有必要配合TFT的構造而設計溝 其次，針對使用氫之電漿處理的條件 16顯示微結晶矽的粒子尺寸與電漿處理之 頻率之關係。此係針對前述之實施例與改變 件而製作的樣品來測定粒子尺寸之結果。 Q 13·56ΜΗζ、27MHz、66MHz、100MHz 而增 緣層之前處理時間很短的情況下，粒子尺寸 在實施狀態1顯示於圖5之不設置籽晶而製 比較的話’可知藉由籽晶的存在而可以使前 短至1 /1 〇以下。 實施例3 - 2 形成圖13所示之籽晶後，對籽晶進 (5 5 0nm )之照射 也很少，超過 的粒子尺寸之 依存性顯示相 見到較大的改 實驗之 5 0 μιη的場合 到閘極電極的 示溝渠可以隨 渠圖案。 加以檢討。圖 前處理時間及 電漿處理的條 可知頻率隨著 加，對閘極絕 即會飽和。與 作的樣品進行 述處理時間縮 行準分子雷射 -22- 200935521 圖17顯示籽晶的寬幅χ與粒子尺寸之關係。間隔w 爲50μηι。可知與圖14所示之不進行雷射照射的場何不 同，深度y爲30nm，而χ爲0.5μπι至3μιη的範圍內粒子 尺寸超過20nm’可以在淺的溝渠得到安定的微結晶矽。 此對於量產時之生產率提高很有效。通常，使用雷射的場 合，爲了得到膜的均勻性雷射照射光之均一性是重要的技 術要素。在相關於本發明之製造方法，膜的均一性在雷射 照射後之成膜時可以得到，所以雷射照射時之均一性沒有 問題。現在，於本實施例，關於膜內之均一性或者TFT 之洩漏電流被認爲沒有問題。此情形在量產製造上，在生 產率以及成本的角度來看有非常大的優點。此外，雷射照 射對粒子尺寸與電漿處理之前處理時間之間的關係（圖 1 6 )並沒有特別造成大的影響。 圖18顯示籽晶的深度y與微結晶矽層的粒子尺寸之 關係。間隔w爲5 0 μ m。 【圖式簡單說明】 圖1係顯示使用於主動矩陣方式之從前之有機EL發 光元件。 圖2僅顯示具備圖1之有機EL發光元件之TFT。 圖3係顯示由PECVD (電漿化學氣相沈積法）形成 微結晶矽之TFT之例。 圖4係顯示相關於本發明之薄膜電晶體。 圖5顯示粒子尺寸與電漿處理之前處理時間及頻率之 -23- 200935521 關係。 圖6顯示粒子尺寸與電漿處理之前處理時間及功率之 關係。 圖7之（A)係好晶（seed)之圖案化後之側面圖， (B)係圖案化點圖案（dot pattern)時之平面圖，（C)係 ' 圖案化線圖案時之平面圖。 圖8顯示點圖案的籽晶大小與微結晶矽層的粒子尺寸 @ 之關係。 圖9顯示點圖案的間隔w與微結晶矽層的粒子尺寸 之關係。 圖10顯示微結晶矽的粒子尺寸與電漿處理之前處理 時間及頻率之關係。 圖1 1顯示籽晶的厚度z與粒子尺寸之關係。 圖12顯示點圖案的間隔w與微結晶矽層的粒子尺寸 之關係。 〇 圖1 3爲溝渠之側面圖。 圖14顯示溝渠的寬幅X與微結晶矽層的粒子尺寸之 關係。 圖15顯示溝渠的深度y與微結晶矽層的粒子尺寸之 關係。 圖16顯示微結晶矽的粒子尺寸與電漿處理之前處理 時間及頻率之關係。 圖17顯示籽晶的寬幅X與粒子尺寸之關係。 圖18顯示籽晶的深度y與微結晶矽層的粒子尺寸之 -24- 200935521 關係。 【主要元件符號說明】 100 :有機EL發光元件 1 :玻璃基板 _ 1 0 2 :閘極電極 103:閛極絕緣層 0 104:本質非晶较層（a-Si)層 105 : η 型 a-Si 層 1 0 6 :源極電極 1 0 7 :汲極電極 110： TFT 1 2 1 :層間絕緣層 122 :貫孔 123 :下部電極 Q 124 :有機發光層 1 2 5 :透明電極 400 :薄膜電晶體 4 04 =本質微結晶矽層層 408 :保護層 -25-Hrftl body. Further, the "fourth aspect of the invention" includes: an insulating substrate, a gate electrode on the insulating substrate, a gate insulating film on the gate electrode, a channel layer on the gate insulating film, and the channel A thin film transistor of a layer of amorphous sand φ on the layer and a metal electrode on the amorphous ruthenium. The channel layer is composed of microcrystalline germanium from the interface with the gate insulating layer to the interface with the amorphous sand layer. Further, the "fifth aspect of the invention" is characterized in that the amorphous ruthenium layer is an n-type amorphous ruthenium layer according to the fourteenth aspect of the invention. Further, the "16th aspect of the invention" is characterized in that the amorphous ruthenium layer is a p-type amorphous ruthenium layer according to the fourteenth aspect of the invention. Further, the "seventh aspect of the invention" includes: an insulating substrate, a gate electrode on the insulating substrate, a gate insulating film on the gate electrode, a channel layer on the gate insulating film, and the channel a thin film transistor of an amorphous germanium layer on a layer and a metal electrode on the amorphous germanium, characterized in that the channel layer is manufactured by any one of the claims iK; Made by the method. According to the present invention, the surface of the gate insulating layer is filled with hydrogen gas and activated by plasma. By introducing a hydrogen hydride compound in this state and plasma-separating, it is possible to inexpensively manufacture the interface from the gate insulating layer. A thin film transistor of a channel layer composed of crystalline germanium. In such a thin film transistor, the threshold 値 - 200935521 has little variation in threshold and high mobility. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same symbols are given to the same components as those shown in the above drawings. (Embodiment 1) Fig. 4 is a film transistor relating to the present invention. The thin film transistor 400 includes the essence of the glass substrate 101 (corresponding to "insulating substrate"), the gate electrode 102 on the glass substrate 101, the gate insulating layer 103 on the gate electrode 102, and the gate insulating layer 103. a microcrystalline germanium layer 404 (corresponding to a "channel layer"), an n-type a-Si layer 105 on the intrinsic microcrystalline germanium layer 404, a source electrode 106 and a drain electrode 107 on the n-type a-Si layer 105, Protective layer 408. The protective layer 408 is SiO 2 , SiN or the like formed by sputtering, CVD or the like. The thin film transistor 400, the intrinsic microcrystalline germanium layer 404, is formed by the intrinsic microcrystalline germanium from the interface with the gate insulating layer 103 to the interface with the n-type a-Si layer 105, and the former crystal fraction The low 'is different from the interface a-Si of the gate insulating layer 103. The thin film crystal system of the present invention exhibits a small variation in threshold 驱动 in driving and a high degree of mobility will be disclosed in the examples to be described later. The intrinsic microcrystalline germanium layer 404 provided in the thin film transistor 400 can be formed in the following manner. After the formation of the gate insulating layer 103, the surface of the gate insulating layer 103 is subjected to plasma treatment by flowing hydrogen gas over a predetermined period of time -12-200935521. Next, while the plasma treatment is being continued, the source gas is introduced to form the intrinsic microcrystal layer 404 composed of the intrinsic microcrystals on the gate insulating layer 103. Microcrystalline ruthenium, for example, is formed by activating and agglomerating ruthenium in the sea of hydrogen. Therefore, this method causes the surface of the gate insulating layer (103) to be filled with hydrogen to be activated, and in this state, it can be introduced from A thin film transistor having a channel layer composed of microcrystalline germanium is inexpensively manufactured at the interface of the gate insulating layer. The apparatus for manufacturing an amorphous TFT can be implemented by changing the process conditions for forming an a-Si layer. The material gas is a gas of an anthracene hydrogen compound composed only of Si and ruthenium, and is, for example, monodecane, dioxane or trioxane. Suitable for the single decane (SiH4) gas. Further, the n-type a-Si layer 105 is shown in Fig. 4, but may be a p-type a-Si layer. The channel layer, which is formed by the intrinsic microcrystalline yttrium, may also be doped. Example 1-1 φ The thin film transistor shown in Fig. 4 was produced. In the plasma treatment of the gate insulating layer 103, the glass substrate 101 is heated to 20 (TC, hydrogen gas is flowed at a flow rate of 120 sccm under a pressure of 300 mTorr, and a high frequency of 27 MHz is applied at 50 mW/cm2 for 30 minutes. The heating temperature is also It can be from 100 ° C to 300 00. The intrinsic microcrystalline ruthenium layer 404 is formed by introducing SiH 4 gas into the film at a rate of 5 sccm without stopping the plasma treatment. The film formation time is such that the film thickness becomes 2 5 Onm. The adjustment was performed to a degree of 30 minutes. Next, an a-Si layer 105 of 50 to 100 nm was formed. The characteristics of the TFT were evaluated, the mobility was 3 cm 2 /Vs, and the threshold 値 was -13 - 35,355,321 3.2 V. In addition, the particle size of the microcrystal was 29 nm. Such mobility is expected to be a microcrystalline ruthenium which is not a-Si but has a very high crystallization fraction. Therefore, it can be known that if the plasma is treated with hydrogen to form an essential microcrystalline ruthenium, The micro-crystal 矽 is formed immediately from the interface of the gate insulating layer. In addition, the TFT is evaluated under conditions of Vgs = 30 V and 60 ° C. When the threshold 値 varies, the 値 1 1 1 1 4 4 4 4 4 4 4 4 4 4 4 4 4 Quite small, in terms of reliability There is a problem. φ Next, the conditions for the treatment of plasma using hydrogen are reviewed. Figure 5 shows the relationship between the particle size of the microcrystalline germanium and the processing time and frequency before the plasma treatment. This is for the foregoing examples and changing the plasma. The sample produced by the conditions of the treatment was used to measure the particle size. It can be seen that the frequency increases with the frequency of 13.56 MHz, 27 MHz, 66 MHz, and 100 MHz, and the particle size is saturated when the processing time of the gate insulating layer is short. Here, the "pre-treatment time" is the time for the plasma treatment of the gate insulating layer. That is, in order to improve the productivity, it is preferable to perform the plasma treatment at a higher frequency. The particle size of the microcrystalline sand exceeds 10~. At 20 nm, the mobility exceeds 3 cm 2 /Vs, which is sufficient for driving the TFT. Therefore, a time when the particle size exceeds 20 nm can be used as a reference for evaluating the productivity. It is necessary to take 30 minutes before introducing the SiH 4 gas at a frequency of 13.56 MHz. Hydrogen treatment, but the pretreatment time can be shortened to 8 minutes at 100 MHz. Finally, Figure 6 shows particle size and plasma treatment. The relationship between the plasma processing time and the power. When the power is increased to 20mW/cm2, 50mW/cm2, 100mW/cm2, which is used for generating plasma, the pre-processing time is very short at -14-355355. 'It is possible to make the surface of the gate insulating layer into a state in which microcrystalline germanium having a necessary particle size can be formed'. The productivity can be improved. By appropriately selecting the frequency and power of the plasma treatment in this way, predetermined pre-processing can be performed. Time forms microcrystalline sand with a certain particle size. Further, the aforementioned particle size was measured by a powder X-ray diffraction method. That is, when the diffraction angle α, the half height φ width Β, and the measurement wavelength λ of the peak 所示 shown by the X-ray diffraction pattern are used, the particle size is expressed by the following formula. t = 0.9X / Bcosa particle size, preferably 20 to 30 nm. Further, the flow rate unit "seem" is a unit normalized in a standard state (latm, 25 ° C), and means standard cc/miη. Example 1-2 The n-type a-Si layer 105 of Example 1-1 was formed into a p-type a-Si layer 薄膜 film transistor. This TFT has a mobility of 2.7 cm 2 /Vs and a threshold 3.1 of 3.1V. The particle size was the same as in Example 1. Assessing the results of trustworthiness, the threshold change is 〇·3 9V is quite small and there is no problem. (Embodiment 2) The thin film transistor according to Embodiment 2 has the same structure as that of the thin film transistor according to Embodiment 1, but the manufacturing method is different. The intrinsic microcrystalline chopped layer 404' provided in the thin film transistor 400 can be formed in the following manner. After the gate insulating layer -15-200935521 layer 103 is formed, the plasma decomposes the raw material gas diluted with the gas gas to form a seed layer for a seed crystal having a predetermined film thickness or more. As the ruthenium layer for seed crystals, as disclosed in Non-Patent Document 1, there is a possibility that the region near the interface with the gate insulating layer 1〇3 is not crystallized, and at least the upper layer is microcrystallized. Select 'Select membrane thickness. Next, the seed layer for the seed crystal is patterned by photolithography to form a dot pattern or a line pattern. Next, the dot pattern or the line pattern and the surface of the gate insulating layer 1〇3 are subjected to plasma treatment by flowing hydrogen gas over a predetermined φ time. Next, while the plasma treatment is continued, the material gas is introduced to form an intrinsic microcrystalline layer 404 composed of intrinsic microcrystals on the gate insulating layer 103. After the formation of the intrinsic microcrystalline ruthenium layer 404, the entire seed crystal becomes a microcrystalline ruthenium. This manufacturing method can be carried out by manufacturing a device for forming an amorphous TFT by changing the process conditions for forming an a-Si layer. The material gas is a gas of a ruthenium hydrogen compound composed only of Si and ruthenium, and is, for example, monodecane, dioxane or trioxane. Suitable for the single decane (SiH4) gas. Further, the n-type a-Si layer 105 is shown in Fig. 4, but it may be the same as the embodiment 1 'as a P-type a-Si layer. The channel layer, which is formed by the intrinsic microcrystals, can also be doped. Example 2-1 A thin film transistor shown in Fig. 4 was produced by the production method of the embodiment 2. The seed crystal layer is formed by decomposing the plasma layer, heating the glass substrate 101 to 200 ° C, allowing hydrogen gas to flow at a flow rate of 120 sccm under a pressure of 300 mTorr, and flowing the SiH 4 gas at 5 sccm to -16 - 200935521 5 OmW/cm2 was applied with a high frequency of 27 MHz. The heating temperature can also be from 1 0 0 ° C to 300 ° C ° Patterning of the seed crystal, usually by photolithography. Fig. 7(A) is a side view of a seed after patterning, (B) is a plan view when a dot pattern is patterned, and (C) is a plan view when patterning a line pattern. The point of Fig. 7(b) is indicated by a rectangle, but when it is circular, the same effect can be obtained by the measurement described later. The width is 0, the film thickness is z = 30 nm, and the interval is \ν = 50μιη. In the case of the dot pattern, the dot interval in the Xi direction is the same as the interval w. The dot pattern 701 or the line pattern 702 and the plasma treatment of the gate insulating layer 103 heat the glass substrate 101 to 200 ° C, let hydrogen flow at a flow rate of 120 sccm under a pressure of 300 mTorr, and apply a high frequency of 27 MHz at 50 mW/cm 2 . Carry out 3 minutes. The heating temperature can also be from 1 ° C to 300 ° C. The intrinsic microcrystalline ruthenium layer 404 was introduced into the SiH4 gas at 5 sCCm to form a film without continuing the plasma treatment. The film formation time was adjusted so that the film thickness became 250 nm, which was about 30 minutes. Next, an n-type a-Si layer 105 of 50 to 1 〇〇 nm is formed. The characteristics of this TFT were evaluated as 'movability of 3.3 cm 2 /Vs ' threshold 3.0 of 3.0V. Further, the particle size of the microcrystals was 29 nm. Such a degree of mobility is expected to be a microcrystalline ruthenium which is not a-Si but has a very high crystallization fraction. Therefore, it can be seen that it can be obtained from a gate as long as it is subjected to plasma treatment using hydrogen gas to form an essential microcrystalline ruthenium. The interface of the pole insulating layer immediately forms a microcrystalline germanium. Further, when the TFT is evaluated for the threshold 値 fluctuation at a condition of Vgs = 30 V and 60 ° C, the change 値 after 1 hour is 〇. 4V is equivalent to a small ' -17- 200935521, and there is no problem in reliability. In addition, the leakage current seen by TFTs fabricated using LTPS technology using laser annealing does not occur. Fig. 8 shows the relationship between the seed crystal size of the dot pattern and the particle size of the microcrystalline germanium layer. The interval w is 50 μm. As the thickness of the dot pattern (the seed layer for the seed crystal) is increased by 20 nm, 30 nm, and 50 nm, the particle size also increases. Further, the film formation time of the seed crystal layer is referred to as a rate of 1 to 1.2 A / s, which is 3 to 10 minutes. φ Figure 9 shows the relationship between the spacing w of the dot pattern and the particle size of the microcrystalline ruthenium layer. The width is xi=yi = 2pm. When the film thickness z is 20 nm, it is understood that the particle size of the microcrystalline ruthenium is rapidly lowered when the interval w is increased. The particle size is uneven, and the dot spacing w is in the range of 50 to 75 μm. When the film thickness ζ is 20 nm, the average particle size is 30 to 50%, but when the dot thickness z is 30 to 50 nm, it is good. The ground is controlled to about 10% of the average particle size. The arrangement of the dot pattern and the line pattern does not adversely affect the characteristics of the TFT as long as it does not overlap with the gate electrode 102. Secondly, the conditions for the treatment of plasma using hydrogen are reviewed. Figure 10 shows the relationship between the particle size of the microcrystalline ruthenium and the processing time and frequency before the plasma treatment. This is the result of determining the particle size for the samples prepared in the foregoing examples and changing the conditions of the plasma treatment. The width is Χι=Υι = 2μιη, the film thickness is z = 30nm, and the interval is νν = 50μιη. It can be seen that the frequency increases with 13.56 MHz, 27 MHz, 66 MHz, and 100 MHz, and the particle size is saturated when the processing time of the gate insulating layer is short. For the sample prepared without the seed crystal, the comparison between the particle size of the microcrystalline germanium -18-200935521 sub-size and the processing time and frequency before the plasma treatment is shown in Fig. 5 and the manufacturing method using the embodiment 2 As a result, it can be seen that the pretreatment time can be shortened to less than 1 / 1 藉 by the presence of the seed crystal. Example 2-2' After forming the dot pattern and the line pattern shown in Fig. 7, it was irradiated with an excimer laser (550 nm). When the irradiation was performed at 500 mJ/cm2 or more, the same results were obtained by the measurement described in connection with U. Figure 11 shows the relationship between the thickness z of the seed crystal and the particle size. The interval w is 50 μΐη. As the thickness z is gradually increased from 5 nm, 10 nm, 20 nm, and 50 nm, the particle size is also increased, and the thickness z is lOnm or more and more than 20 nm, and is sufficiently crystallized. In comparison with Fig. 8, it is understood that micro-crystallization can be performed with a smaller thickness z by performing laser irradiation. Fig. 12 shows the relationship between the interval w of the dot pattern and the particle size of the microcrystalline ruthenium layer. The width is Χι=Υι=2μιη. It is understood that the thickness z is lOnm or more, the particle Q size exceeds 20 nm, and the microcrystallinity is not problematic until the interval w is up to 75 μm. In the case of the dot pattern, it is 50% when z = 5 nm, and the particle size of 10% is uneven when z = 10 nm or more, but the line pattern is improved to 20% when the dot pattern is used instead of the dot pattern. With a degree of 5%. (Embodiment 3) The thin film transistor according to Embodiment 3 is similar to Embodiments 1 and 2 in the structure shown in Fig. 4, but the manufacturing method is different. After the gate insulating layer 19-200935521 is formed, a trench of a certain size is formed on the gate insulating layer i〇3 by photolithography or the like. It can also be formed by pressing a stamper. Then, the plasma is decomposed into a raw material gas diluted with hydrogen, and a seed layer for seeding is formed in such a manner that the ditch is buried. Next, the seed layer is etched with a ruthenium layer, and only the seed crystal is left in the trench to form a seed crystal. As disclosed in Non-Patent Document 1, the seed crystal has a possibility of not being microcrystallized in a region in the vicinity of the interface with the gate electrode insulating layer 1〇3, and the trench is selected in such a manner that at least the upper layer is microcrystallized. depth. φ Next, the surface of the seed crystal and the gate insulating layer 103 is subjected to plasma treatment by flowing a hydrogen gas over a predetermined period of time. Next, while the plasma treatment is continued, the source gas is introduced to form the intrinsic microcrystal layer 404 composed of the intrinsic microcrystals on the gate insulating layer 103. In addition to the activation interface, a thin film transistor having a channel layer composed of microcrystalline germanium from the interface with the gate insulating layer can be manufactured at low cost by previously providing a seed crystal whose upper portion is a microcrystalline germanium. This manufacturing method can be carried out by a manufacturing apparatus for an amorphous TFT by changing the process conditions for forming an a-Si layer. The material gas is a gas of only an anthracene hydrogen compound composed of Si and ruthenium, and is, for example, monodecane, dioxane or trioxane. Suitable for the single decane (SiH4) gas. Example 3-1 A thin film transistor shown in Fig. 4 was produced. Figure 13 is a side view of the trench. The conditions are χ = 2μιη, y = 100nm, λν = 50μιη. The crystal layer for good crystal is formed by decomposition of plasma, the glass substrate 101 is heated to 200 ° C, hydrogen gas is flowed at a flow rate of 120 sccm under a pressure of 300 mTorr, SiH 4 gas is flowed at 5 sccm, and 27 MHz is applied at 50 mW/cm 2 . High -20- 200935521 frequently carried out. Stacked ο.ίμηι degrees. The heating temperature can also be ioot ~300. (:) The seed crystal is etched by a ruthenium layer, and is introduced into a tetrafluoromethane gas diluted with argon gas by plasma etching. Preferably, the gate insulating layer 103 is exposed on the surface of the gate outside the trench. The light on the insulating layer 103 absorbs the data to control the etching. The plasma treatment of the seed crystal 1201 and the gate insulating layer 103' heats the glass substrate 101 to 200 ° C, and the hydrogen gas flows in at a flow rate of 120 sccm under a pressure of 300 mTorr. The high frequency of 27 MHz is applied at 50 mW/cm 2 φ for 3 minutes. The heating temperature may also be 100 ° C to 300 ° C. The intrinsic microcrystalline germanium layer 404 is introduced at 5 sccm without continuing the plasma treatment. The SiH4 gas was formed into a film, and the film formation time was adjusted so as to be about 250 nm. The n-type a-Si layer 105 of 50 to 100 nm was formed. The characteristics of the TFT were evaluated and the mobility was 3.2 cm2. /VS, the threshold 値 is 2.9 V. In addition, the particle size of the microcrystal is 26 nm. Such mobility is expected to be a microcrystalline ruthenium which is not a-Si but has a very high crystallization fraction, so it is known that Suitable for the use of hydrogen in the plasma When the intrinsic microcrystalline germanium is formed, the microcrystalline germanium can be formed immediately from the interface of the gate insulating layer. Further, when the TFT is evaluated for the threshold enthalpy change under conditions of Vgs = 30 V and 60 ° C, after 1000 hours, The variation 値 is 0.4 1 V, which is quite small, and there is no problem in reliability. Fig. 14 shows the relationship between the width X of the trench and the particle size of the microcrystalline ruthenium layer. The interval w is 5 〇μπΐ, and the depth is 50 nm. When the width X is 1 μm, the maximum 値 is obtained, and the particle size is 12 nm. On the other hand, when y is l〇〇nm, when the X exceeds 〇.5μη, the particle size is 21 - 200935521, more than 20 nm, even if When the particle size is reduced by 3.5 μm, the particle size becomes smaller. Figure 15 shows the relationship between the depth y of the trench and the microcrystalline germanium layer. X is 〇·5μπι or more, and the particle size is the same as y, y is more than In the case of lOOnm, the particle size is not changed. In addition, various investigations are performed on the interval w. The same data is obtained in any range of φ 5 μιη < κ < 200 μιη. Further, the upper portion is formed without avoiding the gate electrode. In the case of the channel, there is no problem. In this case configuration, it is not necessary to design the groove in accordance with the structure of the TFT. The condition 16 for the plasma treatment using hydrogen shows the particle size of the microcrystalline germanium and the frequency of the plasma treatment. This is the result of measuring the particle size for the samples prepared in the foregoing examples and the modified parts. Q 13·56 ΜΗζ, 27 MHz, 66 MHz, 100 MHz, and the particle size is being implemented in the case where the processing time is short before the edge layer is formed. State 1 is shown in Fig. 5, and no seed crystal is provided. When compared, it can be seen that the front can be as short as 1 / 1 〇 or less by the presence of the seed crystal. Example 3 - 2 After the formation of the seed crystal shown in Fig. 13, the irradiation of the seed crystal (550 nm) was also rare, and the dependence of the excess particle size showed a larger change of 5 0 μηη. The occasion to the gate electrode of the gate electrode can follow the channel pattern. Review it. The pre-processing time and the strip of plasma treatment show that the frequency will increase and the gate will be saturated. The processing time with the sample is performed to reduce the excimer laser -22- 200935521 Figure 17 shows the relationship between the wide χ of the seed crystal and the particle size. The interval w is 50 μm. It can be seen that unlike the field in which laser irradiation is not performed as shown in Fig. 14, the depth y is 30 nm, and the particle size in the range of 0.5 μm to 3 μm is more than 20 nm', and stable microcrystalline germanium can be obtained in shallow trenches. This is effective for productivity improvement during mass production. In general, in the case of using a laser, in order to obtain uniformity of the film, uniformity of laser light is an important technical element. In the production method according to the present invention, the uniformity of the film can be obtained at the time of film formation after laser irradiation, so that the uniformity at the time of laser irradiation is not problematic. Now, in the present embodiment, the uniformity in the film or the leakage current of the TFT is considered to be no problem. This situation has great advantages in mass production manufacturing in terms of productivity and cost. In addition, the laser radiation does not have a particularly large effect on the relationship between particle size and processing time prior to plasma treatment (Fig. 16). Figure 18 shows the relationship between the depth y of the seed crystal and the particle size of the microcrystalline ruthenium layer. The interval w is 50 μm. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a prior art organic EL light-emitting element used in an active matrix method. Fig. 2 shows only the TFT having the organic EL light-emitting element of Fig. 1. Fig. 3 is a view showing an example of a TFT in which microcrystalline germanium is formed by PECVD (plasma chemical vapor deposition). Fig. 4 shows a thin film transistor related to the present invention. Figure 5 shows the relationship between particle size and processing time and frequency before plasma treatment -23- 200935521. Figure 6 shows the relationship between particle size and processing time and power prior to plasma treatment. Fig. 7(A) is a side view of a patterned seed, (B) is a plan view when a dot pattern is patterned, and (C) is a plan view when a pattern is patterned. Figure 8 shows the relationship between the seed size of the dot pattern and the particle size @ of the microcrystalline ruthenium layer. Fig. 9 shows the relationship between the interval w of the dot pattern and the particle size of the microcrystalline ruthenium layer. Fig. 10 shows the relationship between the particle size of the microcrystalline ruthenium and the processing time and frequency before the plasma treatment. Figure 11 shows the relationship between the thickness z of the seed crystal and the particle size. Fig. 12 shows the relationship between the interval w of the dot pattern and the particle size of the microcrystalline ruthenium layer. 〇 Figure 13 is a side view of the ditch. Figure 14 shows the relationship between the width X of the trench and the particle size of the microcrystalline germanium layer. Figure 15 shows the relationship between the depth y of the trench and the particle size of the microcrystalline germanium layer. Figure 16 shows the relationship between the particle size of the microcrystalline ruthenium and the processing time and frequency before the plasma treatment. Figure 17 shows the relationship between the width X of the seed crystal and the particle size. Figure 18 shows the relationship between the depth y of the seed crystal and the particle size of the microcrystalline ruthenium layer from -24 to 200935521. [Description of main component symbols] 100: Organic EL light-emitting element 1: Glass substrate _ 1 0 2 : Gate electrode 103: Gate insulating layer 0 104: Essential amorphous layer (a-Si) layer 105: η-type a- Si layer 1 0 6 : source electrode 1 0 7 : drain electrode 110: TFT 1 2 1 : interlayer insulating layer 122 : through hole 123 : lower electrode Q 124 : organic light emitting layer 1 2 5 : transparent electrode 400 : thin film electricity Crystal 4 04 = Essential Microcrystalline Layer 408: Protective Layer - 25 -