TW200929496A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating filMdisposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first filMdisposed on an inner wall of the above-described concave portion, a copper-containing second filMdisposed above the above-described first filMand filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first filMand the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80 DEG C to 120 DEG C.

Description

200929496 IX. Description of invention:

TECHNICAL FIELD OF THE INVENTION C FIELD OF THE INVENTION Field of the Invention 5 〇10 15 ❹ 20 This application is based on and claims the application of the present application No. 2008-163798, filed on Jun. 23, 2008, and the application at 2 〇〇 7 The priority benefit of the prior patent application No. 2007-295778, the entire disclosure of which is incorporated herein by reference. The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having a multilayer interconnection structure and a method of fabricating the same. BACKGROUND OF THE INVENTION In the conventional semiconductor integrated circuit device, a plurality of semiconductor elements are provided on a common substrate, and a multilayer interconnection structure is used to connect them. In the multilayer interconnection structure, an interlayer insulating film in which an interconnection pattern constituting the interconnection layer is buried is laminated. In the above multilayer interconnection structure, the lower interconnection layer and the upper interconnection layer are connected to each other via via holes provided in the interlayer insulating film. In particular, in recent ultra-fine, very high-speed semiconductor devices, a low dielectric constant film (so-called low-k film) is used as an interlayer insulating film to reduce signal delay in a multilayer interconnection structure (RC delay: resistor_capacitor) Delayed). In addition, a low-resistance copper (Cu) pattern is used as the interconnection pattern. The multilayer interconnect structure in which the Cu interconnect pattern is buried in the low dielectric constant interlayer insulating film is as described above because the patterned copper layer is difficult to use, so the so-called damascene process or The process of the dual damascene method in which interconnecting trenches or via holes are formed in advance in the interlayer insulating film. In the damascene process or the dual damascene process, the interconnect trenches or vias formed are filled with a Cu layer, and thereafter, too much on the interlayer insulating film (: 11 layers 5 by chemical mechanical polishing (CMP) At this time, if the Cii interconnect pattern directly contacts the interlayer insulating film, Cu atoms may diffuse into the interlayer insulating film to cause a short circuit and the like. Therefore, generally, the sidewalls of the interconnecting grooves or via holes are generally used. The surface and the bottom surface (in which the Cu interconnection pattern is disposed) are covered by a conductive diffusion barrier, a so-called barrier metal film covering 10, and a Cu layer is disposed on the barrier metal film. Generally, a high-refining metal such as a group Conductive vapors of (Ta), titanium (Ti) and town (W) or these high melting point metals are used as barrier metal films. On the other hand 'about the recent 45-nm generation and beyond, ultra-fine, very high-speed semiconductors The size of the device, the interconnecting trench or via formed in the interlayer insulating germanium, has been significantly reduced with miniaturization. As a result, the barrier metal film with high impedance described above is used to reduce the interconnection impedance to the desired Degree is in the case of desire It is necessary to minimize the film thickness of the barrier metal film formed in the fine interconnection trench or via hole. On the other hand, the sidewall surface and the bottom surface of the interconnection trench or via are continuously covered by the barrier metal film. In this case, the interconnecting grooves or via holes formed in the interlayer insulating film are directly bonded to the copper-manganese alloy layer (Cu-Mn alloy layer) in the Japanese Patent Laid-Open Publication No. 2003-218198. The present invention discloses a technique for forming a manganese ruthenium oxide layer having a thickness of 2 nm to 3 nm in the form of 200929496, and via Μη and an interlayer insulating film in the Cu-Mn alloy layer. The self-organization reaction between Si and oxygen, a MnSixOy composition acts as a diffusion barrier film at the interface between the above Cu-Mn alloy layer and the cool insulating film. 5 However, regarding this technology, it has been confirmed that One problem is that in the self-organizing layer having the MnSixOy composition, the concentration of the metal element (i.e., manganese (Mn)) contained in the film is low, and for this reason, the adhesion of the Cu film is insufficient. So 'Japan Lee Early Publication No. 2007-27259 describes - species barrier metal structure, Cu-Mn alloy having a high melting point barrier layer and a metal (e.g., Ta and Ti) combines configuration.

The above-mentioned barrier metal structure in which the Cu-Mn alloy layer and the high-melting-point metal (such as butyl 3 and bismuth barrier metal sisters) also have a desirable property, that is, the oxidation resistance is enhanced because of the case described below. 15 In recent years, in order to avoid signal delay, it has been proposed to use a porous low dielectric constant film as a low dielectric constant material constituting an interlayer insulating film. However, there are problems in this case: such a porous low dielectric constant material has Low density and easy to be damaged by plasma during production. It is easy to absorb moisture on the surface and inside of the damaged crucible. As a result, the porous low dielectric constant film is formed under the influence of the moisture 20 absorbed by the porous dielectric film. The upper barrier metal film is easily oxidized, and therefore, its performance as a diffusion barrier and adhesion to a Cu interconnection layer or a via plunger are easily damaged. However, if the above Cu-Mn alloy layer is used as such The seed layer in the structure, the Μη in the Cu-Mn alloy layer and the oxidizable part of the barrier metal film can be used as a diffusion barrier and as for the Cu interconnect layer or The south adhesion of the layer plunger can be maintained. Incidentally, in the case of forming a Cu interconnection layer by the electric money method, it is necessary to continuously cover the side wall surface and the bottom surface of the interconnection groove or the via hole in a manner of 5 The seed layer is formed. If the seed layer is discontinuous, the crack may occur in the interconnect or the pure plug during the electric ore. In the case where the seed layer is formed by the method of mineral reduction, it is generally considered that the seed has sufficient film thickness. The layers are formed on the sidewall surfaces and the bottom surface of the interconnect trench or via via re-splashing or the like, whereby the resulting seed layer reliably covers the sidewalls of the interconnect trench or via hole in a reliable manner. If such a method is carried out, it will become important to form a layer protruding portion on the trowel above the interconnecting groove or the through hole. If the protruding portion becomes important, the edge filled with the electric money which will be known later will be remarkable. This is reduced, and cracks are easily generated during the recording. On the other hand, the width of the vias or the diameter of the vias become smaller as a result of miniaturization of the semiconductor device. With this phenomenon, it is necessary to reduce the seed film. Thickness. However, special In the range where the seed layer is formed by the ore-killing method, it is difficult to cover the side wall surface and the bottom surface of the interconnecting groove or the through hole with a film having a sufficient thickness, especially for a highly miniaturized semiconductor device. Further, in the case where the low-intensity modulus is used as the interlayer insulating film, bending may occur in the cross-sectional shape of the interconnecting groove or the via hole after the etching. Regarding the side wall portion of the interconnecting groove having a large surface area, even when the seed layer is a continuous film, the film thickness may locally decrease due to fluctuations in film thickness. 200929496 If the seed layer in the side wall portion of the interconnecting groove The film thickness is locally reduced, as described above, in the initial stage of the step of forming a copper interconnection by the electroplating method, the film portion of the above-mentioned seed layer may be dissolved. The electroplating step is carried out using such a partially dissolved layer. In the case, the following door 5 problem may occur, that is, in the heat treatment step performed thereafter, cracks may occur in the place corresponding to the partial film portion of the seed layer. ° Cracks due to the slight dissolution of these layers are usually characterized by no missing filling just after plating. Cracks only occur after the heat treatment step. The reason for this is believed to be that the interconnection pattern itself is formed by a bottom-up filling mechanism at the time of electroplating, so that it is apparent that the Cu plating film is formed without cracks. However, the adhesion between the Cu plating film and the barrier metal film in which the seed layer has been dissolved is insufficient, and therefore, a rapid stress change due to the heat treatment performed thereafter causes cracks to be generated in such places. Examples of the related art in the related art include 15 Japanese Patent Laid-Open Publication No. 2007-141927, Japanese Patent Laid-Open Publication No. 2007-142236, Japanese Patent Laid-Open Publication No. 2007-173511, and U.S. Patent No. 6,136,707. Patent Publication No. 2007-281485, Japanese Patent Laid-Open Publication No. 2004-111926, Japanese Patent Laid-Open Publication No. 2006-24943, Japanese Patent Laid-Open Publication No. 2000-91271, Japanese Patent Early publication No. 2004-153274, Japanese Patent Laid-Open Publication No. 2005-51185, and Japanese Patent Laid-Open Publication No. 2001-160590. SUMMARY OF THE INVENTION Summary of the Invention 9 200929496 According to one embodiment of the present invention, a semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed over the semiconductor substrate, and one of the insulating films a concave portion, a copper-containing first film disposed on an inner wall of the concave portion, a copper-containing second film disposed above the first film and filling the concave 5-shaped portion, and the first film A layer containing a smear of oxide between the film and the second film. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A shows the effect of a Cu-Mn alloy layer in a known barrier metal structure; 10 Figure 1B shows the structure of the test piece used in the present invention; Figure 1C shows the copper interconnection immediately after plating; 1D is used to explain the phenomenon in the case of performing a known heat treatment immediately after electroplating; FIG. 2 is a diagram for explaining the principle of the present invention; 15 Fig. 3 is another diagram for explaining the principle of the present invention 4 is another diagram for explaining the principles of the present invention; 5A and 5B are diagrams for explaining other principles of the present invention; and FIG. 6 is another diagram for explaining the principle of the present invention; Figure 7 is another diagram for explaining the principle of the present invention; 20 Figure 8 is another diagram for explaining the principle of the present invention; Figure 9 is a phase equilibrium diagram of the Cu-Mn system; Figure 10A Another drawing for explaining the principles of the present invention; Fig. 10B is another drawing for explaining the principle of the present invention; Fig. 11 is another drawing for explaining the principle of the present invention; 200929496 Fig. 12 Another diagram for explaining the principles of the present invention; FIG. 13A is another diagram for explaining the principles of the present invention Figure 13B is another diagram for explaining the principle of the present invention; Figure 14 is a diagram for explaining the influence of the present invention; 5 Figure 15 is another diagram for explaining the influence of the present invention; Figure 16 is a view for explaining another aspect of the present invention; FIGS. 17A to 17P are views showing a manufacturing step of a semiconductor device according to a first embodiment of the present invention; and FIG. 18 is a view showing a structure of a semiconductor device according to the first embodiment; 10A to 19P are diagrams showing a production step of a semiconductor device according to a second embodiment of the present invention; and Figs. 20A to 20B are diagrams showing a modification example of the second embodiment of the present invention. t Embodiment 3 Detailed Description of the Preferred Embodiments 15 Occasionally 'About the Cu-Mn alloy layer used to form the barrier metal structure by bonding with the above-mentioned high melting point barrier metal medium, when the above-mentioned Cu-Mn alloy layer is Μη As the concentration becomes higher, the reliability of the interconnection increases. Figure 1 shows the results of a 50-hour test for the resistance to stress migration of the test structure shown in Figure 1B based on heat at a temperature of 150 ° C to 200 ° C. First, as shown in Fig. 1B, a low-k film 12 of SiOC or the like is provided on the substrate 11. In the low-k film 12 of the above SiOC or the like, an interconnection trench 12T having a width of 65 nm to ΙΟμm and a depth of about 150 nm is provided. Moreover, the above-mentioned interconnect trench 12T is filled with the Cu interconnect pattern 12C, and a Ta barrier metal film 11 200929496 12B interposed therebetween, and the Ta barrier metal film covers the sidewall surface and the bottom surface of the interconnect trench and has A thickness of 3 nm to 5 nm. Further, a low-k film 14 having another SiOC or the like having a film thickness of 50 to 150 nm is provided on the low-k film 12 of the above-mentioned SiOC or the like, and a tantalum carbide film having a thickness of 1〇5 to 1〇〇nm. The (SiC film) 13 is interposed therebetween. A low-k film 16 having another SiOC or the like having a film thickness of 120 to 180 nm is provided on the low-k film 14 of the above-described SiOC or the like, and a SiC film 15 having a thickness of 1 Å to 10 〇 11111 is interposed therebetween. In the low-k film 16 of the above SiOC or the like, an interconnection trench 16T having a width of 65 nm to 10 ❹ 10 μm and a depth of 120 to 180 nm is provided on the SiC film 15 while passing through the SiC film 15 at the same time, so that the above-mentioned SiOC Or the low-k film 14 of the analog is exposed. In the above interconnecting trench 16T, a through hole 14V having a diameter of 70 nm is provided in the above

On the low-k film 14 and the SiC film 13 of SiOC or the like, and simultaneously pass through the above *

The low-k臈14 and SiC film 13 of SiOC or the like exposes the above-described Cu interconnection 15 pattern 12C. Moreover, the interconnect trench 12T is filled with the Cu interconnect pattern 12C, and a Ta barrier metal film 12B is interposed between the interconnect pattern 12C and the interconnect trench 12T. The interconnect trench 16T is filled with a Cus connection pattern 16C with a Ta barrier metal film 16B interposed therebetween, and the Ta barrier metal film covers the sidewall surface of the interconnect trench ι6 and the bottom surface of the trench and has a thickness of 3 to 15 nm. The portion of the Cu interconnection pattern 16C filled with the via hole 14V constitutes a Cu via plug ι6ν. a plurality of test structures having the above configuration are disposed in respective regions (I, π, etc.) on the above-mentioned ruthenium substrate 丨j, but the width of the above-mentioned interconnection pattern 12c or 16c may be within the above range Various changes. 12 200929496 At this time, in the test structure shown in FIG. 1B, a Cu-Mn alloy layer 12M or 16M having a thickness of 6 〇 nm is provided on the above barrier metal film i2B or 16B and the above-described Cu interconnection pattern 12C or 16C. Between the above barrier metal film 12B or 16B and the Cu via plunger 16V. 5 In the test structure shown in Fig. 1B, the 'Cu interconnect pattern 12C is formed by a metal damascene process (including seed layer formation, electroplating, and chemical mechanical polishing (CMP)). The Cu interconnect pattern 16C and the via plunger 16V are formed by a dual damascene process including seed layer formation, plating, and CMP. Further, the barrier metal films 12B and 16B and the Cu-Mn alloy layers 12M and 16M are formed by a sputtering method in which a Cu-Mn alloy is used as a standard at a temperature lower than or equal to room temperature. Fig. 1A shows the results of examination of the stress migration resistance of the test structure shown in Fig. 1B by using the above conditions. In Fig. 1A, except that the Cu-Mn alloy layers 12M and 16M are not provided and 15 is used as a reference standard, the sample indicated as "pure Cu" is a sample having the structure shown in Fig. 1B above. In the middle, the vertical axis represents the number of missing contacts measured, and the value has been normalized by the above reference standard sample. In Fig. 1A, a sample expressed as "cu-〇.2at.%Mn" shows 0.2 atom A percentage of the - 的 Cu-Mn alloy is used as an example of the Cu-Mn alloy layers 12M and 16M in the structure of the junction 20 shown in the ugly figure. It is shown that the sample of Cu_〇5 shows that the €11^11 alloy containing 1^11 of 〇·5 atomic percent is used as an example of the Cu_Mn alloy layers 12M and 16M in the structure shown in Fig. 1B. A sample expressed as "Cu_2at.%Mn" shows that a Cu-Mn alloy containing 2 atomic percent of Μη is used as the structure in Fig. 3 〇1_河11合13 200929496 gold layer 12M and 16M case. As is clear from FIG. 1A, in the case where the above-described Cu_Mn alloy layers 12M and 16M are provided, the number of missing contacts is reduced to a quarter or less than the case where the Cu-Mn alloy layers 12M and 16M are not provided. It is lower. In particular, it is clear that the number of occurrences of missing contact can be further reduced by increasing the concentration of Μη in the above Cu-Mn alloy layers 12M and 16M. However, in the case where the Cu-Mn alloy layers 12 and 16 are adjacent to the high-melting-point barrier metal films 12B and 16B, and the Μn concentration in the Cu-Mn alloy layers 12M and 16M is allowed to increase, the Cii interconnection pattern 12C or 16C Or Cu via column © 10 plug 16V containing Μη. Since the Cu via plug 16V contains Μη, problems occur when the impedance value in the Cu interconnection pattern 12C or 16C or the Cu via plug 16V is increased. Occasionally, in order to form a good copper interconnection by electroplating in the interconnection pattern 12c or 16C shown in FIG. 1B, a seed layer as an electrode in electroplating (not showing the Cu species in the figure) The layer or Cu-Mn alloy layer 12M or 16M) must have sufficient film thickness, a continuous layer must be formed, and must exhibit good stepwise coverage. However, when the interconnect width w of the interconnect trench 12T or 16T is decreased, it is very necessary to form a Cu seed layer or a Cu-Mn alloy layer 12M or 16M which is not shown in the drawings with sufficient film thickness and good step coverage. Difficulties. In particular, in the case where the Cu seed layer or the Cu-Mn alloy layer 12M or 16M which is not shown in the drawing is formed by a sputtering method, if the interconnect width W becomes 9〇ηηη or less, the interconnection is The film thickness of the side wall portion of the groove 12T or 16T will be locally reduced 'so that the film thickness variation occurs. If the film thickness of the Cu seed layer or the Cu-Mn alloy layer 12M or 16M is locally reduced in the 12 29 or 16 Τ side surface portion of the interconnect 14 200929496 5 10 15 Ο 20, the above-mentioned Cu seed layer not shown in the drawing Or a very small partial film portion of the Cu-Mn alloy layer 12Μ or 16Μ dissolves in the initial stage of forming the copper interconnection, and the copper interconnection becomes a Cu interconnection pattern 12c or 16C via the subsequent implementation, and occurs The problem that the heat treatment step is subsequently applied to the portion of the (10) layer or the Cu-Mn alloy layer 12M or 16M which is not shown in the drawing corresponding to the side surface portion of the interconnecting groove 12T or 16 Where the film portion is generated, the crack generated by the dissolution of the Cu layer or the Cu_Mn alloy layer 12M or the C-Mn alloy layer 12M in the pattern is characterized in that the interconnection pattern 12C or 16C passes through the electric ore and the m_up The filling mechanism is filled, and no missing filling is seen at this time, as shown in the ic diagram, but after the heat is applied, a crack is generated, such as the first paste*. The reason for this phenomenon is believed to be that in the extremely small dissolved place, the adhesion between the _ and the barrier metal film 12B or between them is in an insufficient state, and therefore, the financial assets are subjected to stress due to the subsequent reduction. Rapid change. Formed on the crucible substrate 11 and heat treated, 'using a variety of different patterns simultaneously

In the basic study of the present invention, the inventors of the present invention examined changes in the interconnection impedance in the following cases, with reference to the relationship shown in the sample shape 15 200929496 described in the figure (7). Figure 3 shows an overview of the samples used in the experiment shown in Figure 2. In the third drawing, elements corresponding to the above elements are denoted by the same element numbers as those described above, and further description thereof will be omitted. In Fig. 3, the portion of the above-described elements shown in Fig. 1B in which the interconnection pattern 16B and the barrier metal film 16B are shown in Fig. 1 is shown in the drawings. Fig. 3 is a cross-sectional view showing an example in which the width W of the Cu interconnection pattern 16C is small (as shown in the area II). Clearly, in this case, the contact area between the Cu interconnection pattern 16C and the interlayer insulation © 10 film 16 is larger than that of the entire Cu amount (presented by the cross-sectional area of the Cu interconnection pattern 16C) than the Cu interconnection. An example in which the width W of the pattern 16C is large (as shown in the area I). Therefore, the relationship shown in Fig. 2 above, that is, the rate at which the interconnection impedance increases when the width W of the interconnection pattern is decreased. The case of the drop is noted. It has been judged that some of the above-mentioned Cu interconnection patterns 16C and I5 cool insulating film 14 or 15 and the interface region between the interlayer plug i6v and the interlayer insulating film 14 or 15 which are not shown in the drawing have occurred. Form of chemical reaction. Fig. 4 shows the relationship between the thickness of the Cu-Mn alloy layer 16M and the rate of increase of the impedance. The example of the increase in impedance is that in the sample of 20 shown in the above figure, the interconnect width W is specified as 3 Gonggua. This is in Figure 4,

The film thickness of the Cu-Mn alloy layer 16M was measured on the upper surface of the above-mentioned interlayer insulating layer (4), i.e., on a flat surface formed by the CMP method. The reference value of the above-mentioned impedance increase rate (an example in which the 〇_Cu Mn alloy layer is not provided. Further, in the experiment shown in Fig. 4, the sample shown in the above-mentioned 汨16 200929496 is also a nitrogen atmosphere at 400 ° C. The heat treatment is performed for 30 minutes. 5 ❹ 10 15 ❹ 20 As clearly shown in Fig. 4, the Cu-Mn alloy layer 16M contains 0.5 atomic percent of Μη, and when the film thickness of the Cu-Mn alloy layer 16M is increased, 'Cu The rate at which the impedance of the interconnection pattern 16C is increased is almost linear. This means that if the Cu-Mn alloy layer 16M having a large film thickness is placed between the Cu interconnection pattern 16C and the barrier metal film 16B, the above Cu- Under the influence of Μη in the Mn alloy layer 16M, the impedance of the Cu interconnection pattern 16C is increased. However, the relationship shown in Fig. 4 is extrapolated toward the direction in which the film thickness of the Cu-Mn alloy layer 16M is reduced. 'The film thickness of the Cu-Mn alloy layer 16M becomes equal to about 15.5 nm. In this case, it is clear that even when the Cu-Mn alloy layer 16M containing Μη is provided in the above-described Cu interconnection pattern 16C or Cu interlayer The impedance of the Cu interconnection pattern 16C between the plunger 16V and the Ta barrier metal film 16B The rate of increase is zero, that is, the phenomenon of impedance increase does not occur. This means that Μη does not have any influence on the impedance value of the Cu interconnection pattern 16C. The result is 'in order to understand the relationship and the 4 The meaning of the relationship shown in the figure, the sample used for the experiment was subjected to elemental analysis using a scanning transmission electron microscope (STEM) using energy dissipative spectroscopy (EDS). Fig. 5A shows the cross section of the Cu interconnection pattern 16C based on the above STEM. Fig. 5B shows a particular X-ray intensity distribution obtained by scanning in the depth direction in Fig. 5A. In Fig. 5A, the "barrier metal" corresponds to the Ta barrier metal film 16B in the sample shown in Fig. 1B. A Cu-Mn alloy layer 17 having an initial film thickness of 15.5 nm is formed on the barrier metal while being held between the barrier metal and the Cu interconnection pattern 16C. It has been found that the above heat treatment is performed by 40 (the nitrogen atmosphere of TC). At 30 minutes, the fierceness in the Cu-Mn alloy layer 16M is absorbed into the cu interconnect pattern 16C. Moreover, it has been found that with this phenomenon, the concentration of Μη in the barrier metal film 5 _6B is remarkably increased, as in 5B. The EDS spectrum is clearly shown. This is attributed to the fact that since the above-mentioned 400 (.: heat treatment is applied to the structure shown in the above FIG. 1B, substantially all of the Μη atoms in the above Cu-Mn alloy layer 16M will It is transferred to the barrier metal film 16B, so the Cu-Mn alloy 10 layer 16M is converted into a Cu layer substantially free of Μη. Moreover, this is attributed to the Μη concentration of 0.5 atomic percentage in the above-mentioned Cu-Mn alloy layer 16M. In the case of the above heat treatment, substantially all of the Μη atoms in the film can be transferred to the Ta barrier metal film 16 Β until the film thickness of the above-described Cu-Mn alloy layer 16 变为 becomes as high as about 15.5 nm. As a result, the 浓度n concentration 15 in the Cu interconnection pattern 16C can be lowered to a concentration which has no influence on the interconnection resistance. The Μη atom transferred to the barrier metal film 16Β, as described above, forms a solid solution having the above-described barrier metal film 16Β. However, a part of the above Μη atoms react with oxygen from the oxygen-containing interlayer insulating film 14 or 16 to form a PCT 11 oxide. The oxygen-containing interlayer insulating film 14 or 16 is present adjacent to the above-mentioned barrier 20 metal film 16 。. This Μ 氧化物 oxide is placed inside the above barrier metal film ΐ 6 处 at the interface between the above barrier metal film 16 Β and the Cu interconnection pattern 16C, or at the interface between the barrier metal film 16B and the interlayer insulating film 14 or 16 The inside of the above barrier metal film 16B is stably held. The results shown in Fig. 4 and Figs. 5A and 5B are related to the above-mentioned cu_Mn combination 200929496. The gold layer 16M contains 0.5 atomic percent of Μη and the Cu-Mn alloy layer 16M has a film thickness of 15 nm. It is believed that substantially all of the Μη atoms in the film can be transferred to the film thickness of the Cu-Mn alloy layer 16M of the barrier metal film 16B, that is, the critical film thickness, and also the Μη concentration in the above-mentioned Cu-Mn alloy layer 5 16M. related. Therefore, the inventors measured the rate of increase in impedance of the Cu interconnection pattern 16C having a width W of 3 μm, in which a Cu-Mn alloy layer having various Μη concentrations was used as the above Cu- in the sample having the structure shown in Fig. 3. Mn © alloy layer 16M. 10 Fig. 6 shows the measurement results of the impedance increase rate of the Cu interconnection pattern 16C having a width W of 3 μm. In Fig. 6, the vertical axis represents the rate of increase in impedance with respect to the case where the above-described Cu-Mn alloy layer 16M is not provided, and the horizontal axis represents the value obtained by multiplying the thickness of the Cu-Mn alloy layer 16M by the concentration of Μη in the film. . This value corresponds to the total amount of Μη atoms in the above-mentioned Cu-Mn alloy layer 16Μ. As shown in Fig. 6, when the total amount of Μη atoms in the above-mentioned Cu-Mn alloy layer 16Μ is increased, the rate of increase in the impedance of the above-described Cu interconnection pattern 16C substantially increases linearly. It is believed that the total amount of Μη atoms at zero impedance increase rate is the Μn threshold that can be transferred to the barrier metal film 16Β at the relevant Μη concentration. If the number of Μn in the above-mentioned Cu-Mn alloy layer 16Μ exceeds the Μn threshold amount 2〇 (hereinafter referred to as “Μη consumption amount”), the Cu—Mn alloy layer 16Μ remains on the barrier metal film 16B after the heat treatment. This causes an increase in the impedance of the Cu interconnection pattern 16C. Fig. 7 shows the relationship between the Μη consumption (indicated as the horizontal axis interpolation in Fig. 6) and the Μn concentration in the above-mentioned Cu-Mn alloy layer 16Μ. 19 200929496 As clearly shown in Fig. 7, the proportionality is represented by the equation y = 15·489 ,, which is maintained at the above Μη consumption (y-axis) and the Μη concentration (X-axis) in the Cu-Mn alloy layer 16Μ. The slope between them is 15 489. It should be noted that the slope shown in Fig. 7 has a dimension of thickness (nm). 5 that is, the relationship equation y = 15_489x shown in Figure 7 indicates that

In the case where the thickness of the Cu-Mn alloy layer 16M is 15 489 mn, the increase in the Mn consumption is proportional to the Μn concentration X of the film 10. Further, it is shown that if the film thickness on the flat surface of the above-mentioned Cu-Mn alloy layer 16 is specifically 15.489 nm or less, all the Μ in the film is subjected to heat treatment at any concentration. The atoms can be transferred to the Ta barrier metal film 16B. The thickness of this 15.489 nm coincides with the critical film thickness of about 15.5 nm of the Cu-Mn alloy layer 16M estimated based on the relationship shown in Fig. 4 above. Fig. 8 shows the relationship between the rate of increase in impedance and the amount of Μ consumption in the case of using Ta barrier and Ti barrier. As shown in the figure, the occurrence of the critical Μ consumption shown in Fig. 6 of Fig. 6 can be observed not only in the case where the Ta film is used as the above-described barrier metal film 16B, but also in the Ti film as the above barrier. It can also be observed in the case of the metal film 16B. As shown in the figure, the difference in Mn consumption is within the experimental error range, and the experimental error range is indicated by the arrow of the horizontal axis section, so the two cases are very close. This is because the amount of oxygen generated by sandwiching the 20-layer insulating film does not vary depending on the type of barrier metal formed in the film on the interlayer insulating tape. As a result, it is clear that the above conclusion is not limited to the Ta barrier film. In Fig. 8, the line indicated by Ta BRM is an example shown in Fig. 6, in which a Ta barrier metal film is used as the barrier metal film 16B and it is shown that (?11_]^11 and 200929496 gold layer 16M Specifically, a case of 0.5 atomic percent. On the other hand, a line represented by Ti BRM is a Ti barrier metal film which is used as an example of the above barrier metal film 16B. In this case, the concentration of Μη in the above Cu_Mn alloy layer 16M is also specified. It is the same 〇·5 atomic percentage. 5 As shown in Fig. 8, in the case where the Ti film is also used as the above-mentioned barrier metal film 16Β, when the number of Μn in the Cu-Mn alloy layer 16M is decreased, Cu interconnection The rate of increase in impedance of the pattern is also reduced. However, it is clear that the presence of Μη (in the range of Μη to 77 atom%.nm) does not appear to cause an increase in impedance. 10 Μη》 The phase equilibrium diagram of the Cu-Mn binary system shown in Fig. 9 is described, and the relationship shown in Fig. 7 can be applied to the Μη concentration range. As clearly shown in Fig. 9, the temperature range is 4 〇〇. : and composition of the Μη concentration in the Cu-Mn alloy Among the 15 cases with a range of up to 3 atomic percent, the Cu-Mn alloy can exhibit a single phase. However, if the concentration of Μη in the Cu-Mn alloy is increased to more than 30 atomic percent, Μη begins to deposit and the Cu-Mn alloy phase appears. The two-phase state of the Μη phase. Therefore, as shown in Fig. 10, the relationship between the consumption of Μη shown in Fig. 7 increases with the concentration of Μn in the above-mentioned Cu-Mn alloy layer 16Μ, until the above-mentioned Cu- It is effective that the concentration of Μ in the Mn alloy layer 16 到达 reaches about 30 atomic percent, and the value of Μ η consumption reaches a maximum value of 465 atomic %·Nm. However, if the value exceeds this value, the maximum value is At 465 atomic percent·nm, the value of Μη consumption becomes fixed. As a result, as shown in Fig. 10, when the range of Μη 21 200929496 concentration X in the Cu-Mn alloy layer 16Μ is the highest at about 30 atomic percent. The maximum film thickness y on the flat surface of the Cu-Mn alloy layer 16M (which does not cause an increase in the impedance of the above-described 〇1 interconnect pattern 16C) is 15.489 nm or about 15 nm. Μη in the above-mentioned Cu-Mn alloy layer 16M Concentration above about 30 atoms above In the case of the concentration ratio of 5, the maximum film thickness y follows the hyperbolic relationship of y = 465 / 。. In other words, the maximum film thickness continuation maintains the total amount of Μ η (xxy) in the above-mentioned Cu-Mn alloy layer 16 为 is 465 atoms. It is clear from the relationship of the percentage .nm (XXy = 465). It can be clearly seen that in the above-described Cu interconnection pattern having a damascene or dual damascene structure (as shown in FIG. 1B), the interlayer 10 is formed therein. The concave portions in the insulating film or in the insulating film 12 or 14 to 16 are each filled with the Cu interconnection pattern 12C or 16C' and the high melting point barrier metal films 12B and 16B and the Cu-Mn alloy layer 12M or 16M are interposed therebetween. In the above-mentioned Cu-Mn alloy layer 12M or 16M, the concentration of Μη is less than 30 atomic percent (for example, in a concentration range of more than 0.2 atomic percent and less than 30 atomic percent (as shown in Figures 6 and 7)) In the case of the above-mentioned Cu-Mn alloy by making the film thickness on the flat surface of the above-mentioned Cu-Mn alloy layer 12 Μ or 16 特定 specific to less than 15.489 nm or about 15 nm (for example, 'in the range of 1 nm to 15 nm) Substantially all of the η η atoms in the layer 12M or 16 可 can be transferred to the high melting point barrier metal film 12 Β or 16 各自, respectively. Therefore, the concentration of Μn atoms in the above-mentioned Cu-Mn alloy layer 12 Μ or 16 Μ 2 下降 is lowered to a concentration which does not affect the Cu resistance, and an increase in the impedance of the Cu interconnection patterns 12C and 16C can be avoided. Further, even in the case where the Μn atomic concentration X in the above Cu-Mn alloy layer 12M or 16M exceeds about 30 atomic percent, the film thickness y is made on the flat surface of the above-described Cu-Mn alloy layer 12M or 16M ( The unit is nm) special 200929496 5 ❹ 10 15 Lu 2 is determined to be less than or equal to the film thickness given by y$465/x, so that substantially all of the Μη atoms in the above Cu-Mn alloy layer 12M or 16M can be Each of them is transferred to the south melting point barrier metal film 12A or 16Β, so that the impedance increase of the Cu interconnection patterns 12C and 16C can be avoided. For example, in the case where the above Cu-Mn alloy layer 16M contains 50 atomic percent of Μη, it is recommended to form the above Cu-Mn alloy layer in such a manner that the film thickness measured on the flat surface is equal to or less than 9.3 nm. 16M. In the case where the above Cu-Mn alloy layer 16M contains 80 atomic percent Μη, it is recommended that the above-described Cu-Mn alloy layer 16M be formed in such a manner that the film thickness measured on the flat surface is 5.8 nm or less. In the case where the above Cu-Mn alloy layer 16M contains 100% atomic percentage η, it is recommended to form the above-described Cu-Mn alloy layer 16M in such a manner that the film thickness measured on the flat surface is 4.7 nm or less. That is, in the case where the above-described Cu-Mn alloy layer 16M is formed in such a manner that the film thickness measured on the flat surface is equal to or less than 4.7 nm, the Μn concentration in the above-described Cu-Mn alloy layer 16M can be specified to exceed 0 atomic percentage and any concentration within the range of 100 atomic percent or less. Figures 6 to 8 relate to a Cu interconnection pattern be having a width W of 3 μm. However, it is clear that the above results can be applied to interconnect patterns having other interconnect widths or via plug diameters. As described above, the barrier metal films 12B and 16B described above are not limited to the Ta film, and may be a metal film containing at least one high melting point metal element such as Ta, Ti, and more Zr or Ru. The above heat treatment step is not limited to 400. Heat treatment under a nitrogen atmosphere of C, and 23 200929496 is that it can also perform heat treatment at a temperature of 1 TC (TC to 4 〇 (in the range of TC, such as nitrogen or Ar). Figure 11 shows a typical obtained From the structure of the following example, in the structure shown in the above FIG. 1B, a concentration range of Μη is between 5 〇·2 atom% and 30 atom% and the film thickness is 15 nm.

The Cu-Mn alloy layer was 16M, and the resultant structure was heat-treated under a nitrogen atmosphere of 4 °C. In the eleventh embodiment, the above-described elements are denoted by the same component numbers as those previously described and their further explanation will be omitted. In the above-mentioned Cu-Mn alloy layers 12M and 16M, substantially all of the Μη atoms in the Cu-Mn alloy layers 12M and 16M are transferred to the Ta barrier metal by the above heat treatment. At the films 12b and 16B, the Μη concentration has dropped to such an extent that it has no effect on the impedance. Further, due to the removal of such Μη, with the above-described Cu interconnection patterns 12C and 16C, the region where the Cu-Mn alloy layer 16M is first formed has been replaced by the cu films 12C1 and 16C1. 15 However, as shown in Fig. 11, the oxide thin layers 120χ and 16〇χ formed by bonding oxygen atoms to the Μη atoms are still formed on the surface portions of the Cu-Mn alloy layers 12M and 16M first. The above-mentioned (^ interconnection patterns 12c and 16C are partitioned into the above-described regions 12cl and 16cl in which the Cu-Mn alloy layers 12M and 16M are first presented, and the regions 2012 and 12c2 in which the Cu interconnection patterns 12C and 16C are first presented. Figure 12 is a map of a second ion mass spectrometer (SIMS) showing Cu, Μη, and oxygen atom distribution. In this figure, the pattern is determined by the Cu interconnection pattern shown in Fig. 11 after heat treatment. This includes the region in which the Cu-Mn alloy layer 12M first appears. 200929496 As clearly shown in Fig. 12, a high concentration of oxygen reaching 102 Å atoms/cm3 can be observed in the surface portion first exhibited by the Cu-Mn alloy layer 12M, and With the oxygen concentration, the Μη concentration also occurs at the same position. Fig. 13 is a view showing the state of the structure shown in Fig. 1, which is formed after the Ta barrier metal film 12 is formed in the interconnection groove i2T, The Cu-Mn alloy layer 12M' is further formed and transferred to the Cu film forming chamber via a vacuum transfer chamber such as a single wafer processing apparatus. Fig. 13B shows the state of the structure shown in Fig. 1B, which is in the Ta barrier The metal film 16B is formed on After the trench 16T and the via 14V, 10 further forms a Cu-Mn alloy layer 16M' and is transferred to the Cu film forming chamber via a vacuum transfer chamber such as a single wafer processing apparatus. See Figures 13A and 13B. Oxygen cannot be completely driven out of the vacuum transfer chamber of a single wafer processing equipment. Even under vacuum, a significant concentration of oxygen is operatively contained in the vacuum atmosphere. Therefore, 15 atmosphere oxygen Absorbing the surface of the Cu-Mn alloy layers 12M and 16M and reacting with the respective Μη atoms in the Cu-Mn alloy layers 12M and 16M. As a result, the above-mentioned Μn oxide thin layers 120 χ and 160 χ are formed on the surface, And each of them is separated from the surfaces of the barrier metal films 12B and 16B by a distance corresponding to the film thickness of the Cu-Mn alloy layer. As clearly shown in Fig. 12, even when the concave portions shown in Figs. 13A and 13B are respectively 20 The ground is filled with Cu interconnection patterns 12C and 16C, and thereafter heat treatment is performed, and the above-mentioned Μn oxide layers 120x and 160 χ are maintained at the original positions. That is, the NMOS oxide thin layers 120 χ and 16 in the Cu interconnection patterns 12C and 16C. Awkward Now, and the distance between the barrier film 12 and the 16 Β surface of each of the barriers 25 and 29 496, respectively, shows a clear record of the process, in which the Cu-Mn alloy layers 12M and 16M are first formed on the barrier metal films 12B and 16B, and then, the above Cu The Μη atoms in the -Mn alloy layers 12M and 16M are each transferred to the barrier metal film 12Β and 16Β. 5 In the above experiment, a Ta film having a film thickness of about 6 nm was formed as the above barrier gold.

The membranes 12B and 16B. When the film thicknesses of the barrier metal films 12B and 16B described above are at least in the range of 3 nm to 15 nm, the above mechanism can be effectively operated to remove the Μη atoms from the Cu-Mn alloy layers 12M and 16M to the barrier metal films 12B and 16B. ❹ 10 Fig. 14 is a diagram in which the result relating to the sample having the structure shown in Fig. 11 (the "invention" in the drawing) is added to the pattern shown in Fig. 1A. In Fig. 14, the sample of the present invention is a sample containing 2 atomic percent of Μη in the above Cu_Mn alloy layers _ 12M and 16M. As clearly shown in Fig. 14, the crack due to stress migration can be effectively reduced by the configuration shown in Fig. 11. Fig. 15 is a view showing the pattern of the stress change with respect to the heat treatment time in the case where the copper plating film formed by the plating method was heat-treated at a temperature of 120 ° C, 100 ° C and 80 ° C. In Figure 15, the change in stress is determined by measuring the surface curvature of the wafer at ambient temperature. 20 As clearly shown in Figure 15, the stress of the copper coating changes due to heat treatment, but the stress change decreases with time, and the film is stabilized. Such a reason is believed to be the growth of Cu grains in Cu. As clearly shown in the relationship shown in Fig. 15, in order to achieve the goal of stabilizing the crystal grains due to stress relaxation, a heat treatment temperature of at least 80 ° C or higher, particularly 12 Å.匸 26 200929496 or higher heat treatment temperature is necessary, and the treatment time must be 60 seconds or more' more preferably 90 seconds or more. From the viewpoint of the throughput of the semiconductor device, it is desirable to complete the heat treatment in a short time. It is clear that for the case of performing heat treatment at a temperature of 100 ° C or more, the heat treatment time is good for 250 seconds. On the other hand, if the temperature is 8 (TC or less, it is impossible to achieve desired film stabilization in a realistic time. Fig. 16 shows the CMP step in the interconnection pattern 12C (as shown in Fig. 1D) The results of the inspection of several defects and the results of the inspection of several defects due to the stress migration of the test structure shown in Fig. 1B, the case of Fig. 1B is the sample shown in Fig. 1B. The Cu-Mn alloy layers 12M and 16M contain Μη′ of any concentration and are filled with Cu layer by electroplating, and heat treatment is performed at a temperature of 15 (TC, 100 ° C, and 25 ° C (in the experiment, "25. (:,, The heat treatment is not actually performed) and the result of removing the excess Cu layer by the CMP method to obtain the interconnect pattern 12C. 15 As clearly shown in Fig. 16, 'the number of defects after the CMP step can be reduced when the heat treatment temperature is lowered. For example, it is clear that the heat treatment temperature is 150° (the defect in the case, when the heat treatment temperature is ι〇〇·χ, it can be reduced by 30% or more, and the heat treatment temperature is 12〇. : When it is reduced by 20% or more. 20 On the other hand 'With regard to stress migration resistance, at 150 ° C and 100. (: no major difference was observed between the heat treated samples, but slightly observed at the lower temperature (ie near 100 ° C) side Improvement. It is clear that 'the stress migration resistance will be severely damaged only in the case where heat treatment is not performed. 27 200929496 As described above, as shown in the figure of Fig. 16, it is shown in the first In the case where the Cu-Mn alloy layers 12M and 16M in the sample contain any concentration of iMn, the 'stress-resistant mobility can be improved semi-finished, and after the interconnection diagrams 12C and 16C are filled through the Cu layer of electric ore, The temperature range is 8 〇. The heat treatment is performed between 匸 and 5 120 c. The defect from the local dissolution of the seed layer can be reduced by 20% or more. The first embodiment 17A to 17P show the first embodiment according to the present invention. The method of using the dual damascene process to form the multilayer interconnection structure is as shown in Fig. 17A, the interconnection trench 22T corresponding to the predetermined interconnection pattern is formed on the insulating layer provided on the semiconductor substrate 21. On the film 22, the semiconductor substrate 21 is placed There are a transistor and a crane plug (which are not shown in the drawings). Further, on the insulating film 22, a 15 barrier metal film 22 which conforms to the cross-sectional shape of the above-mentioned interconnecting groove 22τ is splashed by Formed by a plating method, an atomic layer deposition (ALD) method, or the like, containing at least one high melting point metal element (eg, Ta, Ti,

The barrier metal film 22B of Zr or Ru) covers the sidewall surface © of the above-described interconnection trench 22τ and the bottom surface, and has a film thickness of 1 to 15 nm. The barrier metal film 22B is not limited to the metal film '. In addition to the metal film containing at least one metal element selected from the group consisting of Ta, Ti, and Zr^Ru 20, the barrier metal film 22B may be TaN, TiN or A conductive metal nitride film of the like. As shown in Fig. 17B, a Cu-Mn alloy layer 22 having a cross-sectional shape conforming to the above-described interconnecting groove 22T and containing Μη is formed by the sputtering method on the above-mentioned barrier metal film 22B shown in Fig. 17A. Among them, for example, Cu-Mn 28 200929496 5 ❹ 10 15 φ 20 alloy is used as a standard in a Ar atmosphere of 10-1 Pa, and the substrate temperature is lower than or equal to room temperature, and 10 kW of plasma power is input. At this time, in the case where the Μη concentration in the above Cu-Mn alloy layer 22M is about 30 atom% or less (for example, between 0.2 atomic percent and 30 atomic percent), the above Cu-Mn alloy layer 22M is on a flat surface. It is formed to have a film thickness of about 15 nm or less (for example, in the range of 1 to 15 nm). On the other hand, in the case where the concentration of Μn in the Cu-Mn alloy layer 22M exceeds 30 atomic percent, the above-described Cu-Mn alloy layer 22 is formed such that the film thickness on the flat surface becomes less than or equal to The film thickness y obtained by the equation y = 465 / x, where x represents the concentration of Μη atoms in the above Cu-Mn alloy layer 22M. As shown in FIG. 17C, the Cii film 22C1 having a shape conforming to the cross-sectional shape of the interconnecting trench 22 is formed as an electroplated seed layer by a sputtering method or a CVD method, for example, to have a plating layer of about 4 Film thickness of 〇nm. As shown in Fig. 17D, the Cu film 22C2 is formed on the structure shown in Fig. 17C by using the Cu film 22C1 as an electroplated seed layer, and the interconnect trench 22T is filled in this manner. Further, as shown in the figure, the structure shown in the above-mentioned 17D is polished by the CMp method until the surface of the above-mentioned insulating film 22 is exposed, thus obtaining a structure in which the above-described interconnecting trench 22T is filled with Cu. Connect the pattern 22C. As shown in Fig. 17F, an etch stop film 23 containing siC is formed on the first structure to cover the above-described Cii interconnection pattern 22C and has a film thickness of from 1 Å to 100 nm. The film formation of such an etch stop film 23 is typically carried out at a temperature of 400 C. Therefore, the above-described film 22C1 and Cu film 22C2 constituting the above-described €11 interconnection pattern 22c are fused and formed into a single film. By the heat treatment at this time 29 200929496, the Μη atoms in the above Cu-Mn alloy layer 22M are transferred. Into the barrier metal film 22, the original Cu-Mn alloy layer 22M disappears in the above-described Cu interconnection pattern 22C. However, a thin layer of Μn oxide is formed corresponding to the original Cu-Mn alloy layer. The position of the surface of 22 ,, and the distance of 5 corresponding to the film thickness of the original Cu-Mn alloy layer 82M is separated from the surface of the above barrier metal film 22B, as indicated by a broken line 220x of Fig. 17F. Therefore, the above Cu interconnection pattern 22C is formed from the region 22cl and the region 22c2, wherein the region 22cl is present with the original cu-Mn alloy layer 22M, and the region 22c2 is present with the original Cu films 22C1 and 22C2. ® 10 as shown in Fig. 17G, for example, plasma CVD The method comprises an interlayer insulating film 24 having a thickness of 1 〇〇 to 300 nm, an etch stop film 25' composed of a SiC or SiN film and having a thickness of 10 to 100 nm, and an interlayer insulating film 26 having a thickness of 1 〇〇 to 3 〇〇 nm. Continued to be formed in the above-mentioned 17F Further, the interconnect trench 26T for exposing the etch stop film 25 is formed in the interlayer insulating film 26 by dry etching to have a desired width. The interlayer insulating films 24 and 26 are formed. The ruthenium oxide film which can be formed by the plasma CVD method, the electropolymerization CVD method uses the above TE〇s as an unprocessed material, or the above-mentioned interlayer insulating films 24 and 26 can be formed by a plasma CVD method or a coating method. An organic or inorganic insulating film having a relative dielectric constant of 3 or less. For example, 2 〇 even when an organic polymer film registered under the trademark SiLK is used as the above-mentioned interlayer insulating films 24 and 26 'because of etching or the like The damage, so these films contain a substantial amount of oxygen (moisture). As shown in the figure, 'the opening portion 25V corresponding to the predetermined through hole is formed; exposed to the money stopping film 25 of the above-mentioned interconnecting groove 26T. Further, as shown in the pi 30 200929496, the through hole 24v is formed in the interlayer insulating film 24 by using the above-described _stop film 25 as a hard f mask and in such a manner that the (four) stop film 23 can be exposed. 5 10 15 ❹ 20 as m As shown, the upper stop film 23 at the bottom of the through hole 24V is removed to expose the Cu interconnection pattern 22 (: Thereafter, as shown in FIG. 17K, the interlayer insulating film 26 contains Ta or Further, the barrier metal film 26B having a shape conforming to the cross-sectional shape of the interconnection trench 26T and the via hole 24V described above is formed by a sputtering method or an ALD method such that it can continuously cover the sidewall surface and the bottom surface of the interconnection trench 26T. And the side wall surface and the bottom surface of the through hole 24v and having a film thickness of about 1 to 15 nm. The barrier metal film 26B is not limited to a metal film, and the barrier metal film 26B may be TaN, TiN or the like, except for a metal film containing at least one metal element selected from the group consisting of Ta, Ti Zr and Ru. Conductive metal nitride film. A Cu-Mn alloy layer 26 having a shape conforming to the cross-sectional shape of the interconnecting trench 26T and the via hole 24V as shown in FIG. 17L is formed on the structure shown in the above-mentioned 17th drawing by a sputtering method to cover the above barrier metal film. 26 Å and has a film thickness of about 1 to 15 nm. As shown in Fig. 17M, a Cu layer 26C1 having a shape conforming to the cross-sectional shape of the interconnecting trench 26T and the via hole 24V is formed on the structure shown in the above-mentioned 17L to cover the Cu-Mn alloy by a sputtering method or a CVD method. Layer 26M has a film thickness of 25 to 65 nm. As shown in Fig. 17N, the Cu layer 26C2 is formed by the electroplating method on the structure shown in Fig. 17M to fill the interconnection trench 26T and the via hole 24V. The plating method uses the Cu layer 26C1 as the electroplated seed layer. 31 200929496 As shown in Fig. 170, the Cu layers 26C1 and 26C2, the Cu-Mn alloy layer, and the barrier metal film 26B on the interlayer insulating film 26 are polished and removed by CMP until the surface of the interlayer insulating film 26 is exposed. As shown in Fig. 17P, the cap layer containing the SiN film or the SiC film is typically at a substrate temperature of 4 Å. The plasma CVD method carried out at 5 C is formed on the structure shown in Fig. 170 described above. In the interconnect trench 26T and the via hole 24V, the Cu layers 26C1 and 26C2 are thermally fused with the cap layer 27, and are formed as a single Cu interconnect pattern 26C or a Cu via pillar continuously extending therefrom. Plug 26V. Further, by the heat generated by the formation of the cap layer 27 described above, the Μη atoms in the Cu-Mn alloy layer 26M are transferred to the barrier metal film 26B, and are stably deposited in the form of Μ η oxide. The oxygen of the η η oxide is derived from the interlayer insulating films 24 and 26 and the etch stop films 23 and 25, and the etch stop films 23 and 25 are located in the barrier metal film 26 , or in the barrier 15 metal film 26 Β At the interface between the Cu interconnection pattern 26C or the Cu via plug 26V or the interface between the barrier metal film 26B and the interlayer insulating film 24 or 26, or the above barrier metal film 26B and the etching stop film 23 or At the boundary between the 25th. In the case where a defect occurs in the above-mentioned barrier metal film 26B, such a defect 20 can be self-removed by the deposited ?n oxide. As the Μn atoms in the above-described Cu-Mn alloy layer 26Μ are transferred to the above barrier metal film 26Β, the Μn oxide layer 260 对应 corresponding to the oxide layer is formed on the surface corresponding to the original Cu-Mn metal alloy layer 26Μ. Position, and spaced apart from the surface of the barrier metal film 26B by a distance corresponding to the film thickness of the original Cu-Mn alloy layer 26M, wherein the oxide layer is formed as shown in the above 17th L The surface of the Cu-Mn alloy layer 26M is in the step. Therefore, as shown in FIG. 17P, the Cu interconnection pattern 26C includes the Cu layer formed in the region 26cl and the Cu layer formed in the region 26c2, wherein the original Cu-Mn alloy layer 26M exists in the region 26cl, and the region 26c2 There are original ones (: 11 layers 26C1 and 26C2. In the present invention, the above steps are repeated on a semiconductor substrate (for example, a tantalum substrate) provided with a transistor and a tungsten plug, whereby an image as shown in Fig. 18 can be produced. The semiconductor device 40 is shown. As shown in Fig. 18, on the stone substrate 41, the element region 41A is secured by the element isolation structure 411. The gate electrodes 43A, 43B, and 43C are provided on the above-described ruthenium base. The material 41 has a gate insulating film 42A, 42B and 42 interposed therebetween and the element region 41A. In the above-mentioned element region 41A, the p-type or n-type diffusion The regions 41a, 41b, and 41c are provided in the vicinity of the gate electrodes 43A, 43A, and 43C. The gate electrodes 43A, 43B, and 43C are each covered with insulating films 44A, 44B, and 44C composed of SiON or the like. An insulating film 44 composed of a tantalum oxide film or the like to cover The gate electrodes 43A to 43C are provided on the above-described ruthenium substrate 41, and each has the above-described insulating films 44A to 44C interposed therebetween, a through hole 44VI exposing the diffusion region 41B, and a through hole 44V2 exposing the diffusion region 41c. The sidewalls and the bottom surface of the through holes 44V1 and 44V2 are continuously covered by the barrier metal films 46B1 and 46B2 composed of, for example, TiN, and the through holes 44V1 33 200929496 and 44V2 are each tungsten. 46V1 and 46V2 are filled. An interlayer insulating film 46 composed of an inorganic or organic insulating film and including a porous film is provided on the above insulating film 44, and an etch stop film 45 composed of siN or sic is interposed therebetween. The interconnecting trenches 46T1 and 46T2 5 are disposed along a predetermined interconnect pattern. The sidewall surface and the bottom surface of the interconnect trench 46T1 are continuously covered by the barrier metal film 46B1, and the barrier metal film 46bi includes at least one high-refining metal. An element such as Ta, Ti, Zr or RU. The above-described interconnection trench 46T1 is filled with the CU interconnection pattern 46C1 and has the above-mentioned barrier metal 臈 46m interposed therebetween. ❿ ° Similarly, the side of the above-mentioned interconnection trench 46T2 The surface and the bottom surface are continuously covered with a barrier metal film 46B2 containing at least one high melting point metal element such as Ta, Ti, & or Ru. The above interconnecting trench 46T2 is filled with the Cu interconnect pattern 46C2, and The barrier metal film 46Β2 is interposed therebetween. 5 The interlayer insulating film 48 composed of an inorganic or organic insulating film and including a porous film is smattered on the above-mentioned insulating film 46, and an etching stopper film 47 composed of SiN or Sic is interposed therebetween. . An interlayer insulating film 50 composed of an inorganic or organic insulating film and including a porous film is provided on the above insulating film 48, and an etching stopper film 49 composed of SiN or SiC is interposed therebetween. In the above-mentioned interlayer insulating film 5, the interconnection grooves 5, T1, 5, 2, and 5 are disposed along a predetermined interconnection pattern. Further, in the above-mentioned insulating film 48, the via hole 48V1 for exposing the above-described Cu interconnection pattern 46C1 corresponds to the above-described interconnection trench 50TU while passing through the above-described etching stopper film 49. The through hole 48V2 for exposing the above-described Cu interconnection pattern 46C1 in the above-mentioned insulating film 48 is disposed corresponding to the above-mentioned mutual interface 30 200929496, while passing through the above-described etching stopper film 49. Further, in the above insulating film 48, a via hole 48v3 for exposing the above-described Cu interconnection pattern 46C2 is disposed corresponding to the above-described interconnection trench 50T3 while passing through the above-described etching stopper film 49. 5 Ο 10 15 ❹ 20 The side wall surface and the bottom surface of the interconnecting trench 50T1 and the via hole 48V1 are continuously covered by the barrier metal film 50B1, and the barrier metal film 5〇Β1 contains at least one melting point metal element such as Ta, Ti, Zr Or Ru. The interconnect trenches 5? and the vias 48V1 are filled with the Cu interconnect pattern 50C1, and the CU via plug 50V1 is continuously extended from the Cu interconnect pattern 50C1 with the barrier metal film 50B1 interposed therebetween. Similarly, the sidewall surfaces and the bottom surface of the interconnecting trench 50T2 and the via hole 48V2 are continuously covered by the barrier metal film 50B2 containing at least one high melting point metal element such as Ta, Ti, 21* or . The interconnecting trench 50T2 and the via hole 48V2 are filled with the Cu interconnect pattern 50C2, and the Cu via plug 50V2 is continuously extended from the Cu interconnect pattern 50C2 with the barrier metal film 50B2 interposed therebetween. Similarly, the side wall surface and the bottom surface of the interconnecting trench 50T3 and the via hole 48V3 are continuously covered by the barrier metal film 50B3 containing at least one high melting point metal element such as Ta, Ti, Zr or Ru. The interconnecting trench 50T3 and the via hole 48V3 are filled with the Cu interconnect pattern 50C3, and the Cu via plug 50V3 is continuously extended from the Cu interconnect pattern 50C3 with the barrier metal film 50B3 interposed therebetween. A cool insulating film 52 composed of an inorganic or organic insulating film and including a porous film is provided on the above insulating film 50, and an etch stop film 51 composed of SiN or SiC is interposed therebetween. A clip composed of an inorganic or organic insulating film and including a porous film 35 200929496 A layer insulating film 54 is provided on the above insulating film 52 with an etch stop film 53 composed of SiN or SiC interposed therebetween. In the above interlayer insulating film 54, the interconnection grooves 54T1 and 54T2 are disposed along a predetermined interconnection pattern. Further, in the above-described insulating film 52, a via hole 52V1 for exposing the above-described Cu interconnection pattern 50C2 is provided corresponding to the above-described interconnection groove 54T1 while passing through the above-described etching stopper film 53. In the above-mentioned insulating film 52, a via hole 52V2 for exposing the above-described Cu interconnection pattern 50C3 is provided corresponding to the above-described interconnection groove 54T2 while passing through the above-described last stop film μ. The side wall surface and the bottom surface of the interconnecting groove 54T1 and the through hole 52V1 are continuously covered by the ©10 barrier metal film 54B1, and the barrier metal film 54 contains at least a metal element of the south refining point, such as Ta, Ti, Zr or Ru. The interconnect trench 54T1 and the via 52V1 are filled with the Cu interconnect pattern 54C1, and the Cu via plug 54V1 is continuously extended from the Cu interconnect pattern 54C1 with the barrier metal film 54B1 interposed therebetween. Similarly, the side wall surface and the bottom surface of the interconnecting groove 54T2 and the through hole 52V2 are continuously covered by the barrier metal film 54B2 containing at least one high melting point metal element such as Ta, Ti, Zl^Ru. The inter-connecting trench 54T2 and the via 52V2 are filled with the Cu interconnect pattern 54C2, and the Cu via plug 54V2 is continuously extended from the Cu interconnect pattern 54C2 with the barrier metal 20 film 54B2 interposed therebetween. An interlayer insulating film 56 composed of an inorganic or organic insulating film and including a porous film is provided on the above insulating film 54, and a residual stop film 55 composed of SiN or SiC is interposed therebetween. An interlayer insulating film 58 composed of an inorganic or organic insulating film and including a porous film is provided on the above insulating film 56, and an etch 36 consisting of siN or Sic stops the film 57 interposed therebetween. In the above interlayer insulating film 58, the interconnection grooves 58T1 & 58T2 are disposed along a predetermined interconnection pattern. Further, in the insulating film 56, the via hole 56V1 for exposing the Cu interconnection pattern 54C1 is disposed corresponding to the interconnection trench while passing through the etching stopper film 57. In the above insulating film 56, a via hole 56V2 for exposing the above-described Cu interconnection pattern 54C1 is provided corresponding to the above-described interconnection groove 58T2 while passing through the above-described etching stopper film 57. Similarly, in the above-mentioned insulating film 56, a via hole 56¥3 for exposing the above-described Cu interconnection pattern 54 (: 2 is provided corresponding to the above-described interconnection trench 58T3 while passing through the above-described etching stopper film 57. 10 The side wall surface and the bottom surface of the 58T1 and the through hole 56V1 are continuously covered by the barrier metal film 58Β1, and the barrier metal film 58 contains at least a metal element such as Ta, Ti, Zr or Ru. The interconnection groove 58Τ1 and the pass The hole 56V1 is filled with the Cu interconnection pattern 58C1, and continuously extends from the Cu interconnection pattern 58C1 with the via plug 58V1, and the above barrier metal film 15 58B1 is interposed therebetween. Similarly, the above-described interconnection trench 58T2 and via 56V2 The sidewall surface and the bottom surface are continuously covered by the barrier metal film 58B2 containing at least one of two melting point metal elements such as Ta, Ti, Zr or Ru. The interconnecting trench 58T2 and the via 56V2 are inter-Cu The pattern 58C2 and the Cu interlayer plug 20 58V2 are filled, and the barrier metal film 58B2 is interposed therebetween. Similarly, the sidewall surfaces and the bottom surface of the interconnection trench 58T3 and the via hole 56V3 are continuously covered by the barrier metal film 58B3. The barrier metal film 58B3 There is at least one high melting point metal element such as Ta, Ti, Zr or Ru. The interconnecting trench 58T3 and the via 56V3 are filled with a Cu interconnect pattern 58C3 and a Cu via plug 58V3, and the upper barrier metal film 58B3 is described in the above 37 200929496 Further, an interlayer insulating surface composed of an inorganic or organic insulating film and including a porous film is provided on the above-described interlayer insulating film 58, and an etch stop film 59 composed of _ or as is interposed therebetween. The inflammatory layer 5 insulating film 62 composed of a similar substance is provided on the above-mentioned moxibustion layer insulating film 6 ,, and the etched film 61 composed of _ or si (: is interposed therebetween. In the above other interlayer insulating film 62, The interconnecting trenches 62T are disposed along a predetermined interconnect pattern. Further, in the interlayer insulating film 6A, the via holes 60V for exposing the Cu interconnect patterns 58C3 are disposed corresponding to the interconnecting trenches 62T, and are worn at the same time. The etch stop film 59 is formed. The sidewall surfaces and the bottom surface of the interconnect trench 62T and the via 60V are continuously covered by a barrier metal film 62B containing at least one high melting point metal element such as Ta, Ti, Zr. Or Ru. The above interconnecting trench 62T and via 60V are The interconnect pattern 62C composed of A1 or Cu is filled, and the via plug 62V composed of Cu or 15 A1 continuously extends from the interconnect pattern 62C, and the above barrier metal film 62B is interposed therebetween. In the CVD method or the like, a cover film 63 composed of SiN or the like is formed on the other interlayer insulating film 62 so as to cover the interconnection pattern 62C. 20 Regarding the semiconductor device 40 shown in Fig. 18, In the Cu interconnection patterns 46C, 46C2, 50C1 to 50C3, 54C1, 54C2, 58C1 to 58C3 and the like, a Cu-Mn alloy layer corresponding to the above-described Cu-Mn alloy layer 22M or 26M is formed in the vicinity of the respective barrier metal film, It is made such that the film thickness and/or concentration of substantially all of the Mn atoms in the Cu-Mn alloy layer can be transferred to the adjacent barrier metal film of 200929496 described above. As a result, a cross-sectional structure having characteristics is obtained in which substantially all of the above-described Mn atoms are transferred to the above adjacent barrier metal film to form the above-described cap film 63, and the tantalum oxide thin layers 460x1, 460x2, 500x1 to 500x3, 540 540 540x2 and 5 ❹ 10 15 20 580x1 to 580x3 only exist on the portion corresponding to the surface of the original Cu-Mn alloy layer, as indicated by the broken line in Fig. 18. With respect to the semiconductor device 4 having the above-described multilayer interconnection structure, as described with reference to Fig. 14, a Cu-Mn alloy layer having a high Μn concentration is provided, whereby the stress migration resistance is remarkably enhanced. In addition, the interconnection resistance increased by Μη can be suppressed. In the step shown in Fig. 17 of the present embodiment, the interconnection trench 26 and the via hole 24V may be filled by depositing a Cu layer one or several times, for example, by the MOCVD method. In this case, the interconnect trench 26 and the via 24V are filled with a Cu layer deposited by the MOCVD method, and the plating process shown in Fig. 17N can be omitted. In the above-described step of forming the Cu-Mn alloy layer 22M or 26M shown in Fig. 17B or 17L of the present embodiment, it is clear from the relationship shown in Fig. 10 that 'if the above-mentioned Cu-Mn alloy layer 22M or 26M The film thickness is specifically inM or more and 4·5 η Μ or less, and the Cu-Mn alloy film or the Μ 膜 film containing 〇 2 atomic percent to 100 atomic percent Μ η may be relative to the above Cu-Mn alloy layer 22M or 26M And was used. In this embodiment, more specifically, in the interconnection trench 22T shown in FIG. 17C

Cu film 22C1 and interconnection trench 26T and via hole 24V shown in FIG. 17M

The Cu layer 26C1 is formed by a sputtering method, and after the interconnection trenches 22T, the inter-transfers 29200929496, the trenches 26T, and the via holes 24V are filled by electroplating, heat treatment is performed below. Similarly, in the semiconductor device 4A shown in FIG. 18, when the Cu interconnection patterns 46C1, 46C2, 50C1 to 50C3, 54C1, 54C2, 5 58C1 to 58C3 and the like are formed, corresponding to the above Cl^ In the case where the Cu layer of the Cu layer 26C1 is formed by a sputtering method, the same heat treatment is performed 'and the 'Cu layer is filled by using an electroplating method. SECOND EMBODIMENT Figs. 19A to 19P show the steps of forming a multilayer interconnection structure by using a double damascene process by ❹ 10 in accordance with a second embodiment of the present invention. As shown in FIG. 19A, an interconnection trench 82 corresponding to a predetermined interconnection pattern is formed in the insulating film 82, and the insulating film 82 is provided with a transistor and a tungsten plug (the same is not shown in the drawing). On the semiconductor substrate 81. Further, on the insulating film 82, the barrier metal film 15 82 having a shape conforming to the cross-sectional shape of the interconnecting groove 82 is formed by a money bonding method, an atomic layer deposition (ALD) method or the like. The barrier metal film 82B containing at least one high-refining metal element such as Ta, Ti, Zr or Ru covers the side wall surface and the bottom surface of the above-mentioned interconnection groove 82T and has a film thickness of 1 to 15 nM. The barrier metal film mb is not limited to the metal film. The barrier metal film 82B may be TaN, in addition to a metal film containing at least one metal element selected from the group consisting of Ta, Ti, Zr, and Ru.

A conductive metal nitride film of TiN or the like. The Cu-Mn alloy layer 82M containing θ having a shape conforming to the cross-sectional shape of the interconnecting groove 82T as shown in Fig. 19B is formed on the above-described barrier metal film 82B shown in Fig. 19A by a sputtering method. Wherein, for example, Cu-Mn alloy 40 200929496 is used as a target, in an Ar atmosphere of 10-1 Pa, and the substrate temperature is lower than or equal to room temperature, while inputting 10 kW of plasma power 'to have any thickness ( For example 30nM). In the step shown in FIG. 19B, in the case where the concentration of Μη in the formed Cu_Mn alloy layer 82m 5 is about 30 atom% or less (for example, between 原子2 atomic percent and 30 atomic percent), the above The film thickness of the Cu_Mn alloy layer 82M is adjusted by etching (for example, Ar ion etching) treatment so that the film thickness on the flat surface becomes about 15 n or less (for example, in the range of 〇 to © 15 nM). In the case where the concentration of Μn in the Cu-Mn alloy layer 82M exceeds 30 atomic percent, the film thickness of the Cu-Mn alloy layer 82A is adjusted by the same etching treatment so that the film thickness on the flat surface becomes smaller. Or equal to the film thickness y obtained by the equation y = 465/x, which again represents the concentration of Μη atoms in the above Cu_Mn alloy layer 82M. 15, as shown in FIG. 19C, the Cu film 82C1 having a shape conforming to the cross-sectional shape of the interconnecting trench 82 is formed as an electroplated seed layer by a sputtering method or a CVD method, for example, to have a plating layer of about 4 〇 to 8〇11]^ film thickness. As shown in Fig. 19D, by using the above-mentioned (:11 film 82C1 as the electroplating species 20 layers, €11 film 82 €2 to fill the above-described interconnecting grooves 82τ, the structure shown in the above-mentioned 19C is formed. As shown in Fig. 19, the structure shown in the above i9D is polished by the CMP method until the surface of the above-mentioned insulating film 82 is exposed. Thus, a structure is obtained in which the above-mentioned interconnecting groove 82τ is filled with the CuS connecting pattern 82c. 41 200929496 As shown in Fig. 19F, an etch stop film 83 composed of SiN or SiC is formed on the structure shown in Fig. 19E so as to cover the above-described Cu interconnection pattern 82C and has a film thickness of 10 to ΙΟΟηΜ. The film formation of the film 83 is typically carried out at a temperature of 400 ° C. Therefore, the Cu film 82C1 and the Cu film 82C2 constituting the Cu interconnection 5 pattern 82C are fused and formed into a single Cu film. The Μη atoms in the Cu-Mn alloy layer 82M are transferred into the barrier metal film 82B. As a result, in the Cu interconnection pattern 82C described above, the original Cu-Mn alloy layer 82 Μ disappears. However, the Μ 氧化物 oxide thin layer Formed in the corresponding original Cu-Mn The position of the surface of the surface of the layer 82M is the distance from the surface of the barrier metal film 82B at a distance corresponding to the film thickness of the original Cu-Mn alloy layer 82M, as shown by the broken line 820x shown in Fig. 19F. The continuous pattern 82C is formed by a region 82cl and a region 82c2 in which the original Cu-Mn alloy layer 82M is present in the region 82cl, and the original Cu films 82C1 and 82C2 are present in the region 82c2. I5 has a thickness of 1 as shown in Fig. 19G. The interlayer insulating film 84 of 〇〇n to 3〇〇nM is composed of an etch stop film 85 having a thickness of 1 Å to 〇〇 Μ 及 and an interlayer insulating film 86 having a thickness of 1 Å to 〇 η 由 by a SiC or SiN film by, for example, electricity The polyCVD method is successively formed on the structure shown in the above-mentioned 19F. Further, the interconnection trench 86T for exposing the etching stopper film 85 is formed in the interlayer insulating film 86 by a dry etching process to have a desired effect. The interlayer insulating films 84 and 86 may be tantalum oxide films formed by a plasma CVD method by using the above TEOS as an unprocessed material, or may be formed by a plasma CVD* method or a coating method. Organic with a dielectric constant of 3 or less Or an inorganic insulating film. For example, even when the organic polymer film 200929496 registered under the trademark SiLK is used as the above-mentioned interlayer insulating films 84 and 86, these films still contain a substantial amount of oxygen because of damage from etching or the like ( Moisture) 5 ❹ 10 15 ❿ 20 As shown in Fig. 19H, an opening portion 85V corresponding to a predetermined through hole is formed in the etching stopper film 85 exposed to the above-described interconnecting groove 86T. Further, as shown in Fig. 191, a through hole 84V is formed in the above-described interlayer insulating film 84 by using the above-described etching stopper film 85 as a hard mask to expose the above-described pattern of the stop film 83. As shown in Fig. 19J, the above-described etching stopper film 83 at the bottom of the above-mentioned via hole 84v is removed to expose the Cu interconnection pattern 82C. Thereafter, as shown in FIG. 19κ, on the interlayer insulating film 86, the barrier metal film 86B composed of Ta*Ti and having a shape conforming to the cross-sectional shape of the interconnection trench 86T and the via hole 84V is by a sputtering method or an ALD method. A method of continuously covering the side wall surface and the bottom surface of the interconnecting groove 86T and the side wall surface and the bottom surface of the through hole 24V is formed, and has a film thickness of 1 to 15 nM. The barrier metal film 86B is not limited to the metal film 'except for the metal film containing at least one metal element selected from the group consisting of Ta, Ti, Zr, and Ru. The barrier metal film 86B may be TaN, TiN, or the like. A conductive metal nitride film of matter. As shown in FIG. 19L, a Cu-Mn alloy layer 86 having a shape conforming to the cross-sectional shape of the interconnection trench 86τ and the via hole 84v is formed on the structure shown in FIG. 19K by a sputtering method to cover the barrier metal film. 86B and has a crucible thickness of 1 to 15 nM. As shown in FIG. 19M, a Cu layer 86C1 having a shape conforming to the cross-sectional shape of the interconnect trench 86T and the via hole 84V is formed on the structure shown in FIG. 19L by a sputtering method or a CVD method to cover the above cu_Mn alloy. Layer 43 200929496 86M, and has a film thickness of 25 to 65 nm. As shown in Fig. 19N, the Cu layer 86C2 is formed on the structure shown in Fig. 19M by an electroplating method using the Cu layer 86C1 as an electroplated seed layer to fill the interconnection trench 86T and the via hole 84V. As shown in Fig. 190, the Cu layers 86C1 and 86C2, the Cu-Mn alloy layer 86M, and the barrier metal film 86B on the interlayer insulating film 86 are polished and removed by CMP until the surface of the interlayer insulating film 86 is exposed. As shown in Fig. 19P, a cap layer composed of a SiN film or a SiC film is formed on the structure shown in Fig. 190 by a plasma CVD method which is typically carried out at a substrate temperature of 400 °C. In the interconnect trench 86T and the via hole 84V, the Cu layer 86C1 and the Cu layer 86C2 are fused with the heat generated by the cap layer 87 formation and formed as a single Cu interconnect pattern 86C or continuously extended therefrom. Cu interlayer plunger 86V. Further, by the heat generated by the formation of the cap layer 87, the ?n atoms in the Cu-Mn alloy layer 86M are transferred to the barrier metal film 86B. The 15 atom to be transferred is stably deposited in the form of Μ η oxide, wherein the oxygen of the Μ η oxide is derived from the interlayer insulating films 84 and 86 and the etch stop films 83 and 85 in the barrier metal film 86 ,, or is located above The interface between the barrier metal film 86Β and the Cu interconnection pattern 86C or the Cu interlayer plug 86V, or the interface between the barrier metal film 86B and the interlayer insulating film 84 or 86, or the above-described 20 barrier metal film 86B At the interface with the etch stop film 83 or 85. In the case where the defect occurs in the above-mentioned barrier metal film 868, such a defect self-recovers by the deposited Μη oxide. As the Μn atoms in the Cu-Mn alloy layer 86Μ are transferred to the barrier metal film 86Β, as described above, the Μη oxide 44 200929496 layer 860x corresponding to the oxide layer is formed in the layer corresponding to the original Cu-Mn metal alloy layer. The position of the surface of 86M is further separated from the surface of the barrier metal film 86B by a distance corresponding to the film thickness of the original Cu-Mn alloy layer 86M formed in the above-mentioned Cu- in the step shown in the above-mentioned 19L. On the surface 5 of the Mn alloy layer 86M. Therefore, as shown in FIG. 19P, the Cu interconnection pattern 86C is composed of a Cu layer formed in the region 86cl and a Cu layer formed in the region 86c2, wherein the original Cu-Mn alloy layer 86M appears in the region 86cl, The original cu layers 86C1 and 86C2 appear in the area 86c2. In the present embodiment, the above steps are repeated on the semiconductor substrate 10 (e.g., Shishi substrate) in which the transistor and the tungsten plug are provided, and thereby, the semiconductor device 40 shown in Fig. 18 can be produced. In the step shown in Fig. 19M of the above embodiment, the interconnection trench 86T and the via hole 84V may be filled by, for example, depositing a Cu layer one or several times by the MOCVD method. In this case, the interconnection trench 86T and the via hole 84V may be filled with a Cu layer deposited by the M CVD method, and the plating step shown in Fig. 19N may be omitted. In the above-described step of forming the Cu-Mn alloy layer 82M or 86M shown in the 19B or 19L of the present embodiment, it is clear from the relationship shown in the above first drawing that the above Cu-Mn alloy layer 82M or The film thickness of 86M is specifically lnM or more 20 and 4·5 η Μ or less, and the Cu-Mn alloy film or the Μη film containing Μη concentration of 0.2 atom% to 100 atom% may be relative to the above-mentioned Cu-Mn alloy layer 82 or 86Μ was used. In the present embodiment, the etching step shown in Fig. 19B may be performed until the barrier metal film 82B is exposed to the bottom of the interconnection trench 82T as shown in Fig. 2a 2009 2009496. In this case, the Cu-Mn alloy layer 82M is removed from the bottom of the interconnecting groove 82T. In the case where the concentration of Μη in the film is 0.2 atom% or more and 30 atom% or less, the Cu-Mn 5 alloy layer 82M having the film thickness of 1 to 15 η above is formed only on the side wall surface of the interconnection groove 82T. In the case where the Μη concentration in the Cu-Mn alloy layer 82M exceeds 30 atomic percent, the Cu-Mn alloy layer 82 is formed such that the film thickness on the side wall surface becomes less than or equal to the relationship shown in the above FIG. 10B. The specific film thickness, for example, the film thickness is in the range of InM or more and 4·5ηΜ or less. As a result, in the case of performing the heat treatment shown in FIG. 19F, the tantalum oxide layer 820 showing the presence of the original Cu-Mn alloy layer 82 is formed along the above-described interconnecting groove 82, which corresponds to the above Cu- The distance of the film thickness of the Mn alloy layer 82 is spaced apart from the above barrier metal film 82B as shown in Fig. 20B. The invention also includes such a structure. Further, in the present embodiment, in the interconnection groove 82T shown in FIG. 19C

The Cu seed film 82C1 and the interconnecting groove 86T shown in FIG. 19M and the Cu layer 86C1 of the through hole 84V are formed by a sputtering method. Further, in the case where the interconnection trench 82T, the interconnection trench 86T, and the via hole 84V are filled by the plating method, heat treatment is performed at 8 ° C to 120 ° C after the plating. 20 By now, the preferred embodiment of the invention has been described. However, the invention is not limited to these specific embodiments. Various modifications and changes are intended to be included within the scope of the invention as described in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A shows a shadow of a Cu_Mn alloy layer in a known barrier metal structure. 200929496 FIG. 1B shows the structure of a test piece used in the present invention; FIG. 1C shows a copper interconnection immediately after plating; 1D is a diagram for explaining a phenomenon in the case of performing a known heat treatment immediately after electroplating; FIG. 2 is a diagram for explaining the principle of the present invention; and FIG. 3 is another diagram for explaining the principle of the present invention. Figure 4 is another diagram for explaining the principles of the present invention; © Figures 5A and 5B are diagrams for explaining other principles of the present invention; 10 Figure 6 is another diagram for explaining the principle of the present invention; Figure 7 is another diagram for explaining the principle of the present invention; Figure 8 is another diagram for explaining the principle of the present invention; 'Fig. 9 is a phase equilibrium diagram of the Cu-Mn system; 10A is another diagram for explaining the principles of the present invention; 15 Figure 10B is another diagram for explaining the principle of the present invention; Figure 11 is another diagram for explaining the principle of the present invention; Figure 12 is a diagram for explaining another principle of the present invention; Figure 13A is for explaining the original of the present invention Figure 13B is another diagram for explaining the principle of the present invention; 20 Figure 14 is a diagram for explaining the influence of the present invention; Figure 15 is another diagram for explaining the influence of the present invention. Figure 16 is another diagram for explaining the influence of the present invention; 17A to 17P are diagrams showing the steps of producing a semiconductor device according to the first embodiment of the present invention; 47 200929496 Figure 18 shows the first embodiment according to the first embodiment The configuration of the semiconductor device; FIGS. 19A to 19P show the steps of producing the semiconductor device according to the second embodiment of the present invention; and FIGS. 20A to 20B show the modified example of the second embodiment of the present invention. 5 [Description of main component symbols] 11...level 16C2...region 12...film 16M...alloy layer 12B...barrier metal film 160x...oxide thin layer 12C...interconnection pattern 16T...interconnect trench 12 ( :1...〇1 film/area 16V···Interlayer plunger 12C2··region 21...semiconductor new 120x...oxide thin layer 22...insulating film 12M...alloy layer 22B...barrier metal film 12T.. Interconnecting groove 22C.. Interconnection pattern 13...Carbide film 22C1...Cu film 14...Low-k film 22C2·. Cu film 14V". Through hole 22M... Alloy layer 15...Carbide film 220x...Dash line 16... Her film 22T··interconnecting groove 16B...barrier metal film 23...etching stop film 16C..interconnect pattern 24...interlayer insulating film 16C1...CU film/area 24V···layer plunger

48 200929496

25.. Etch stop film 25V" via plunger 26... interlayer insulating film 26B... barrier metal film 26C.. interconnection pattern 26C1...Cu layer 26CZ·. Cu layer 26M··· alloy layer 260x... oxidation Thin layer 26T..·interconnecting groove 26V" via plunger 27... cap layer 40.. semiconductor device 41... semiconductor substrate 41A... element region 41a... diffusion region 41b... diffusion region 41c· Diffusion region 411.. element separation structure 42... gate insulating film 42A... gate insulating film 42B... gate insulating film 42C... interconnect pattern 43A... gate electrode 43B... gate electrode 43C. .. gate electrode 44: insulating film 44A: insulating film 44B: insulating film 44C: insulating film 44V1 ... through hole 44V2 ... through hole 45 ... etching stop film 46 ... cool insulating film 46B1 ... barrier metal film 46B2. Barrier Metal Film 46C1... Interconnect Pattern 46C2... Interconnect Pattern 460x1... Oxide Thin Layer 460x2... Oxide Thin Layer 46T1... Interconnecting Slot 46T2... Interconnecting Slot 49 200929496 46V1...Tungsten 46V2···Tungsten 47.. Etch stop film 48... interlayer insulating film 48VL·. via hole 48V2·.·through hole 48V3...through hole 49.. etching stop film 50... interlayer insulating film 50B1... barrier The film 50B2...the barrier metal film 50B3...the barrier metal film 50C1...the interconnection pattern 50C2...the interconnection pattern 50C3...the interconnection pattern 500x1...the oxide thin layer 500x2...the oxide thin layer 500x3... Thin oxide layer 50T1...interconnecting groove 50T1·.interconnecting groove 50T3...interconnecting groove 50V1...interlayer plunger 50V2...interlayer plunger 50V3...interlayer plunger 51...etch stop film 52...interlayer insulating film 52V1... · Through hole 52V2... Through hole 53.. Last name stop film 54B1... Barrier metal film 54B2... Barrier metal film 54C1... Interconnection pattern 54C2... Interconnection pattern 54 0x1... Oxide thin layer 54 0x2... Oxidation Thin layer 54T1...interconnecting groove 54T2...interconnecting groove 54V1...interlayer plunger 54V2...interlayer plunger 55..etch stop film 56...interlayer insulating film 56VL··through hole

50 200929496

56V2...through hole 56V3...through hole 57.. money stop film 58... interlayer insulating film 58B1... barrier metal film 58B2... barrier metal film 58B3... barrier metal film 58C1... interconnection pattern 58C2... interconnection pattern 58C3...interconnect pattern 580x1...oxide thin layer 580x2...oxide thin layer 580x3...oxide thin layer 58Ή...interconnect trench 58T1·interconnect trench 58T3...interconnect trench 58V1...interlayer plunger 58V2...via pillar Plug 58V3...interlayer plunger 59..etch stop film 60...interlayer insulating film 60V··interlayer plunger 61...etch stop film 62..etch stop film 62B...obstacle metal film 62C...interconnect pattern 62T ...interconnecting groove 62V".layer plunger 63.. cover film 81...semiconductor substrate 82...insulation film 82B...barrier metal film 82C..interconnection pattern 82C1...Cu film 82C2...Cu film 82M...alloy Layer 820x...Oxide thin layer 82T.·Interconnecting groove 83.. Etch stop film 84... Interlayer insulating film 84V·.. Through hole 85.. Etch stop film 51 200929496 85V... Opening portion 86C2.. .CU layer 86... interlayer insulating film 86M... alloy layer 86B... barrier metal film 86T... interconnecting groove 86C... interconnect pattern 86V··· via layer minus 86C1...Cu layer 8 7...cover layer ❹ 52

Claims (1)

200929496 X. Patent application scope: 1. A semiconductor device comprising: a semiconductor substrate; an oxygen-containing insulating film disposed over the semiconductor substrate; 5 a concave portion formed in the insulating film; a first copper-containing film over the inner wall of the concave portion; a copper-containing second film formed on the first film and filling the concave portion; and a first film formed between the first film and the second film A manganese-containing oxide layer. 2. The semiconductor device of claim 1, further comprising a diffusion preventing film for preventing diffusion of copper 10 between the insulating film and the first film. 3. The semiconductor device of claim 2, wherein the diffusion preventing film comprises at least one element selected from the group consisting of Ta, Ti, Zr, and Ru. 4. The semiconductor device of claim 2, wherein the diffusion preventing film comprises manganese. 5. The semiconductor device of claim 1, wherein the first film has a ruthenium film thickness ranging from 1 nm to 15 nm. 6. A method of fabricating a semiconductor device, the method comprising: forming a transistor having at least one gate 20 electrode and a source and drain region on a semiconductor substrate; forming over the semiconductor substrate An oxygen-containing insulating film; forming a concave portion in the insulating film; forming a metal film containing copper and manganese and having a predetermined film thickness on an inner wall of the concave portion; 53 200929496 forming a metal film on the metal film a copper-containing film filling the concave portion; and after the copper-containing film is formed, performing heat treatment. 7. The method of manufacturing a semiconductor device according to claim 6, further comprising forming a diffusion preventing film to prevent copper from diffusing between the insulating film and the metal film. 8. The method of producing a semiconductor device according to claim 6, wherein the metal film has a concentration of Μn of 0.2 atom% to 30 atom% and a film thickness of from 1 nm to 15 nm. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the metal film has a concentration of Μn of 0.2 atom% to 100 atom% and a film thickness of 1 nm to 4.5 nm. 10. The method of manufacturing a semiconductor device according to claim 6, wherein the diffusion preventing film is a high melting point metal film containing a group selected from the group consisting of Ta, Ti, Zr, and Ru. At least one element. The method of manufacturing a semiconductor device according to claim 6, wherein the metal film has a concentration of Μn of 0.2 atom% to 30 atom% and a film thickness of 15 nm or less. 12. The method of manufacturing a semiconductor device according to claim 11, comprising the step of performing etching to achieve a predetermined film thickness of 20 degrees after the film formation of the metal film. 13. The method of manufacturing a semiconductor device according to claim 6, comprising the step of performing etching on the inner surface of the sidewall of the concave portion to give a predetermined film thickness after the film of the metal film is formed. 14. The method of fabricating a semiconductor device according to claim 6 of claim 5, further comprising forming a copper-containing seed film on the metal film. 15. The method of manufacturing a semiconductor device according to claim 6, wherein the metal film is formed by a sputtering method. 16. The method of manufacturing a semiconductor device according to claim 6, wherein the forming the copper-containing film to fill the concave portion comprises: forming a copper-containing film filling the concave portion by electroplating, and The copper-containing film is formed by the electroplating method and then subjected to a heat treatment at a temperature of 80 ° C to 120 ° C. 17. A method of fabricating a semiconductor device, the method comprising: forming a transistor having a gate electrode 10 and a source and drain region on a semiconductor substrate; forming a pattern over the semiconductor substrate An oxygen-containing insulating film; forming a concave portion in the insulating film; forming a metal film containing copper and manganese on an inner wall of the concave portion; forming a copper-containing film over the metal film, the copper-containing film The film is filled with the concave portion 15; and after the copper-containing film is formed, heat treatment is performed. Wherein the 浓度 concentration X in the metal film is in the range of 0 atomic percent < X < 30 atomic percent, the film thickness of the metal film is specified to be 15 η Μ or less, and 20 In the case where the 浓度 concentration X is in the range of 30 atomic percent SX < 100 atomic percent, the film thickness is specified to be equal to or smaller than the film thickness y (nm) or less, wherein y is by equation y =465 (atomic percent.nm) / x given. 18. The method of manufacturing a semiconductor device according to claim 17, wherein the forming the copper-containing film to fill the concave portion in 55 200929496 comprises the step of forming a copper-containing film filling the concave portion by electroplating, and The step of performing heat treatment is performed at a temperature of 80 ° C to 120 Q C after the copper-containing film is formed by the plating method. 19. The method of manufacturing a semiconductor device according to claim 17, wherein the heat treatment is performed for 5 to 250 seconds. 56