SU571891A1 - Delay circuit - Google Patents

Description

(54) DELAY DEVICE

-. one

The invention relates to radio engineering, can be used in automation and computing.

A delay device is known that contains serially connected generators, the first blasting unit, a frequency divider, a second shaping unit and a differentiating circuit, a coincidence unit whose inputs are connected to the outputs of the shaping units, operating and controlling counters, between which the device is compared in comparison of codes; the counting input of the operating counter is connected to the output of the coincidence unit, and the inputs of the zero setting are connected to the output of the differentiating circuit tl.

However, this device has a relatively low latency.

The purpose of the invention is to improve the accuracy of the delay.

For this, in a delay device, comprising a generator connected in series, a first shaping unit, a Frequency divider, a second shaping unit and a differentiating circuit, a coincidence unit, the inputs of which are connected to the outputs

The operating and control counters between which the code comparison device is switched on, the counting input of the operating counter is connected to the output of the coincidence unit, and the inputs of the zero setup are connected to the output of the differentiating circuit, the interpolation counter, the code-voltage converter, third block form. nor, generator of shock excitation, intervals; connected to the output of the device comparing codes are connected in series the third unit of formation, the generator of shock excitation, the interval counter and the decoder, the output of which is

dinene with inputs of the third formation block and interval counter; the input of the control counter is connected to the output of the interpolation counter, the discharge output of which is connected to the control input of the shock excitation generator through a code-voltage converter.

The drawing shows a structural electrical circuit of the device.

The delay device contains connected

Claims (1)

sequentially generator 1; block odds - world unit 2, frequency divider 3, unit forming 4 and differentiating circuit 5. The match 6 inputs are connected to the outputs of the formation 2 and 4. Between the working and control counters 7 and 8, the code comparison device 9 is turned on. Count counter input 7 is connected to the output of the coincidence unit 6, and the inputs of the zero setting are connected to the output of the differentiating circuit 5. An interpolation counter 10, a third shaping unit 11, a code-voltage converter 12, a shock excitation generator 13, an interval counter 14 are inserted into the delay device. . Connected in series to the generator 11, the shock excitation generator 13, the interval counter 14, and the decoder 15, the output of which is connected to the inputs of the formation 11 and the interval counter 14, are connected to the output of the comparison device, Kodse 9,. Chica 10, the discharge output of which is connected via a converter voltage code 12 to the control input of the shock excitation generator 13. The delay device operates as follows. The harmonic oscillations of the quartz oscillator 1 are transmitted to the light formation 2, where they are converted into square pulses that go further to one of the inputs of the match 6 unit. This block: is open at its second input in the interval defined by frequency divider 3 and the shaping unit 4. The impulse signals from the coincidence block 6 are fed to the counting input of the working counter 7, which is pre-zeroed by the maximum edge of the maximum delay signal generated by the differentiating circuit 5. The delay increment pulses are applied to the even input of the interpolation counter 10 and further to the counting input of the control counter 8. At the time of the comparison of the codes of the counters 7 and 8, the comparison device of the codes 9 generates, together with the forming unit 11, a pulse starting shock excitation generator 1 Interval counter 14 together with the decoder 15 selects a delay pulse, after which, as a result of locking the airconnection unit 11, the interval counter 14 is turned on and the excitation generator 13 is turned off. The interpol code of the ion counter 10, converted into a control voltage reobrazovatelem code-voltage 12 controls the frequency for generators 13, whereby detention impulse smoothly moved in preelah discrete value dependent on the frequency present geeratora 1. Mathematically it can be shown that delays iskret offer ohms. device is more than the prototype. Here is the maximum number recorded in the interpolation counter 10. Formula of the invention A delay device comprising a generator connected in series, a first shaping unit, a frequency divider, a second shaping unit and a differentiating circuit, a coincidence block, whose inputs are connected to the outputs of the shaping units, operating and control counters, between which the code comparison device is switched on, wherein the counter input of the operating counter is connected to the output of the match output, and the inputs of the zero setting are connected to the output of the differential An enzyme circuit, characterized in that, in order to increase the accuracy of the delay, an interpolation counter, a voltage converter, a third generation unit, a shock excitation generator, an interval counter, are inserted into it, and a third unit connected in series is connected to the output of the code comparison device the generator, the shock excitation generator, the interval counter, and the descrambler, the output of which is connected to the inputs of the third generation unit and the interval counter, the input of the control counter is connected to the output An interpolation counter, whose discharge output through a code-voltage converter is connected to the control input of a shock excitation generator. Sources of information taken into account in the examination: 1. Vazhenina 3. P. and others. Methods and schemes for the time delay of pulse signals, M., 1971, p. 139.