SU1725148A2 - Device for measuring ratio of frequencies of pulse sequences - Google Patents

Abstract

The invention relates to a pulse technique and can be used to measure the frequency of following statistical sequences of pulses. The purpose of the invention is to expand the functionality of the device. A device for measuring the frequency ratio of a sequence of pulses. Contains input buses 1-5, reversible counters 6, 7, switches 12.13, OR elements 8.9, code-equalizing dividers 10.11 frequencies, triggers 14, 15. To achieve the goal The switch 17, the inverter block 18 and the input bus 19 are added to the device. 2 Il.

Description

VJ GO SL

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Yu

1

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nineteen

The invention relates to a pulse technique, can be used to measure the frequency of following statistical sequences of pulses, and is an improvement of the device according to the author. No. 1620935.

A device for measuring the ratio of two frequencies, containing two pulse counters, a strobe generator, the input of which is connected to the output of one of the pulse counters, and an indicator device are known.

In this device, both pre-zeroed pulse counters are filled with input signals. When the pulse counter connected to the strobe generator is filled, the indicator device displays the contents of another pulse counter, which corresponds to the frequency ratio of the input signals. After reading the result, the pulse counters are zeroed and the measurements are repeated.

A disadvantage of this device is the inability to continuously monitor changes in the frequency ratio until the end of the measurement period, which causes a slow response of the device.

A device for measuring the frequency ratio of pulse sequences is known, which contains two input buses, a reversible counter, and a code-controlled frequency divider whose counting input is connected to the first input bus, and the information inputs are bitwise connected to the information outputs of the reversible counter, the summing input of which is connected to the output of the code control frequency divider, and the subtracting input is connected to the second input bus.

The disadvantage of this device is the limitation of its functionality due to the implementation by the device of only one dependency, namely the ratio of the frequencies fi and f2: fi

TO

h

In practice, it is often necessary to use more complex dependencies.

The closest in technical essence to the present invention is a device for measuring the ratio of the frequencies of pulse sequences, containing the first - fifth input buses, the first and second reversible counters, the first and second elements OR, the first and second co-controlled frequency dividers, the first and second switches, the first and second triggers, with the first input bus connected

with the counting input of the first code-controlled frequency divider, whose information input is connected to the output of the first switch, the first and second information inputs of which are connected respectively to the third and fourth input buses, the control input of the first switch is connected to the output of the first trigger, whose input is connected to the release of the first

0 code-controlled frequency divider and subtractive input of the second reversible counter, the direct transfer output is connected to the first input of the second OR element and the summing input of the first reversible counter, the direct and reverse transfer outputs of which are connected respectively to the first and second inputs of the first element OR, output which is connected to the synchronization input of the record of the first reversible counter, whose information input is connected to the information output of the first reversible counter, the subtractive input of which is It is connected with the output of reverse transfer of the second reversing counter and the second input of the second OR element, the output of which is connected to the synchronization input of the second reversible counter, whose information input is connected with the information

0 by the output of the second reversible counter, the summing input of which is connected to the output of the second code-controlled frequency divider, the counting input of which is connected to the second input bus, the information

5 the input of the second code-controlled frequency splitter is connected to the output of the second switch, the first information input of which is connected to the fifth input bus, the second information input of the second switch is connected to the information output of the first reversible counter and the output of the device, the second trigger is connected to the output of the second frequency splitter and the output of the second trigger is with the input

5 controls the second switch.

A disadvantage of the known device is the limitation of its functionality due to the implementation by the device of only one type of dependency, namely:

Y Ј. (D + B) -C,

where fi, h are input frequencies;

A, B, C are numbers describing the scale and range of the measured frequency ratio.

In practice, it is often necessary to use other types of dependencies.

The aim of the invention is to extend the functionality of the device for measuring the ratio of the frequency of a sequence of pulses.

The goal is achieved by introducing a third switch, an inverter unit and a pole input bus into the pulse frequency ratio measurement device, the first information input of the third switch connected to the information output of the first reversible counter and the input of the inverter unit whose output is connected to the second information input the third switch, the control input of which is connected to the sixth input bus, and the output of the third switch is connected to the output bus of the device.

Fig. 1 shows a block diagram of an apparatus for measuring the frequency ratio of a sequence of pulses; Fig. 2 shows the dependences of the input code on the measured frequency ratio for the proposed and known devices.

The device for measuring the frequency ratio of the pulse sequences contains the first 1, second 2, third 3, fourth 4, fifth 5 and sixth 19 input buses, first 2 and second 7 reversing counters, first 8 and second 9 elements OR, first 10 and second 11 code controllers, the first 12, the second 13 and the third 17 switches, the first 14 and the second 15 triggers, the output bus 16 and the inverter unit 18, the first input bus 1 through the first frequency divider 10, the information input of which is connected to the output of the first switch 12 is connected to the subtractive m input of the second reversible counter 7, whose information input is connected to the information output of the second reversible counter 7, and the input of the first trigger 14, whose output is connected to the control input of the first switch 12, the first and second information inputs of which are connected respectively to the third 3 and fourth 4 input buses, the output of the first switch 12 is connected to the information input of the frequency divider 10, the second input bus 2 through the second code-controlled frequency divider 11, whose information input is connected connected to the summing input of the second reversing counter 7 and the input of the second trigger 15, the output of which is connected to the control input of the second switch 13, the first and second information inputs of which are connected respectively to the fifth input bus 5 and

the information output of the first reversing counter 6, the outputs of the forward and reverse transfers of which are connected respectively to the first and second inputs of the first element OR 8, the output of which is connected to the synchronization input of the recording of the first reversible counter 6, the summing and subtracting inputs of which are connected respectively to the first and second inputs the second element OR 9, the output of which is connected to the synchronization input of the recording of the second reversible counter 7, the outputs of the forward and reverse transfers of which are connected respectively summing and subtracting inputs of the first reversible counter 6, the information input of which is connected to the information output of the first reversible counter 6, the first information input of the third switch 17 and the input of the inverter unit 18, the output of which is connected to the second information input of the third switch 17 whose control input is connected to the sixth input bus 19, and the output of the third switch 17 is connected to the output bus 16 of the device.

The device works as follows.

The sequence of pulses divisible with frequency fi through the second input bus 2 is fed to the counting input of the second code-controlled frequency divider 11, and the sequence of pulses of the splitter with frequency h through the first, input bus 1 to the counting input of the first code-controlled frequency divider 10. On the third 3, fourth 4 and fifth 5 input buses, the codes of numbers A, B and C are given, respectively.

A sixth input bus 19 is supplied with a signal controlling the state of the third switch 17. Depending on the value of the control signal (logical O or logical 1) at the output of the switch 17. a direct or inverse code of the number generated at the information output of the first reversible counter is set. 6

The information inputs of frequency dividers 10 and 11 through switches 12 and 13, respectively, depending on the state of the flip-flops 14 and 15, which operate in the T-flip-flop mode, i.e. trigger with a counting input, connects the code of the number A or the code of the number B (to the information input of the frequency divider 10) and the code of the number C or the code of the number K, which is formed on the information output of the counter 6 (to the information input of the frequency divider 11). As a result, at the output of the splitter 1Q frequency, pulse sequences with a frequency f2 / A or with a frequency f2 / B are formed depending on the state of trigger 14, and at the output of the frequency divider 11 - a sequence of pulses with a frequency fi / C or with a frequency fi / K depending on the state of the trigger 15. These pulse sequences are fed to the subtracting and summing inputs of the second reversing counter 7, and the subtracting input of counter 7 receives pulse sequences with frequencies f2 / A and f2 / B, and to the summing input - a successor pulses with frequencies fi / C and fi / K. In addition, pulse sequences with frequencies f2 / An f2 / B control the state of the trigger 14, and pulse sequences with frequencies fi / C and control the state of the trigger 15.

In the steady state measurement, i.e. in the mode in which the mean values of the frequencies fi and f2 remain unchanged, the number of pulses in pulse sequences arriving at the summing and subtracting inputs of counter 7 for equal periods of time are equal. Obviously, two impulses are sent to the subtracting input of the counter 7 for a period of time g - 1 -1-1 -A + Bm

G2 + G75GG 0)

f2 / A T2 / Bt2

and to the summing input of the counter 7 two pulses arrive at the time interval

1 1 C + K, 0 h

1 7-V7T + 7-717-, (2)

f, / C f; / Kf,

Since the device operates in a steady state, there is equality

T1 T2 (3)

or according to (1) and (2)

A + + K ...

-T.-. (4)

B

from here to

g. (A + Bj-C

(five)

Thus, in the steady-state measurement mode, at the output of the counter 6, a code of the number K is generated, which is related to the frequencies fi and f2 by expression (5). The specified code K is fed to the output bus 16 through the switch 17, the output of which (depending on the value of the control signal on the sixth input bus 19) generates a code

Yi k. (A + B) -C (6)

or code number

  -. (A + B) + C + (APP), (7)

where K is the inverse code value; Ap - the maximum value of the number recorded in the counter 6;

A-base number system (usually binary);

n is the number of bits of the counter 6. Thus, in the steady-state measurement mode, the code of the number YI or the code of the number Y2 associated with the frequencies fi and h by the expressions (6) and (7) are recorded at the output of the device.

At deterministic frequency values f 1 and fa, the state of counter 7 changes only within one pulse, which is caused by the presence of a phase shift between frequencies (fi / C + fi / K) or (f2 / A + f2 / B). Typically, the capacity of the reversible counters is set to not less than ten pulses, due to the design of integrated circuits. Consequently, the oscillation of the state of the counter 7 within one pulse does not cause the appearance of signals at its outputs of direct and reverse transfer, and the state of the counter 6 remains unchanged. However, due to statistical oscillations of the frequencies fi and f2, oscillations of the state of the counter 7

5 go beyond one pulse. Therefore, the capacitance Qrt / KJCC of the counter 7 is chosen so that the code of the number Q (t) determining the state of the counter 7 in the steady-state measurement mode ensures

0 condition fulfillment

Q..Q (t) Omax,

at the same time, there are no pulses on the summing and subtracting outputs of the counter 6, and the output code of the number K of the counter 6, and, consequently, the output code of the device remain unchanged.

When changing the average value of the frequencies fi and f2 or the average value of one of them, i.e. when the device is in transition mode, one of the counting inputs of counter 7 receives more pulses than the other. The state of counter 7 begins to change either upward or downward as accumulated

5 pulses until a pulse is received at one of the direct or reverse transfer outputs. This pulse through the logical element OR 9 is fed to the synchronization input of the record of the counter 7 and

0, with its leading edge, records the Q (t) code arriving at its information inputs from its information outputs. In this case, changing the code for information

5 outputs of the counter 7 on the falling edge of the input pulse, and the limit state of the counter 7, which corresponds to the code of the number O O, Q Omax, remains until the direction of accumulation of pulses in the counter 7 changes.

it follows that when counter 7 reaches one of the limit states, each high-frequency pulse uncompensated by a low-frequency pulse repeats at the corresponding transfer output, goes to the corresponding summing or subtracting input of counter 6, and i changes the code K at the information outputs of the last and on the information input of the frequency divider 11 (via the second information input of the switch 13). Changing the code K at the information input of the frequency divider 11 leads to a change in the time interval ri, during which two pulses arrive at the summing input of counter 7, so that the imbalance between time intervals t and Z2 caused by a change in the frequency fi and f2 or one of them decreases. This process is repeated until equality (3) is restored, after which an established measurement mode occurs.

The stated calculations are valid under the condition

1 Ј (A + B) -C An, (8)

where An is the maximum value of the number written in the counter 6. Obviously, under the condition

f2

(A + B) - With An

an overflow of counter 6 will occur, and a pulse appears at its direct transfer output, which through the first logical element OR 8 enters the synchronization input of the record B of the counter and its leading edge records the code of the number A, arriving at its information inputs of the same information exits. At the same time, the change of the code of the number A at the information outputs of the counters 6 along the trailing edge of this pulse is blocked. Thus, after K reaches the value of An, a further increase in K corresponds to the maximum number An given by the code on the information inputs of counter 6, while on the output bus 16 either the maximum code An is set, or zero, depending on the state of the switch 17.

Similarly, the transition of the counter 6 through zero is blocked provided that

Ј. (A + B) -C 1,

while the information outputs of the counter 6 fix the code zero, and on the output bus 16 either the code zero or the maximum code A.

Thus, at the output of the proposed device for measuring the ratio of the frequency of a sequence of pulses, a code CVD is generated associated with the measured ratio of frequency dependencies (6)

and (7):

YBb, x Yi | i. (A + B) -C

or

15

Wow Y2 -: g. (A + B) + C + (An-1),

those. in comparison with the known device implementing the dependence depicted by line a (FIG. 2), in the proposed device it is possible to implement two types of dependencies (line mi and b).

Consequently, the introduction of a third switch, an inverter unit and a sixth input bus with appropriate connections expands the field of application of the device.

by allowing the output of information with different conversion characteristics, in particular, the proposed device can be used in production lines for

presenting information about the proceeding processes in a convenient form and for simultaneous control of automatic controllers with different transient characteristics.

Claims (1)

Apparatus of the Invention A device for measuring the frequency ratio of a pulse sequence according to the author. No. 1620935, characterized by that, in order to expand its functionality, a pole, a third switch and an inverter unit are added to it, the inputs of which are connected to the information outputs of the first reversible pulse counter and the first information inputs of the third switch, the second information inputs of which are connected control of the third switch is connected to the sixth input bus, and the output of the third switch is connected to the output bus of the device. FIG. 2