SU1628193A1 - Interference suppressor - Google Patents

Abstract

The invention relates to the technique of technology and may have been non-zero. In the device for processing pulse signals. The purpose of the invention is to truncate the functionality due to the suppression of both synchronous and asynchronous interference with periola following significantly less information signal duration - comprehended by introducing the N-bit reversing-G1o device of the counter 4, the comparison unit of the cops 5, the initial installation unit 6, the control bus 9. In addition, the device includes a threshold element 11, the register cd VIG., EXCLUSIVE OR 3 element, clock bus 7, input and output tires 8 and 10, the device allows processing to be processed continuously, with a treasure value of the studied clock cycle, in register 2 N last samples of the input sequence are stored, and the contents of counter 4 correspond to the number of 1 stored in register 2. (Odder of counter 4, compare with tiopoi, selection, set by IM code, control 9: b to b, vyo group of inputs of the comparison unit codes 5, and on his descriptions are:, 1, when the number of the counter is greater than or equal to The values of selection threshold. Thus, in a noisy environment, not worse than the specified selection threshold, the device emits information pulses; and suppresses all interferences. 1 il „

Description

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The invention relates to a pulse technique and can be used in a device for processing pulse signals.

The purpose of the invention is to enhance the functionality by suppressing both synchronous and asychronic interference with a period of following a substantially shorter duration of the information signal.

The drawing shows a functional diagram of the device

The device contains a threshold element 1. shift register 2, an EXCLUSIVE OR 3 element, an N-bit reversible counter 4, a code comparison unit 5, an initial setup block 6, a clock bus 7, an input 8, a control 9, and an output 10 bus. The input of the threshold element 1 is connected to the input bus 8, and the output to the information input of the shift register 2, the clock input of which, together with the clock input of the N-bit reversing counter 4, is connected to the clock bus 7, the first and second inputs of the EXCLUSIVE OR 3 element connected, respectively, with the 1st and 2N-M bits of the shift register 1, the counter direction control input of the reversible counter 4 is also connected to the last one, the counting blocking input of which is connected to the output of the EXCLUSIVE OR 3 element, the output of the reversible counter 4 Nena with a first group of inputs code comparing unit 5, a second group of inputs of which is connected to the control bus 9, setting inputs of register 2 and a shift-down counter 4 connected to the output unit 6, the initial setting, and comparing the code output unit 5 is connected to the output bus 1CL

The proposed technical solution performs the functions of the prototype, provided that the numerical value of the code supplied to the control bus 9 is 2 "

For the sake of consistency, consider the case for N 4 ". The shift register is 2 16, the counter 4 and code comparison block 5 are four-bit, and the numeric value of the code supplied to control bus 9 is eight (code 1000).

Let there be a signal in the initial state on the input bus 8 of the device, which is perceived as

5 0 0 5 0

five

0

Signal element 1 as a signal This signal arrives at the information input of shift register 2 Register 2 and counter 4 are pre-resetted when the power is turned on by a pulse from the output of block 6 of the initial setting, therefore O, and 3 are present at the inputs of the EXCLUSIVE element and 1, which, entering the lockout of the counter 4, prohibits his account. The level O supplied to the control input of the counting direction of the counter 4 from the 16th bit of register 2 maintains it in the mode of summation. Since the state of the counter is zero,. less than the permissible threshold (equal to 8) specified by the control code received from bus 9, then at the output of the code comparison unit 5 there is a level O that is fed to the output bus 10 of the device. If the input signal (bus 8) now changes in such a way that signal 1 is output at the output of threshold element 1, then the forward front of the pulse coming from clock bus 7, 1 will register the first bit of shift register 2. At the first input of the element EXCLUSIVE OR 3 appears 1, and on the yoke output - O, which resolves the count to 4, the decrement of the clock pulse of the content of the estimator increases by one and becomes 1 (code 0001). If the duration of the signal 1 at the output of the threshold element 1 is sufficient, then an entry to the 8th rar of dhregister 1 shift occurs, the contents of counter 4 according to the clock pulse is eight (code 1000), t0e. It is equal to the numerical value of the code, if the arc is applied to the second group of inputs of the code comparison block 5 from the control bus 9, and level 1 appears on the output bus 10,

Suppose that in the ninth clock cycle the input signal is changed in such a way that the output of the threshold element 1 is a signal O, which is written on the front of the clock pulse to the first digit of register 2, the state of its bits (0000000111111110). Since on both inputs of the UNIQUE UNIQUE OR 3 there is O, there is a level 1 at its output, which, entering the account lock input

5 1

counter 4, blocking its count, the counter state does not change. On the outgoing bus, G1 is held. If the duration O is less than eight periods of the clock frequency, then the output information does not change, so the information in the first and sixteenth bits of register 2 is the same. (0), therefore, the state of counter 4 does not change. If the duration of the signal O at the output of the threshold element 1 is more than eight periods of the clock frequency, then on the front of the eighth clock pulse the register is 1111111100000000. Since the information in the first and sixteenth bits of register 2 is different, then the output of the EXCLUSIVE OR 3 appears O which allows the counter to count 4. Considering that level 1 is present at the input of the counting direction control, the decay of the current pulse of counter 4 decreases by one and becomes equal to seven (code 0111), which is less than 8 (code 1000) installed on the second group of inputs of the code comparison unit 5, therefore O appears at its output (pin 10)

Thus, at the output of the device, a signal 1 or O is formed, if the duration of the input action, perceived by the threshold element as signal 1 or O, remains unchanged by eight clock pulses,

The proposed device allows to extend the functionality of the prototype.

Know the minimum duration of the information signal, the clock frequency is selected from the conditions:

t F4

1 t 7

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where is t.j. - period of the clock frequency; 21 - - permissible total duration of interference per interval

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in 2 clock pulses; - shift register size

2;

M - the numerical value of the code supplied to the pin, control 9,

CWHH is minimal.

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The input information is processed continuously, with each register clock in register 2 storing

The last 2 samples of the input sequence are counted, and the contents of counter 4 correspond to the number 1 stored in register 2. At its output, 1 appears when the contents of counter 4

greater than or equal to the value of the selection threshold "In this case, the value of the selection threshold characterizes the allowable total duration of interfering pulses per interval

in 2 periods of clock pulses (interference intensity) "Suppose the selection threshold is set to (2N-rO" This means that for an interval of 2 clock pulses, the total duration of interference is equal to M cycles of clock pulses. When the interfering situation is not worse than the given one, the device No informational and suppresses interference pulses.,

Claims (1)

Invention Formula Tomech suppression device containing EPRMR: EXCLUSIVE OR, 2 is a bit shift register, the synchronization input of which is connected to the clock signal bus, threshold, - whose input is connected to the input spike, and the output to the information input of the shift register, characterized in that suppression of both synchronous and asynchronous interference, with a succession of significantly less than the duration of the information signal, an N-bit reversible counter, a comparison block, an initial setup block, which is connected to the setup and the inputs of the shift register and M-bit reversible counter, the input of blocking the account of which is connected to the output of the EXCLUSIVE OR element, and the control input of the counting direction - to the second input of the EXCLUSIVE OR element and the shift of the shift register, to the first output of which is connected the first OUTPUT of the EXCLUSIVE OR, 716281938 the clock input of the N-reair of a single reversing code, the second group of inputs of the counter is connected to the bus of the clock, which is connected to the control bus, signal, and its outputs are connected to the output bus “with the first group of inputs