SU1622950A1 - Device for checking pseudorandom sequence of binary signals - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to reduce the monitoring time. The device contains D-flip-flops 1, 2, elements 3, -4, 6 and 10, inverter 5, reversible counter 7, start element 8, count indicator 9, indicator 11 counting, shift register 12, switching unit 13, sensor unit level 14 and decoder 15 "Reverse counter 7 using elements 1-6 and 8 determines the difference between the number of units and the number of zeros entered between two states. All units of register 12 which are allocated in blocks 13-15. 2 or „

Description

Faye. 7

The invention relates to telecommunications and can be used in equipment for monitoring and testing discrete communication signals,

The purpose of the invention is to reduce the monitoring time,.

FIG. Figure 1 shows the structural electrical circuit of the device proposed; FIG. 2 shows timing diagrams for his work,

A device for controlling a pseudo-random sequence (PSP) of binary signals contains the first 1 and second 2 triggers, the first 3 and second 4 elements And, the inverter 5, the third element And 6, the reversible counter 7, the start element 8, the count indicator 9, the fourth element And 10 , the counting indicator 11, the shift register 12, the switching unit 13, the unit level sensor 14 and the decoder 15,

The device works as follows,.

When the start element 8 is pressed, S-input of trigger 2 and K-in:; one trigger 1 receives logic level 1 and trigger 2 is set to state 1 (FIG. 2a), and trigger 1 is set to state O (Fig. 26 ) "The clock frequency and signals of the memory bandwidth being checked are received at the inputs of the shift register 12" With a high signal from the output of flip-flop 2, the reset state of the reversing counter 7 is held, and the And 3 element is closed. In switch block 13, the switches are set to the position where the inputs of the decoder 15 are connected to the outputs of the bits of the shift register 12 by the number of bits of the memory bandwidth being checked, the other switches are set to position, with the Q.T. PT. the inputs of the decoder 15 are connected to the logic level 1 , formed by the sensor 14 level unit. Thus, regardless of the number of inputs of the decoder 15, it will generate pulses when a combination containing all units in shift register 12 arrives at its input, which occurs once in each memory bandwidth.

When a pulse is formed at the output of the decoder 15 (when a combination of all units enters the shift register 12) by a positive differential (Fig. 2c) of the pulse (falling front), the trigger 2 is transferred to the state

Oh, since at its D-input there is a low-level signal, and the trigger 1 is in state 1 (FIG. 2a, b). In this case, the reset from the reversible counter 7 is removed, the AND 3 element opens, transmitting the clock frequency signals that cut the signals of the units (AND element 2) and through the inverter 5 - zeros (And 6 element) of the checked SRP0 To the summing input of the reversible counter 7 impulses of PSP units arrive, and to the subtracting input, impulses of PSPo zeros. At the same time, account indicator 9 is opened (FIG. 2d), registering the counting process.

At the end of the full period of the memory bandwidth, when the second pulse arrives from the output of the decoder 15 (combination of units in the memory bandwidth checked) trigger 2 remains in state O, and trigger 1 is transferred to state O.

At the same time, element 3 is closed and pulses stop flowing to the reversible counter 7, the count indicator 9 stops working at the same time, and high level signals appear at the inputs of the 10 element, and the end of count indicator 11 registers the end of the test (Fig. 2d). the counter 7 stores the display of the results until the next pressing of the start element 8 (FIG. 2 e).

Having calculated all combinations of ones and zeros in the SRP under study from one All to One State, the reversible counter 7 will register one unit, since in any SRP the number of units exceeds the number of zeros by one unit.

Claims (1)

Invention Formula A device for controlling a pseudo-random sequence of binary signals, containing a reversible counter, serially connected first trigger, first And element and second And element, whose output is connected to the reversing counter adding input, inverter connected in series and the third And element, whose output and second input are connected respectively to input subtracting the reversible counter and with the output of the first element I, connected in series to the shift register, the signal input of which is connected to the input of the inver torus and the second input of the second element AND, which is the input of a pseudo-random 516 the device sequence, the clock input of which is the second input of the first element I, the switching unit and the decoder, the output of which is connected to the synchronization input of the first trigger, and serially connected unit level sensor and the start element, the first and second inputs and output of which are connected respectively to the common wire power supply, with the input of the unit level of the switching unit and with the reset input of the first trigger, characterized in that, in order to reduce the monitoring time, the counting indicator, the second trigger, and edovatelno connected to the fourth AND gate and the indicator terminal count, the output of 06 the decoder and the output of the start element are connected respectively to the synchronization input and to the installation input of the second trigger, the reset input and data input of which and the installation input of the first trigger are connected to the common power wire, the second output of the second trigger is connected to the reset input reversible counter and to the data input of the first trigger, the direct and inverse outputs of which are connected respectively to the input of the count indicator and to the first input of the fourth element And, the second input of which is connected to the inverse input of the second trigger, and the clock input of the shift register is connected to the second input of the first element I0  S-th .. 0ToZ /