SU1725388A1 - Binary counting device with check - Google Patents

Abstract

The invention relates to automation and computing and can be used in equipment with a limited time control; mainly in equipment containing large timers. The essence of the invention: the device contains a differentiating element 4, elements AND-YE 8.9, one-oscillators 6.7, tires .11.12, counter 5, elements 10.14 of indication, N-1 elements II, N-1 triggers 3, binary counter 1, terminal 13 output. In the proposed device, fewer clocks are required to verify the operability of the counter. 3 il.

Description

The invention relates to the field of automation and computer technology and can be used in equipment with a limited time of its control, mainly in equipment containing timers of large time.

The purpose of the invention is to reduce the device monitoring time.

The goal is achieved by introducing new design features into the device.

FIG. 1 shows a diagram of the device, in FIGS. 2 and 3 are graphs of its operation.

The device consists of a binary counter 1, logic elements AND 2, triggers 3, differentiating element 4, counter 5 cycles, one-shot 6 and 7, logic elements AND-HE 8 and 9, element 10 of indication Norm, bus 11, input bus 12, terminals 13 outputs, element 14 of the indication. Standards no.

The input bus 1.2 of the device is connected to the inputs of the counter 1, the differentiating element 4 and the counter 5 cycles.

The number of elements And 2 and the number of triggers in the groups is equal to N-1, i.e. one less than the number of bits in counter 1. Each trigger 3 and its corresponding element AND 2 are bit-wise connected to counter 1, except for the higher bit.

The first inputs of the And 2 elements are combined and connected to the bus 11 of the control, their second inputs are also combined and connected to the output of the differentiating element 4..

The third inputs each of the elements And 2 connected to the direct output of the trigger 3.

The outputs of the elements And 2 are connected to the installation inputs in 1 counting cells of the counter 1.

The outputs of the bits of counter 1 are connected to the inputs of the corresponding triggers 3, and the output of the higher bit of counter 1 is connected to the output terminal 13 and the input of the first one-oscillator 6. The input of the other one-oscillator 7 is connected to the output of the counter 5 cycles.

The first element AND-NOT one input is connected to the output of the one-shot b, the other input is connected to the output of the one-shot 7 and the input of the second element AND-HE 9,. the second input of which is connected to the output of the first AND-HE element 8 and the input of the display element 10. The output of the second element AND NOT 9 is connected to the input of another indication element T4.

The counting factor of the 5 clock counter is set to K N + 1, where N

- the number of bits of the controlled counter 1.

The device works as follows.

In the initial state, counter 1, triggers 3, and counter 5 cycles are reset. Terminal 11 has a voltage of Log.1.

When a counting pulse arrives at the input 12, parallel operation begins.

0 counter 1 and counter 5 tactor. Switching cells in the counters 1 and 5 occurs on the trailing edge of the input pulses. At the output of differentiating element 4, positive pulses are generated in

5 half periods of input signals at times

voltage level changes from 0 to 1.

. On the falling edge of the first pulse on

the input device of the cell in the lower de

counter 1 switches out

0 to state 1. On the leading edge of the second counting pulse, a positive pulse is generated at the output of differentiating element 4, but the output state of the AND 2 element does not change,

5 since its third input is in the state O. On the falling edge of the second pulse, the cell of the first bit returns to O, and the cell: the second bit of counter 1 is set to 1.

0 At the same time, the trigger 3 is triggered, corresponding to the low-order bit of the counter 1. As a result, the state of the third input of the AND 2 element changes from O. Then, at the moment when the leading edge of the third pulse passes through the counting input 12, the pulse from the output of the differentiating element 4 goes through the element I 2 to the installation input of the low-order cell of counter 1 and again translates it into

0 state 1. The state of the other bits of the counter 1 does not change. By the end of the third pulse, the cells of the first and second bits are in state 1, on the falling edge of the third

5 pulses of both cells switches to the O state, and the third discharge cell of counter 1 is set to 1. At the same time, trigger 3, which corresponds to the second discharge of counter 1, is triggered ... Next

0 impulse from differentiating element 4 transfers the first and second digit cells from O to G.

On the trailing edge of the fourth pulse, the first, second and third cells are switched to O, and 1 is written to the fourth cell, and so on.

Thus, after passing through the counting input 12 pulses, the number of which is equal to N + 1, an overflow signal appears at the output of counter 1, the output time of which from the start of operation of the device is monitored by a counter of 5 cycles.

Since the recalculation coefficient of the 5 clock counter is also equal to the value of N + 1, the signals at the inputs of the first and second single vibrators 6 and 7 appear simultaneously. The pulses generated at their outputs are equal in duration.

With a good counter 1, the pulses at the outputs of the one-shot coincide in time, the output of the AND-HE element 8 is a negative pulse that arrives at the input of the indication element Norma. At the output of the element AND-NOT 9 signal at this moment does not occur, since a positive pulse acts on one of its inputs, and a negative pulse of the same duration acts on the other.

In the event of the malfunction of counter 1 (open circuit, component element failure, the counter cell division ratio is not equal to 2), the output state of the AND-NE element 8 does not change during the entire monitoring time and the display element 10 does not work.

After the 5-clock counter has been terminated, a monovibrator 7 is started with a signal from its output.

A positive polarity pulse appears at the input of the NAND 9 element, 1 is fed to the other input from the output of the NAND 8 element, as a result of which the display element 14 is fired. There are no norms,

To switch the device from monitoring mode to binary counting mode, a voltage Log is applied to control terminal 11. A. As a result, the entire group of elements AND 2 is blocked by the input, the conversion factor of counter 1 becomes equal to 2.

As an example, Fig. 2 shows a sequence diagram of the operation of a five-bit counter in the accelerated control mode.

In FIG. 3, for comparison, the graphs of the dependence of the monitoring time (the number of pulses at the counting input) on the number of bits of the monitored counter for the proposed device and the known one.

In comparison with the well-known, we offer my device requires less time to monitor the counter.

The counter is monitored when a minimum number of clock signals is applied to the device’s counting input.

Time control of the proposed device

Tk tn (N + 1),

and the time control of the known device T tn (2N 1-H1).

The positive effect is most pronounced when monitoring multi-bit counters in software-time devices of large time, which is practically not checked in real time.

For control, for example, a 16-bit counter in the proposed device requires - "3.8. 103 times less time than in the famous.

In addition, a side effect is achieved when the counter is monitored. Not only malfunctions of the type of element failure or open circuit are detected, but also non-fault type of transition of the counting cell from the division mode into 2 to the repeater mode (), which will be fixed by the display element 14 . .

Claims (1)

Formula from a routine Binary control rectifier containing the first display element, input bus, M-bit binary counter, each bit of which, except the last one, contains the installation input 1, the output of the last digit of the binary counter is connected with the input of the first single-vibrator, that is so that, in order to reduce the control time, a differentiating element is introduced into it, the first, second AND-NOT elements, the second one-oscillator, the control bus and the counter modulo N + 1, the second element of the display, and in each category d, besides the last binary counter, the element I and the trigger are entered, the dynamic installation input in 1 of which is connected to the output of this bit, the input of installation in 1 of which is connected to the output of the element And, the first, second and third inputs of which are connected respectively to the output of the differentiating element , with the control bus and with the direct output of the trigger, the input bus is connected to the input of the differentiating element, with the counting input of the N-bit binary counter and with the counting input of the counter modulo N + 1, the output of which is connected to the input o one-shot, the output of which is connected to the first inputs of the first and second elements AND-NOT, the second inputs of which are connected respectively to the outputs of the first one-vibration and to the output of the first element AND-NOT, the inputs of the first and second elements of the display, respectively -NOT.