SU1432731A1 - Variable pulser - Google Patents

Abstract

The invention can be used to synchronize data in computer reading channels. The purpose of the invention is to increase the reliability of the generator by forming the first norm. impulse. The goal is achieved by introducing a control bus connected directly to the second input of logic element 2OR-NO 3 directly, and to the output of the OR-NOT 2 inverter through series-connected resistor 6 and diode 7. A feature of the pulse train received on the output bus 9, the duration of which is much less than all the others, because when generation is prohibited, the capacitor 5 is charged to the level lying between the threshold values of the OR-NOT 1 inverter, and by the beginning of the generation the capacitor 5 is already partially charged. In order to eliminate this effect, a diode 7 and a limiting resistor 6 are introduced. The controlled pulse generator has the ability to operate both in continuous and in standby mode, with all the generated pulses of the same duration, 1 slug. (L

Description

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The invention relates to a pulse technique and can be used to synchronize data in the reading channels of a computer,

The purpose of the invention is to increase the reliability of the generator by forming a first normalized pulse.

The goal is achieved by introducing a control NINA connected to the second inlet | 1 of the logic element, STI — NOT directly, and to the output of the second | 1inverter through a series-connected resistor and diode. I The drawing shows an electrical schematic diagram of a controlled pulse generator and a diagram, which explains its principle of operation. ; Controlled pulse generator Consists of the first inverter OR NOT 1 SECOND inverter OR NOT 2, logic element 2 OR OR NOT 3, first resistor 4, capacitor 5, second resistor 6 and semiconductor Diode 7, input 8 and output 9 bus .

The output of the first inverter OR NOT 1 Connected to the input of the second inverter OR NOT 2, the output of which is connected to the first input of the logic element, 2ILI NOT 3, as well as the cathode of the semiconductor diode 7 and through the capacitor 5 to the input of the first inverter OR -NOT 1.

The second input of the logic element 11ИЛИ-НЕ 3 is connected to the input bus 8 and through the first resistor 6, with the cathode of Diode 7, and its output - with the other output 9 and through the second resistor 4 - 4 input of the first inverter OR NOT 1.: Controlled the pulse generator works as follows. ; To begin, consider the operation of a generator without a resistor 6 and diode 7. If the control bus 8 receives a high level of the logic unit, the output of the logic element 2ILITE 3 sets a low level of logic zero, which through the resistor 4 enters the input of the inverter OR NOT 1 and discharges the capacitor 5, 37 of the aviva in such a way at the output of the second OR-NOT 2 inverter a low level. In such a state, generation is prohibited until such time as the low level of the logical zero is established on the control pin. As soon as this happens, on both inputs of the element 2, OR NOT 3, the installer

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a low level of logical zero, and at its output - a high level. The capacitor 5 through the resistor 4 begins to charge. When the capacitor 5 is charged to the threshold level of a logical unit, the OR-NOT 1 and 2 inverters are sequentially switched, and this will lead to the establishment of a high-level element 2OR-NOT on the first input. Accordingly, a low level will be set at its output. The capacitor 5 through the resistor 4 will begin to discharge to a threshold level of logical zero. The inverters OR-NOT 1 and 2 are sequentially switched and the input level of element 2OR is NOT reset to a high level. Thus, one cycle of pulse generation is completed. In the future, the cycle will be repeated.

The peculiarity of the obtained pulse train is the first pulse, the duration of which is much shorter than all the others. This is due to the fact that when generation is prohibited, the capacitor 5 is charged to a level that lies between the threshold values of the OR-NOT 1 inverter, and by the beginning of the generator and the capacitor 5 is already partially charged. To eliminate this effect, a diode 7 is inserted and the 1st resistor is terminated 6. When a high level is prohibited on the input bus line B, a diode 7 is opened and the potential of logical level zero is set on the capacitor 5 plate. The capacitor 5 is discharged and is in a state prepared for the generation of pulses of equal duration. When the enable low is set on the input bus 8, the diode 7 closes and has no effect on the generation process

The proposed generator can be used both in the continuous and in the standby modes, with all the generated pulses of the same duration. This greatly expands its scope.

In addition, the proposed pulse generator can be implemented on both transistor-transistor logic (TTL) circuits4z and K500 series emitter-coupled logic (ECL). The use of ECL circuits allows one to obtain output pulses with a delay not greater than 31D327314

more than 3 NS with respect to the resolution of the third inverter, and the generator's input coupling. torus, connected between the input of the first and second impedance of the inverter,

Claims (1)

Claims of the invention characterized in that A controlled pulse generator, the purpose of increasing reliability, the second one containing a series-connected input of the third inverter, connected three inverters, made by a control bus, which through a subunit 2ILI -NE, connects a resistor to the circuit consisting of a resistor, including - Q is the anode of the diode, the cathode of which is connected between the first input and output with the output of the second inverter.