SU1425823A1 - Pulsed phase detector - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automatic control systems, following electric drives and generator synchronization systems. The invention improves the reliability of detecting synchronous signals. The device contains the element OR I, JK-triggers 2,3 and 4, the elements AND-NOT 5 and 6. The introduction of two logical elements AND-NOT eliminates the formation of a square wave at the output of the detector at the moment of arrival of the clock pulses. The exclusion of the meander from the output signal of the detector when synchronous pulses arrive at its input increases the reliability of operation of the device, since this excludes output signals corresponding to a phase shift of 2 Il. (L

Description

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The invention relates to a pulse technique and can be used in automatic control systems, following electric drives and in generator synchronization systems.

The purpose of the invention is to increase the reliability of detecting synchronous signals.

Figure 1 shows the functional diagram of the pulse-phase detector; figure 2 - timing charts of his work.

The pulse-phase detector contains an element OR 1, JK-triggers 2-4 and elements AND-NOT 5 and 6, while the first input bus is connected to the first input of the element OR 1 and the first J-inputs of the trigger 2-4, the second input bus is connected with the second input of the element OR 1 and the first K-inputs of the flip-flops 2-4, the synchronization inputs of which are connected to the output of the element OR 1, the direct output of the flip-flop 2 is connected to the second J-inputs of the flip-flops 3 and 4 and the first input of the AND-NOT 5 element, the second input of which is connected to the forward code of trigger 3 and the third J input of trigger 4, and the output is C: per th input of AND-NO element 6, a second input coupled to an inverted output of the second flip-flop 4 and K inputs of flip-flops 2 and 3, the output - to the output bus, and an inverse output of the third flip-flop third K-input of flip-flop 2.

Pulse-phase detector works as follows.

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Let, for example, the frequency of the pulses on the first input bus Vx1 be constant, and on the second input bus Vx.2 gradually increase, but at the initial moment the time is less than the frequency of the signals on the first input bus (figure 2). At some instant of time t, the phase mismatch decreases until the impulses on the inputs of the element OR 1 are superimposed over time (t ,, t, t5).

which is equivalent to the synchronous sequence of pulses. Starting from the moment of time t, the triggers 3 and 4 begin to change their states in counter phase, and the trigger 2 is always in the unit state, because for it to go to the zero state, it is necessary that both triggers 3 and 4 were in zero conditions, and

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this is possible only with mismatched arrival of pulses at the detector inputs, when trigger 4 is constantly in the zero state, and trigger 3 changes its state. with the alternate arrival of pulses on the input bus, i.e. when trigger 3 is in phase mode.

The change in the frequency ratio of the pulses arriving at the detector inputs is accompanied by the necessary transition of trigger 3 to the phase mode, so the first single pulse arriving at input Bx 2 after pairs of synchronous pulses (time t) and indicating that the pulse period at input B .2 became less than the period of impulses at input B.1, translates both triggers 3 and 4 into the zero state. Trigger 3 goes into phase mode.

Claims (1)

Thus, the introduction of two logical elements IS-NOT eliminates the formation of a meander at the detector output at the time of the arrival of synchronous pulses, since connecting the element AND-NOT to the outputs of the trigger 2 and 3 eliminates the formation of the meander at its output when the phase change of these triggers, and connecting the second NAND element to the output of the first NAND element and the inverse output of trigger 4 eliminates the formation of a meander at the output of the second NAND element when the phase change of the CONSTITUTION IGN of triggers 3 and 4 occurs, since the output is At this time, the first element of the IS-NOT drive was driven by the introduction of additional connections between the triggers and corresponds to the signal at the inverse output of trigger 3. At the same time, the signal at the output of the second AND-NE element is in accordance with the frequency difference, 5 and with equal frequencies and phase mismatch - in accordance with the state of trigger 3, i.e. with detector output signal. The exclusion of the meander from the output signal of the detector, when synchronous pulses arrive at its input, in turn, increases the reliability of the device, since this excludes output signals corresponding to the phase shift, in reality. Invention Formula Pulse-phase detector containing three JK-flip-flops and an OR element, five 0 0 five the output of which is connected to the synchronization inputs of all JK-flip-flops, the first input is connected to the first input bus and the first inputs of all JK-flip-flops, and the second input is connected to the second input bus and the first K-inputs of all JK-flip-flops, direct output and the second K The input of the first JK flip-flop is connected respectively to the second J-input and the inverse output of the second JK flip-flop, the direct output and the second K-input of which are connected respectively to the second J-input and the inverse output of the third JK flip-flop, characterized in that , with a view to more nor is the reliability of detecting synchronous pulses, it additionally introduces two NAND elements, the first input of the first element. The NAND is connected to the direct output of the first JK-flip-flop and the third J-input of the third JK-flip-flop, the second input to the direct output of the second JK-flip-flop, and the output to the first input of the second NAND element, the second input of which is connected with the inverse of the JK TpHrrepa and the third K-input of the first JK-flip-flop, and the output - with the output bus.