SU1458835A1 - Apparatus for tolerance frequency monitoring - Google Patents

Abstract

The invention relates to the field of instrumentation technology and can be used for frequency tolerance control in automation and control systems. The purpose of the invention is improving speed. The frequency tolerance control device contains cores I and 2, counter-divider 4, reference frequency generator 5, memory register 11 and decoder 12. Introducing counter divider 3, delay element 6, OR element 7 and AND elements 8-10 allow determining the value of the frequency of the input signal is above, below or within the tolerance field during one period of the input signal, and also independently set the nominal frequency value and the value of the tolerance field. 1 il.

Description

1 ate

X 00 00 SP

The invention relates to instrumentation engineering and can be used for frequency tolerance control in automaton systems. tics and controls. ..

The purpose of the invention is to increase speed.

The drawing shows a block diagram of the device.

The device contains counters I and 2, counters dividers 3 and 4, the generator 5 of the reference frequency, the delayed element 6, the element OR-7 and the element AND 8, as well as the elements 9 and 10, the memory register 11 and the decoder 12, the inputs which are connected to the outputs of the memory register 11, and the outputs are the outputs of the device. The output of the generator 5 of the reference frequency is combined with the counting inputs of the counters-dividers 3 and 4, the information inputs of the counter are the inputs of the tolerance code and the code of the nominal frequency of the device. The output of the counter-divider 4 is connected to the input of the delay element 6, the output of which through the element AND 9 is connected to the subtracting input of counter 2. The output of the counter-divider 3 is combined with the second input of the element OR 7 and the input of the element 10, the output of which is connected to the summing the input of the counter 2. The input of the device is combined with the synchronization inputs of the storage register 11 and the counters I and 2, the information inputs of which are combined with the inputs of the fixed device code. The output of the loan of counter 1 is combined with the first input of the storage register 1I and through the second input of the element I B is connected to the subtractive input of the counting 1, and the output of the loan of the counter 2 is combined with the second input of the storage register 11 and the second inputs of the elements 9 and 10.

The device tolerance control frequency works as follows. The synchronization signals of counters 1 and 2 arrive at the pulse signal under study with a frequency F. Each regular impulse enters in-counters 1 and 2 a constant code KO- At this, their inverse loan outputs have 1, due to which the pulses from the outputs of the element OR 7, element 6. Delay and counter-divider .3 through elements And 8-10 pass to the subtracting input of counter 1 and subtract

The summing and summing inputs of the counter 2. The division factors of the counters-dividers 4 and 3 are changed under the influence of the codes Мр and К p supplied to their information inputs. The code of the nominal frequency is N p n Fg, the tolerance code is n UF, where n is a constant coefficient; FIJ - frequency corresponding to a given value; UF - tolerance value. .

Frequency of the output pulses of the counters-dividers 4 and 3

f.P fott

& F

de fo n

N „, 0 /

- frequency generator 5 reference frequency; e is a constant value characterizing the design feature of counters-dividers 3 and 4. Code value

N f.

P

-o N

max

 Due to the delay element 6, the pulses arriving at the inputs of the OR element 7 and the counter 2 do not coincide in time, therefore the frequency of the pulses at the output of the SH-7 element 7.

 4P fo

NFO + N, p N.

one

During the time T between two successive input pulses of the device, the pulses go to the subtracting input of counter 1

N

1 - Npa + NAF

50

Similarly, the summing input of the counter 2 at the same time will receive pulses

N N.

uF

about F and to the subtracting input

 N,.

those. the equivalent number of pulses calculated by the counter. 2 at time T,

N N.

FO - UF

When + uF, i.e. in the case when the number of pulses arriving at the subtracting input of counter 1 during the period of the input frequency F is less than the value of the code N entered into counter 1, by the time of the arrival of the next impulse of the input frequency at the output of the loan, 1.

nominal values are made; during one period of the input frequency, which increases the speed g of the device, in addition, the possibility of separately setting the nominal frequency and magnitude, tolerance, expands the functionality of the device.

ten

Formulas

the invention

A device for frequency control, containing two counters that deduct 15, a memory register, a decoder, a reference frequency generator and the first counter-divider, whose counting input with a reference frequency generator output and information

FO-AF, all of the above applies to counter 2. Therefore, the storage register 11 is loaded with input pulses signals corresponding to 1. Code from the outputs of the memory 20 Dion inputs are sent by the code inputs of register 11 to the inputs of the binary code decoder 12. ny. In the considered case, binary code 11 corresponds to the decimal

the number 3, therefore, at the output of the decoder 12 + iF. appears. At FO + UF through T

25

R

F + UF

at the exit of the loan counter

1 O appears, which arrives at the input of the And 8 element, prevents the counting pulses from passing to the subtracting input of the counter 1. This state of the counter 1 remains until the next pulse arrives at the device input, which enters 1 into the counter N. Counter 2 maintains state 1 at the output of the loan during the entire period of the input signal. Therefore, the binary code 01 is entered into the storage register 11 and the output F - iF + AF of the decoder 12 is set to 30

: 1. For F FQ -uF, through

1 F + U F Loan

time t

the nominal frequency of the device, which is characterized by the fact that, in order to increase speed, the second counter-divider, the delayed elements connected in series, the OR element and the first AND element, as well as the second and third And elements, and the information inputs of the second counter- the divider are the inputs of the device tolerance code, the counting input of the second divider counter is connected to the code of the reference frequency generator, and the output is connected to the second input of the OR element and through 2g the third element AND is connected to the summing input of the second a meter that subtracts the input of which through the second element I is connected to the output of the delay element, the device input is combined with the synchronization inputs of the storage register and the first and second counters, whose information inputs are combined with the input of a constant device code, the subtracting input of the first 45 counter is connected to the output of the first element And, the second input of which is connected to the output of the loan of the first counter and the input of the storage register; the output of the second counter of the loan combined with the second inputs of the second and third elements And the second input of the storage register, the outputs of which are connected to the inputs of the decoder, while the output of the first counter of the counter 1 and through T

FO - uF

on

: The output of the counter 2 is generated, which are stored until the next input pulse arrives, which enters code 00 in the storage register 11, and as a result, the output of the decoder 12 - AF appears 1.

the nominal frequency of the device, which is characterized by the fact that, in order to increase the speed, the second counter-divider, hence the connected delay element, the OR element and the first AND element, as well as the second and third And elements, with the information inputs The second divider counter are the device tolerance code inputs, the second divider counter input is connected to the reference frequency generator code, and the output is connected to the second input of the OR element and through 2g the third AND element is connected to the summing input of the second The sensor, whose subtracting input through the second element I is connected to the output of the delay element, the input of the device is combined with the synchronization inputs of the storage register and the first and second counters, whose information inputs are combined with the input of a constant device code, the subtracting input of the first 45 counter is connected to the output of the first element And, the second input of which is dinene with the output of the loan of the first counter and the input of the storage register; the output of the second counter of the loan combined with the second inputs of the second and third elements And the second input of the storage register, the outputs of which are connected to the inputs of the decoder, while the output of the first counter - f y - f - - -. . V.JJD W1 J. ES 1 NO

In the device tolerance control. The separator is connected to the input of the element and the measurement of it is irrelevant. l „„ „

frequency measurement of the frequency of the input signal and its comparison with

These delays and decoder outputs are device outputs.

e, t 14588354

nominal values are produced within one period of the input frequency, which improves the speed g of the device, moreover, the possibility. separately setting the nominal frequency and magnitude, the tolerance expands the functionality of the device.

ten

Formulas

the invention

A frequency control device containing two subtractive counters, a memory register, a decoder, a reference frequency generator and the first counter-divider, the counting input of which is with the output of the reference frequency generator, and information inputs are entered with code inputs

20 Dion inputs. Avl code inputs.

25

thirty

the nominal frequency of the device, which is due to the fact that, in order to increase the speed, the second counter-divider, the delay element connected in series, the OR element and the first AND element, as well as the second and third AND elements, and the information inputs of the second the divider counter are the device tolerance code inputs, the second divider counter input is connected to the reference frequency generator code, and the output is connected to the second input of the OR element and through 2g the third AND element is connected to the summing input the counter, the subtracting input of which through the second element I is connected to the output of the delay element, the input of the device is combined with the synchronization inputs of the storage register and the first and second counters, the information inputs of which are combined with the input of the permanent device code, the subtracting input of the first 45 counter is connected to the output the first element And, the second input of which is connected to the output of the loan of the first counter and the input of the storage register; the output of the loan of the second counter is combined with the second inputs of the second and third elements And the second input of the storage register, the outputs of which are connected to the inputs of the decoder, while the output of the first counter 0

- f y - f - - -. . V.JJD W1 J. ES 1 NO

a divider is connected to the input element „„ „

ka-divider is connected to the input ale l „„ „

These delays and decoder outputs are device outputs.

Claims (1)

Claim A frequency tolerance control device containing two subtracting counters, a memory register, a decoder, a reference frequency generator and a first divider counter, the counting input of which is connected to the output of the reference frequency generator, and the information inputs are inputs of the nominal frequency code of the device, characterized in that, in order to improve performance, a second counter-divider, a delay element connected in series, an 'OR element and a first And element, as well as a second and third And element, are introduced into it, moreover, the inputs of the second counter-divider are the inputs of the device access code * the counting input of the second counter-divider is connected to the output of the reference frequency generator, and the output is connected to the second input of the OR element and through 'the third AND element is connected to the summing input of the second counter, the subtracting input of which through the second element And is connected to the output of the delay element, the input of the device is combined with the synchronization inputs of the memory register and the first and second counters, the information inputs of which are combined with the input of the constant a device for subtracting input of the first counter is connected to the output of the first AND gate, the second input of which is connected to the output * loan first counter and the input of the memory register; loan output of the second counter of an alternate input pulse, which enters code 00 in the memory register 11, as a result, 1 appears on the output of the decoder 12 F <F - AF. In the frequency tolerance control device, measuring the frequency of the input signal and comparing it with the second inputs of the second and third elements and the second input of the memory register, the outputs of which are connected to the inputs of the decoder, while the output of the first counter55 divider is connected to the input of the element delays, and the outputs of the decoder are the outputs of the device.