SU1367023A1 - Device for converting images - Google Patents

Abstract

The invention relates to automation and computing, specifically to the field of optical information processing and can be used in pattern recognition devices. The aim of the invention is to improve the accuracy and simplify the device due to the special synchronization of the operation of the optical memory block. The device comprises an optical memory unit, a multi-channel optical converter unit and a control unit. Due to the fact that the optical memory unit is implemented on the basis of three-phase D-triggers with optical inputs H outputs, synchronized from the control unit, high accuracy and reliability of image transformations is achieved. 4 il. i SP

Description

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The invention relates to optical information processing and computing technology and can be used in optical image recognition and image normalization devices for performing operations of shifting, rotating and scaling images,

The purpose of the invention is to improve the accuracy and simplify the device due to the special synchronization of the operation of the optical memory block.

FIG. 1 shows a functional diagram of the device; in fig. 2 and 3 are schematic diagrams of the main element of the memory unit and the control unit, respectively; in fig. 4 is a diagram of the operation of the device.

The device contains (Fig. 2) memory block 1, built on the basis of three-phase D-flip-flops with optical inputs and outputs, multichannel - block 2 optical converters, built on the basis of fiber-optical transformers 3 and optical gates 4, control block 5 with three outputs . Input 6 and output 7 of memory block 1 are the inputs and outputs of the device. At the same time, these inputs and outputs are the output and input of multi-channel unit 2. Unit 2 contains various image transformation channels, such as channels for zoom, rotate, pan, etc. All of these operations are performed when the optical signal passes through the corresponding 1st channel. The choice of this channel is carried out with the help of turning on one of the optical gates 4. Electro-optical gates can be used as gates. Each of the elements of the optical memory block 1 is a three-phase D-trigger.

The three-phase D-flip-flop (see Fig. 2) contains the first 8, second 9, third 10 photodetectors, first 11, second 12,; that the third 13 light emitters. All the first terminals of the photo detectors are connected to the power bus E, and the free terminals 14, 15 and 16 of the light emitters 11, 12 and 13 are connected to the first, second and third outputs of the control unit 5. The combination of the inputs of the photodetectors 8 forms the information input 6 of the memory unit 1, and the set of outputs of the light emitters 13 form the information output of the unit 1.

The control unit 5 (see FIG. 3) contains a parallel register 17, a coincidence unit 18, a counter 19, a first 20 inverter, a pulse generator 21, a three-input element 22 I, a second 23 inverter, a first delay element 24, a second delay element 25, an element 26 OR, third element 27

delays. The outputs of the elements 23, 24 and 27 form the first C., the second C and the third Sd outputs of the control unit 5. ; The device works as follows.

To set up the device for any kind of conversion of the original image (for example, zooming), the corresponding optical shutter 4 of the channel 3 of the zoom of block 2 is opened.

the image is recorded in memory block 1 through input 6. The image 5 controls the recording, storing and mixing the image. When reading the image, the original image through output 7 (and the paired same input of block 2) is again scaled and recorded in block 1. 5 controls the number of zoom cycles.

The control of the recording, storage and reading of information in block 1 is carried out with the help of synchronization C, C, St ,, formed by block 5.

The control unit (Fig. 3) operates in the following way.

The code N of the command set on the input bus of register 17 is written to register 17 by the signal D. The same

the signal zeroes the pulse counter 19 and prohibits, via the i-inverter 20, at the time of its operation, the counting of the pulses coming from the generator 21 through the element 22 I.

This means that the codes on the input buses are equal to the zero signal at their output. During the action of the signal D at the output of the block 18 matches - a single signal,

as the counter 19 is reset, and the code of the number N in the register is different from zero. As soon as the signal D stops, a single signal from the output of the inverter 20 and from the output of the block 18 is coincident

solves the arrival of pulses from the generator 21 through the element And 22 to the inputs of the elements 23, 25, 26 and to the counting input of the counter 19 pulses. The pulses from the generator arrive before

the moment of coincidence of the codes in the counter 19 and the register 17, where the code of the number N, i.e. at the output of element 22, a sequence of pulses is formed, after which the block 18 of coincidence gives a zero signal, which prohibits the further arrival of pulses at the output of element 22 and indicates that the operation has been completed. The appearance of the zero signal at the output of block 18 is the resolution for performing another image conversion.

In the initial state, in the absence of a pulse, at the output of element 22, at outputs C, Cj and C, and hence at the corresponding synchronous inputs 14, 15 and 16, there are respectively logic signals 1.1 and 0. Since the supply voltage (+ E) in amplitude close to the voltage level of the logical unit, this means that only the third shoulder of the D-trigger, consisting of the photodetector 10 and the light emitter 13, is under voltage. Let zero signal be written to the trigger in the initial state, i.e. . light emitter 13 not

light, and 11

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and 12 can't take them then it radiates

radiate,

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When a single optical signal appears at the D-input 6, the resistance of the photoreceiver 8 becomes small (light) and with the appearance of a zero potential at the input 14, the light emitter 11 becomes under voltage + Ertz and begins to emit light, which, entering the photoreceiver 8, fixes its excited state to the photodetector 9, reduces its resistance. The zero signal at the third sync input 16 does not disappear immediately on the leading edge of the sync pulse arriving at the output element 22, but after time t, the time goes t, tg, where t g is the key from O to 1 of the trigger memory of the trigger. The presence of a zero signal simultaneously on the synchronous inputs 14 and 16 for the time t, is necessary so that the optical signal from the output of unit 5 affects its input during the activation time of the first trigger arms, since in this case the first arms will reliably operate and will not change signals at the outputs of the third arms of the trigger

15

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 ditch due to the fact that the second shoulders

disconnected by a single signal on the synchronous inputs 15. After turning on the first trigger arm, the photodetector 9 isp

the optical signal from the light emitter P, but the light emitter 12 does not emit, as at the synchronous input level 15 units. The zero level to the input 15 is served not immediately after the first trigger arm is turned on, but through time t, with t ,; t, where b / c is the switching time from 1 to O of the memory arm. This is necessary so that the third shoulder, if it was in a single state, is reliably extinguished. The level zero on the sync input 15 turns on the second trigger arm, i.e. light emitter 12 will begin to emit. In order to reliably turn on the light emitter 12, it is necessary that after applying a zero to the input 15, the light emitter 11 radiates over time t, (i .. Thus, the duration of the zero im20

25

pulse in sync series C (t (-,) should be: t, - t, + t + ti 2 t, + t. The light from 12, acting on the photodetector 9, captures its excited state, and affecting the photodetector 10 , reduces its resistance, thereby preparing it to switch. However, the zero signal to enable

5 of the third shoulder is fed to the synchronous input 16 not immediately after the second shoulder is turned on, but after another time tj (t BiriKf) This is necessary so that the first shoulders of the D-flip-flops are reliably extinguished. The duration of a single pulse in sync series Cj is required.

(tj,) should be: t

+ t, + t7 t, + 2t,

Ci

 t.

2

five

0

2 under the action

a zero signal on the synchronous input 16, the light emitter 13 will begin to emit. The zero signal at input 15 is removed at time t, (t, tg) after the appearance of zero at input 16. This is necessary for reliable ignition of the third arm of the D-flip-flop. The duration of the zero pulse in sync

C} (tr,) should be: t

+ t.

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- 2 t,, + t ,, i.e. t ci

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 tci. A single optical signal from the output of the light emitter 13 is fed to the optical output 7, which indicates the record in the trigger unit. After time t after supplying the unit to input 15, which is necessary for reliably quenching the second trigger arm, the next sync pulse can be fed to the input of the inverter 23, which again produces zero pulses at the outputs (C,) and (C,) and a single pulse at the output ( Se). Thus, the minimum period of following

pulses is:

T,

+ t,

+ t, + t, + t, + t 3 (t, + t,).

The invention makes it possible to abandon a multitude of receptor, threshold, radiative, and light valve elements, which greatly simplifies the design of the device and improves its accuracy.

Claims (1)

Invention Formula An apparatus for image conversion comprising an optical conversion unit, a control unit and a memory unit, characterized in that, in order to increase 67023  These are the first, second, and third gaseous inputs of the memory block, respectively, the first input of the first photo-. the receiver is an information input of the memory unit, and the second input of the first photoreceiver is optically coupled with the output of the first light emitter, the first and second inputs of the second 10 photodetectors are optically connected with the upper and second light emitters, the first and second inputs of the third photoreceiver are optically connected with the outputs of the second and third light emitters, the third light output is an information output of the memory unit, and the control unit contains parallel register, counter, match block whose inputs 20 Connected to the outputs of a parallel register and counter, the first inverter, the input of which is connected to the installation inputs of the counter and parallel register, pulse generator, ele accuracy and simplification of the device, block 25 And, the first, second and third input optical conversions are implemented as a multi-channel optical transformer with optical gates, the information inputs and outputs of the memory block are optically connected to the outputs and inputs of the multi-channel optical transformer respectively, and are the information inputs and outputs of the device, and the three control inputs of the memory block connect. there are three outputs of the control unit, and the memory unit consists of optical C-flip-flops, each of which contains the first, second and third photodetectors and a light beam 40, the first terminals of the photodetectors connected to the power bus, and their second terminals are connected to the first year of the corresponding svetoiz-. radiators, the second conclusions of which are 45 which are connected to the counter input of the counter, the first, second and third delay elements, the OR element and the second inverter, whose input is connected to the output of the AND element, and the output is the first the output of the control unit and is connected to the input of the first delay element, whose input is the second output of the control unit, the inputs of the OR element are connected to the input of the second inverter and the output of the second delay element, whose input is connected to It is connected to the input of the second inverter, and the output of the OR element is connected to the input of the third delay element, the output of which is the third output of the control unit. COP And, the first, second and third inlets which are connected to the counter input of the counter, the first, second and third delay elements, the OR element and the second inverter, whose input is connected to the output of the AND element, and the output is the first the output of the control unit and is connected to the input of the first delay element, whose input is the second output of the control unit, the inputs of the OR element are connected to the input of the second inverter and the output of the second delay element, whose input is connected to It is connected to the input of the second inverter, and the output of the OR element is connected to the input of the third delay element, the output of which is the third output of the control unit. Code 1 f (Ci} i5 (C2) 16 (Cz) Fig. 2 Fig.Z FIG.