SU1213529A1 - Synchronizing device - Google Patents

Abstract

The invention relates to a pulse technique and can be used to synchronize asynchronous pulse sequences with clock pulses. The purpose of the invention is to increase reliability in operation. The device contains input bus 1, buses 2 and 3 clock pulses, triggers 4 and 5, block AND-OR 7 with elements AND 9 and 10, element EXCLUSIVE OR 8 and output bus 6. Introduction of element EXCLUSIVE OR eliminates faulty situations, in any way because of the operation of trigger 5 in the counting mode. The description contains timing diagrams for the operation of the device. 2 pe. in CO ate N9 QD ./

Description

one

The invention relates to a pulse technique and can be used to synchronize asynchronous pulse sequences of clock pulses in automation and computing devices.

The purpose of the invention is to increase reliability in operation.

FIG. 1 shows an electrical functional diagram of a synchronization device; in fig. 2 - time diagrams for his work.

The synchronization device contains the input bus 1, the first and second buses 2 and 3 clock pulses, the first and second triggers 4 and 5, the output bus 6, the AND-OR 7 block and the EXCLUSIVE OR 8 element, the C input of the first trigger 4 is connected to input bus 1, J- and K-inputs - with the first and second clock buses 2 and 3, respectively; direct and inverse outputs - with the first inputs of the first and second elements, AND 9 and 10 of block AND-OR 7, respectively, the first element input is EXCLUSIVE OR 8 is connected to the input line 1, the second input is connected to the output of the AND-OR 7 block, the output is connected to the C-input of the second trigger pa 5, the output of which is connected to the second. the inputs of the first and second elements are AND 9 and 10 of the block AND-OR 7, the third inputs of which are connected According to the first and second 2 and 3 clock buses, the output bus 6 is connected to the output of the AND-OR block 7.

The synchronization device operates as follows.

When an input pulse appears on bus 1 (Fig. 2a), it is a pulse of a single level with a duration shorter than the time interval between the falling edge of the pulse of one clock sequence and the leading edge of the next pulse of another clock pulse sequence (Fig. 25 and 26) An impulse similar in terms of duration is also formed at the output of element B (Figure 2

In case of a falling edge of the input pulse (Fig. 2q) with a clock pulse (Fig. 2B) coming through the bus 3 to the K input of the trigger 4, the latter switches to the zero state (Fig. 2d). With a delay due to a delay in the propagation of a signal in an element

13529

EXCLUSIVE OR 8, trigger 5 is switched by the falling edge of this pulse (Fig. 2). Zero level (Fig. 2d), coming from the direct

5 outputs of trigger 4 on the first & element of stroke AND 9 of block 7, prohibits the output of block I-ШШ 7 clock pulses from bus 3, and a single level coming from the inverse output of trigger 4 to the first input of element AND 10 of block AND-OR 7 , together with the unit level (Fig.2e), coming from the output of the trigger 5 to the second inputs of the elements And 9 and

15 10 block AND-OR 7, permits passing to the output of block I-ШШ 7 of the next clock pulse from bus 2 (Fig. 2x). The same impulse arrives at the bus 6 and through the EXCLUSIVE CLUTTER OR 8 element - to the C input of the trigger 5. With the falling edge of this pulse (Fig. 2a), the trigger 5 switches to the zero state (Fig. 2c). Zero level coming from the output

25 flip-flop 5 to the second inputs of elements AND 9 and 10 of block I-ШШ 7 prohibits the passage of subsequent clock pulses to its output, i.e. after the occurrence of each asynchronous input pulse to the output of the synchronization device, only one pulse of the clock pulse sequence determined by the trigger state 4 passes.

In the case when the input pulse enters the interval between the clock pulses (Fig. 2.6), the trigger 4 does not change its state (Fig. 2d). Therefore, after switching the trigger 5 to the one state (Fig. 2e) front. pulse (Fig. 2.), the output of the block AND-OR 7 passes the next pulse (Fig. 2jf) from the same bus clock pulses, as before (in this case from bus 2). .

When the input pulse (Fig. 2d) coincides with the clock pulse (Fig. 2S) arriving along bus 2, trigger 4 is switched by the falling edge of the input pulse into one state (Fig. 2t) and the next pulse passes through the output of the AND-OR block (Fig. 2g), acting on. bus 3 (Fig. 2S).

55 Introduction of the element 8 EXCLUSIVE OR eliminates faulty situations due to the operation of the trigger 5 in the counting mode.

40

Claims (1)

Invention Formula A synchronization device containing two triggers, the C input of the first of which is connected to the input bus, the I and K inputs, respectively, with the first and second clock buses, the direct and inverse outputs, respectively, with the first inputs of the first and second I elements of AND block -OR, and the output bus, characterized in that, with the aim of the Editor N. Gunko Compiled by T. Sokolov Tehred T. Dubinchak Proofreader V. Sinitska 785/60 Circulation 818 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch PPP Patent, Uzhgorod, st. Project, 4 Reliability in operation, an EXCLUSIVE OR element is entered into it, the first input of which is connected to the input bus, the second input is connected to the output of the AND-OR block and the output bus, the output is connected to the second input of the second trigger, the output of which is connected to the second inputs of the first and the second elements AND block AND-OR, the third inputs of which are connected respectively with the second and first clock tires. Fmg.2