SU1283951A1 - Pulse generator - Google Patents

Abstract

The invention relates to a pulse technique. The aim of the invention is to increase reliability and speed. The pulse generator contains a reference frequency generator 1, a pulse counter 2, a trigger 3, a discrete delay element 4, and an analog delay element 5. To achieve the goal in the generator, the output of the discrete delay element 4 is connected to the input of the analog delay element 5, the output of which is connected to one of the inputs of trigger 3, one of the outputs of which is connected to the input of the reference frequency generator. This pulse generator allows you to increase the speed by 1.5 times. 1 il.

Description

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The invention relates to a pulse technique.

The purpose of the invention is to increase the reliability and speed of the pulse generator,

The drawing shows a structural diagram of the pulse generator.

The pulse generator contains a reference frequency generator 1 pulse counter 2, trigger 3, discrete delay element 4, analog delay element 5, output bus 6,

The output of the generator 1 reference frequency is connected to the input of the counter 2, the output of which is connected to the first input of the trigger 3 ,. the first output of which is connected to the input of the generator 1, the first output of the trigger 3 through the element 4 of the discrete delay is connected to the input of the element 5 of the analog delay, the output of which is connected to the second input of the trigger 3 and the output bus 6.

The device works as follows.

Suppose first that at the first output of the trigger 3 and, accordingly, the chd of the blocking input of the generator 1, there is a potential allowing generation. The pulses from the generator 1 output go to the counting input of counter 2. When passing (A certain number of input pulses at the output of counter 2, a signal appears that triggers trigger 3. From the first output of trigger 3, the potential prohibiting generation goes to the blocking input of generator 1 Generation the oscillation of the reference frequency ceases. At the same time, the potential of the voltage obtained by switching trigger 3 to the second

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Its output, the passage through the discrete delay element 4 and the analog delay element 5, is delayed by a set value and fed to the second input of the trigger 3, switching it to the initial state. At the first output of the trigger 3 at the blocking input of the generator 1, a potential appears that allows generation. At the output of oscillator 1, pulse and reference frequency pulses appear. The process then repeats. The discrete delay element 4 is a delay on discrete elements (cable segments, logic chips of chips, etc.). It performs a period change within Td with discreteness, where n is the number of switchable positions of the discrete delay element, in a particular case. With the help of the analog delay element, the period change within TQ / P is made with the possibility of its smooth variation. Formula from gain

A pulse generator containing a reference frequency generator, the output of which is connected to the counting input of a pulse counter, the output of which is connected to the first trigger input, the first output of which is connected to the input of the discrete delay element, and the analog delay element that is that, in order to increase speed and reliability, the output of the discrete delay element is connected to the input of the analog delay element, the output of which is connected to the second trigger input and output bus, and the second trigger output is connected to the input reference frequency for generators.

Claims (1)

Formula. From acquisition A pulse generator comprising a reference frequency generator, the output of which is connected to a counting input of a pulse counter, the output of which is connected to the first input of a trigger, the first output of which is connected to the input of a discrete delay element, and an analog delay element, characterized in that, in order to improve performance and reliability, the output of the discrete delay element is connected to the input of the analog delay element, the output of which is connected to the second input of the trigger and the output bus, and the second output of the trigger with one with the input of the reference frequency generator.