SU1241468A2 - Pulse repetition frequency divider with controlled pulse duration - Google Patents

Abstract

This invention relates to a digital pulse technique. It can be used in equipment for processing digital information, in automation and digital measuring equipment. It is an additional invention to auth. St. No. 1091351. The purpose of the invention — extending the functionality — is achieved by additionally generating an output frequency signal proportional to the sum of the input codes. For this purpose, the BAN element 10 and the control bus 11 are entered into the frequency divider. In addition, the divider contains a pulse counter 1, buses - input 2, code 5 and 6, output 8 and 9, code comparison elements 3 and 4, trigger 7. Output pulses 8 and 9 generate pulses, the period and duration of which are determined by binary codes on buses 5 and 6, respectively, in the mode of separate setting the frequency and duration of the output pulses. In the mode of summation of frequency setting codes, pulses are formed, the duration and pause of which are determined by the values of binary codes on buses 5 and 6, respectively, and the period is equal to the sum of bus codes 5 and 6. 1 sludge. “O (lu 4 NU O5 CX) INJ

Description

The invention relates to a digital pulse technique, is intended for use in equipment for processing digital information, can be used in automation and digital measuring equipment and is an improvement of the basic invention according to the author. St. No. 1091351.

The purpose of the invention is to expand the functionality by allowing the additional generation of an output frequency signal proportional to the sum of the input codes.

The drawing shows a structural electrical circuit of a pulse frequency divider with adjustable pulse duration.

An adjustable pulse width pulse frequency divider contains a pulse counter 1, the counting input of which is connected to the input bus 2, and the outputs to the first groups of inputs of the first and second elements 3 and 4 of the code comparison, the second groups of inputs of which are connected respectively to the first and second code buses 5 and 6, trigger 7, the inverse and direct outputs of which are connected to the control inputs of elements 3 and 4, respectively, as well as the first and second output buses 8 and 9, respectively; the reset input of trigger 7 is connected to the output of element 4 and the first reset input of counter 1, the trigger start input of 7 is connected to the output of element 3 and the second input of element 10 BANCH, the first input of which is connected to the control bus 11, and the output to the auxiliary reset input of counter 1.

Before you start, you must set the device operation mode. For this, a logical zero or a logical one level is supplied to bus 11. Level zero on bus 11 is present when the device performs a separate setting of the frequency and duration of the output pulses, and the level of one when the codes are combined to set the frequency of the output pulses.

The device in the mode of separate setting the frequency and duration of the output pulses operates as follows.

In the initial state, the counter 1 is reset at the output of elements 3 and 4 — unit levels, at the input bus 2 — zero level, trigger 7 is reset, at the output bus 8 — unit level, which unlocks element 3, at the output bus 9 — zero level which blocks element 4, on bus 11, a zero level, which keeps unit 10 at the output of element 10 and does not allow zero level from element 3 to pass to the auxiliary reset input of counter 1, for example, an OOP code is set on code bus 5,

equal to three, which corresponds to the duration of the output pulses. On code bus 6, there is an OP1 code of seven and corresponding to the value of the period of the output pulses.

Upon receipt of the clock pulses on the bus 2, the counter 1 counts them to the value of the code set by bus 5; on the third clock pulse in the counter 1, an OOP code is set which coincides with the bus code 5. As a result of the coincidence of the codes at the output of element 3, a zero level is produced, according to which the trigger 7 is set to one state. The change of states at the output of the trigger 7 leads to the blocking of the operation of the element 3, on

the output of which is set to a single level. At the same time, the operation of element 4 is permitted. The zero level from the output of element 3 does not pass through element 10, since the zero level is set on bus 11, and

does not affect the counter 1. Counter 1 continues to recalculate pulses to the value of code 0111. At this point, the code of counter 1 coincides with the code specified by bus 6, element 4 triggers, giving zero output at which counter 1 and trigger 7 is set in the initial state. After the trigger 7 is set to the initial state, the zero level on the bus 9 blocks element 4 and a single level is set at its output, which permits operation of the counter 1. At the same time, output pulses are formed on the output buses 8 and 9, the period and duration of which are determined by the values binary codes on code buses 6 and 5, respectively, i.e. The proposed device retains the functions of the known, namely, it allows separately controlling the division factor of the device and the duration of the pulse at its output. In this case

T T, Ni, U)

where T is the period of the following output pulses;

T | - the period of the following clock pulses;

NI is the value of the code value specified by the code bus 6. With N, 7, T 7T, the device operates in the mode of summation of frequency setting codes as follows.

On bus 11, a single level is set, on bus 5, the OOP code corresponding to the length of the output pulses; on bus 6, code 0111, corresponding to the length of the pause between the output - HfjiMH pulses. The initial state of the elements is similar to that described. Upon receipt of the clock pulses on the bus 2, the counter 1 counts them up to the code value set by OJIN 5. If the output of the counter 1 coincides with that of the bus 5, the

Step 3 generates a zero level at which the trigger 7 is set to one, and the output of element 10 is set to zero, by which counter 1 returns to the initial state. The change of states at the output of the trigger 7 leads to the blocking of the operation of the element 3, at the output of which a single level is set, by which the element 10 returns to the initial state. OdPri N2 3 and NI 7, we have T YuT. Therefore, when installing codes NI and N2 identical for the first and second modes, we have that By setting the corresponding mode, frequencies can be changed with fixed NI and N2 codes. Thus, on the output buses 8 and 9, pulses are generated, the period and duration of which are determined by the values of the binary codes on the code buses 6 and 5, respectively

the operation of element 4 is resolved at the time in a separate installation mode. Counter 1 starts counting from the initial state and at the moment the code value at the output of counter 1 coincides with the code specified on bus 6, element 4 triggers, issuing a zero level at the output counter 1 and trigger 7 are reset. After the trigger 7 is set to the initial state, the zero level on the bus 9 blocks element 4 and a 1 level is set at its output, which permits operation of the counter 1.

In this case

 T T, N2 + T, Ni (2)

where T is the period of the following output pulses;

20

frequencies and durations of output pulses, and in the mode of summation of frequency setting codes, pulses are generated, the duration and pause of which are determined by the values of binary codes on code buses 5 and 6, respectively, and the period is equal to the sum of bus codes 5 and 6.

Claims (1)

Invention Formula Pulse frequency divider with adjustable pulse duration according to aut. St. No. 1091351, characterized in that, in order to expand the functionality by providing the possibility of additional signal formation, the value of the code value N2 sets 25 the output frequency proportional to my code bus 5; Ti.N2-duration of the output pulses; TI-NI is the duration of the pause between output pulses. From formula (2) it follows that the output frequency depends on the sum of the codes specified by code buses 5 and 6. the sum of the input codes, the BAN item and the control bus, which is connected to the first input of the BAN, the second input of which is connected to the output of the first code comparison element, and the output to the auxiliary pulse counter reset input. With N2 3 and NI 7, we have T YuT. Therefore, when installing the codes NI and N2 identical for the first and second modes, we have that By setting the corresponding mode, frequencies can be changed with fixed NI and N2 codes. Thus, on the output buses 8 and 9, pulses are generated, the period and duration of which are determined by the values of the binary codes on the code buses 6 and 5, respectively 10 is legally in split mode 20 frequencies and durations of output pulses, and in the mode of summation of frequency setting codes, pulses are generated, the duration and pause of which are determined by the values of binary codes on code buses 5 and 6, respectively, and the period is equal to the sum of bus codes 5 and 6. Invention Formula Pulse frequency divider with adjustable pulse duration according to aut. St. No. 1091351, characterized in that, in order to expand its functionality by providing the possibility of additionally generating a signal sum of input codes, a BAN element and a control bus are introduced into it, which is connected to the first input of the BAN element, the second input of which is connected to the output of the first code comparison element and the output is with an additional pulse counter reset input.