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SG11201807493WA - Ground reference scheme for a memory cell - Google Patents

Ground reference scheme for a memory cell

Info

Publication number
SG11201807493WA
SG11201807493WA SG11201807493WA SG11201807493WA SG11201807493WA SG 11201807493W A SG11201807493W A SG 11201807493WA SG 11201807493W A SG11201807493W A SG 11201807493WA SG 11201807493W A SG11201807493W A SG 11201807493WA SG 11201807493W A SG11201807493W A SG 11201807493WA
Authority
SG
Singapore
Prior art keywords
digit line
boise
memory cell
international
voltage
Prior art date
Application number
SG11201807493WA
Inventor
Daniele Vimercati
Scott Derner
Vincenzo Umberto Di
Christopher Kawamura
Eric Carman
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11201807493WA publication Critical patent/SG11201807493WA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2297—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2293—Timing circuits or methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Medicinal Preparation (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property -, Organization IIIMI41101110101011111 HO 11111011101 10110111011100111110 1111 III International Bureau 0.. .1 j ..... ..or::,„, (10) International Publication Number (43) International Publication Date WO 2017/151803 Al 8 September 2017 (08.09.2017) WIP0 I PCT (51) International Patent Classification: (81) Designated States (unless otherwise indicated, for every G1 1C 11/22 (2006.01) kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, (21) International Application Number: BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, PCT/US2017/020251 DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, (22) International Filing Date: HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, 1 March 2017 (01.03.2017) KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, (25) Filing Language: English NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, (26) Publication Language: English RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, (30) Priority Data: ZA, ZM, ZW. 15/057,914 1 March 2016 (01.03.2016) US (84) Designated States (unless otherwise indicated, for every (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; kind of regional protection available): ARIPO (BW, GH, 8000 S. Federal Way, Boise, ID 83716-9632 (US). GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, (72) Inventors: VIMERCATI, Daniele; 8000 S. Federal Way, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, Boise, ID 83716-9632 (US). DERNER, Scott, James; TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, 8000 S. Federal Way, Boise, ID 83716-9632 (US). DI DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, VINCENZO, Umberto; 8000 S. Federal Way, Boise, ID LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, — 83716-9632 (US). KAWAMURA, Christopher, John; SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). 8000 S. Federal Way, Boise, ID 83716-9632 (US). CAR- MAN, Eric, S.; 8000 S. Federal Way, Boise, ID 83716- Declarations under Rule 4.17: 9632 (US). — as to applicant's entitlement to apply for and be granted a Agent: KRAFT, Aaron, J.; Holland & Hart LLP, P.O. patent (Rule 4.1700) (74) Box 11583, Salt Lake City, UT 84147 (US). [Continued on next page] Title: GROUND REFERENCE SCHEME FOR A MEMORY CELL (54) (57) : Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be em- ployed in a digit line voltage sensing operation. A positive voltage may be = Apply a positive voltage to a ferroelectric capacitor of the ferroelectric memory cell, applied to a memory cell; and after a voltage of the digit line of the cell has = wherein the ferroelectric capacitor is in -- reached a threshold, a negative voltage may be applied to cause the digit line = — electronic communication with a digit line s ••• 1005 voltages to center around ground before a read operation. In another ex- am vol e p ta l g e athat first is v eg o u lt a a lt g m e o an v ay in b e a ers p e p o l f ie t d he to fir a st m vo em itag o ry e m ce a ll y b ad then e n appli a second edtoa ref- - I = = erence capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a — = = Determine that a vo tage of the digit line read operation. has reached a threshold in response to the ..‘ — applied positive voltage ‘*- 1010 = — Apply a negative voltage to the ferroelectric capacitor after the voltage of --, 11 the digit line reaches the threshold k. 1015 .4 en © GC 1000 ki) 11 ,-.... FIG. 10 IN 11 © N O WO 2017/151803 Al MIDEDIM01101DERMEMOMOVEMOIE11111111111111111110110111111 — as to the applicant's entitlement to claim the priority of Published: the earlier application (Rule 4.17(iii)) — with international search report (Art. 21(3))
SG11201807493WA 2016-03-01 2017-03-01 Ground reference scheme for a memory cell SG11201807493WA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/057,914 US9934837B2 (en) 2016-03-01 2016-03-01 Ground reference scheme for a memory cell
PCT/US2017/020251 WO2017151803A1 (en) 2016-03-01 2017-03-01 Ground reference scheme for a memory cell

Publications (1)

Publication Number Publication Date
SG11201807493WA true SG11201807493WA (en) 2018-09-27

Family

ID=59724273

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201807493WA SG11201807493WA (en) 2016-03-01 2017-03-01 Ground reference scheme for a memory cell

Country Status (8)

Country Link
US (3) US9934837B2 (en)
EP (1) EP3424052B1 (en)
JP (1) JP7022071B2 (en)
KR (1) KR102248175B1 (en)
CN (1) CN109074837B (en)
SG (1) SG11201807493WA (en)
TW (2) TWI623935B (en)
WO (1) WO2017151803A1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10325641B2 (en) * 2017-08-10 2019-06-18 Ivani, LLC Detecting location within a network
US9934837B2 (en) * 2016-03-01 2018-04-03 Micron Technology, Inc. Ground reference scheme for a memory cell
US11403241B2 (en) 2017-10-02 2022-08-02 Micron Technology, Inc. Communicating data with stacked memory dies
US10446198B2 (en) 2017-10-02 2019-10-15 Micron Technology, Inc. Multiple concurrent modulation schemes in a memory system
US10725913B2 (en) * 2017-10-02 2020-07-28 Micron Technology, Inc. Variable modulation scheme for memory device access or operation
US10410721B2 (en) * 2017-11-22 2019-09-10 Micron Technology, Inc. Pulsed integrator and memory techniques
US10446214B1 (en) * 2018-08-13 2019-10-15 Micron Technology, Inc. Sense amplifier with split capacitors
US10902935B2 (en) * 2018-08-13 2021-01-26 Micron Technology, Inc. Access schemes for access line faults in a memory device
US11360704B2 (en) 2018-12-21 2022-06-14 Micron Technology, Inc. Multiplexed signal development in a memory device
US10692557B1 (en) 2019-04-11 2020-06-23 Micron Technology, Inc. Reference voltage management
US11056178B1 (en) * 2020-07-20 2021-07-06 Micron Technology, Inc. Read operations based on a dynamic reference
US11749329B1 (en) * 2022-05-20 2023-09-05 Micron Technology, Inc. Off-state word line voltage control for fixed plate voltage operation
CN115754604B (en) * 2022-11-22 2025-10-31 广东电网有限责任公司茂名供电局 Grounding reliability judging method and device based on charge loss

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KR100256226B1 (en) 1997-06-26 2000-05-15 김영환 Reference voltage generator
KR100381023B1 (en) * 1999-05-13 2003-04-23 주식회사 하이닉스반도체 Ferroelectric random access memory having bitline charge pumping circuit
US20050094457A1 (en) 1999-06-10 2005-05-05 Symetrix Corporation Ferroelectric memory and method of operating same
JP2001319472A (en) * 2000-05-10 2001-11-16 Toshiba Corp Semiconductor storage device
JP4153780B2 (en) 2002-11-25 2008-09-24 富士通株式会社 System and ferroelectric memory data reading method
CN100505088C (en) * 2003-02-27 2009-06-24 富士通微电子株式会社 Semiconductor memory device and data reading method
EP1622162B1 (en) * 2003-04-10 2009-11-18 Fujitsu Microelectronics Limited Ferroelectric memory and method for reading its data
KR100568861B1 (en) 2003-12-15 2006-04-10 삼성전자주식회사 Ferroelectric memory device with reference voltage generator
US7009864B2 (en) * 2003-12-29 2006-03-07 Texas Instruments Incorporated Zero cancellation scheme to reduce plateline voltage in ferroelectric memory
JP4785180B2 (en) * 2004-09-10 2011-10-05 富士通セミコンダクター株式会社 Ferroelectric memory, multilevel data recording method, and multilevel data reading method
JP4638193B2 (en) * 2004-09-24 2011-02-23 パトレネラ キャピタル リミテッド， エルエルシー memory
US8570812B2 (en) 2011-08-23 2013-10-29 Texas Instruments Incorporated Method of reading a ferroelectric memory cell
US20140029326A1 (en) * 2012-07-26 2014-01-30 Texas Instruments Incorporated Ferroelectric random access memory with a non-destructive read
US9934837B2 (en) * 2016-03-01 2018-04-03 Micron Technology, Inc. Ground reference scheme for a memory cell

Also Published As

Publication number Publication date
US20180190337A1 (en) 2018-07-05
TW201735038A (en) 2017-10-01
EP3424052B1 (en) 2021-09-15
EP3424052A4 (en) 2019-11-06
TW201824280A (en) 2018-07-01
US10978126B2 (en) 2021-04-13
EP3424052A1 (en) 2019-01-09
US20190130955A1 (en) 2019-05-02
TWI623935B (en) 2018-05-11
US9934837B2 (en) 2018-04-03
KR102248175B1 (en) 2021-05-06
US20170256300A1 (en) 2017-09-07
KR20180110682A (en) 2018-10-10
CN109074837B (en) 2021-02-09
CN109074837A (en) 2018-12-21
WO2017151803A1 (en) 2017-09-08
JP7022071B2 (en) 2022-02-17
JP2019513278A (en) 2019-05-23
US10163482B2 (en) 2018-12-25
TWI673713B (en) 2019-10-01

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