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SG11201903787YA - Exploiting input data sparsity in neural network compute units - Google Patents

Exploiting input data sparsity in neural network compute units

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Publication number
SG11201903787YA
SG11201903787YA SG11201903787YA SG11201903787YA SG11201903787YA SG 11201903787Y A SG11201903787Y A SG 11201903787YA SG 11201903787Y A SG11201903787Y A SG 11201903787YA SG 11201903787Y A SG11201903787Y A SG 11201903787YA SG 11201903787Y A SG11201903787Y A SG 11201903787YA
Authority
SG
Singapore
Prior art keywords
input
international
activation
activations
memory
Prior art date
Application number
SG11201903787YA
Inventor
Dong Hyuk Woo
Ravi Narayanaswami
Original Assignee
Google Llc
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Publication of SG11201903787YA publication Critical patent/SG11201903787YA/en

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/15—Correlation function computation including computation of convolution operations
    • G06F17/153—Multidimensional correlation or convolution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G06N20/10—Machine learning using kernel methods, e.g. support vector machines [SVM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0495—Quantised networks; Sparse networks; Compressed networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
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    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/10—Interfaces, programming languages or software development kits, e.g. for simulating neural networks
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00—Computing arrangements using knowledge-based models
    • G06N5/04—Inference or reasoning models
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
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  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Neurology (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Medical Informatics (AREA)
  • Image Analysis (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
  • Memory System (AREA)
  • Storage Device Security (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property :::` , 1111111011110111011111111111011111010111111111101110111111111111111111111111110111111 Organization International Bureau (10) International Publication Number (43) International Publication Date .....•\"\" WO 2018/080624 Al 03 May 2018 (03.05.2018) W I PO I PCT (51) International Patent Classification: NARAYANASWAMI, Ravi; 1600 Amphitheatre Park- G06N 3/10 (2006.01) way, Mountain View, California 94043 (US). (21) International Application Number: (74) Agent: HENRY, Joel et al.; Fish & Richardson P.C., P.O. PCT/US2017/047992 Box 1022, Minneapolis, Minnesota 55440-1022 (US). (22) International Filing Date: (81) Designated States (unless otherwise indicated, for every 22 August 2017 (22.08.2017) kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, (25) Filing Language: English CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, (26) Publication Language: English DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, (30) Priority Data: HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, 15/336,066 27 October 2016 (27.10.2016) US KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, 15/465,774 22 March 2017 (22.03.2017) US MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, (71) Applicant: GOOGLE LLC [US/US]; 1600 Amphitheatre SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, Parkway, Mountain View, California 94043 (US). TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (72) Inventors: WOO, Dong Hyuk; 1600 Amphitheatre (84) Designated States (unless otherwise indicated, for every Parkway, Mountain View, California 94043 (US). kind of regional protection available): ARIPO (BW, GH, (54) Title: EXPLOITING INPUT DATA SPARSITY IN NEURAL NETWORK COMPUTE UNITS 300-- INSTRUCTIONS, INPUT ACTIVATIONS, AND WEIGHTS/PARAMETERS 303--- t Bitmap 1 1 ° 1 1 1 6 1 1 1 ° 1 1 1 ° ( 1 ) ( ) 3 + ( ) 5 ( ) 7 Weights and Partial Sums (Second Memory 110) Controller 302 310 First Activiations 102 Memory 108 Input 310 310 Activation Bus Parameters MAC 304 T r104a f Parameters MAC 304 r104b IL f Parameters MAC 304 r104c 306 —2 Output Activation Bus I 1 , 308 305 -- UU1 t. EI1 i ,-1 .4 I I - (57) : A computer el a controller of the computing device, whether each of the input activations has either a zero value or a non-zero value. The method 0 further includes storing, GC © activation includes generating - non-zero values. The GC ,_ 1 onto a data bus that is © memory address location N ( 1 ) ( ) 3 ( 5 ) ( ) 7 FIG. 3 -implemented method includes receiving, by a computing device, input activations and determining, by in a memory bank of the computing device, at least one of the input activations. Storing the at least one input an index comprising one or more memory address locations that have input activation values that are method still further includes providing, by the controller and from the memory bank, at least accessible by one or more units of a computational array. The activations are provided, at least associated with the index. one input activation in part, from a C [Continued on next page] WO 2018/080624 Al MIDEDIMOMMIDIREEMOOMMMONEDIDEHMEMOIMIE GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(U)) — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))
SG11201903787YA 2016-10-27 2017-08-22 Exploiting input data sparsity in neural network compute units SG11201903787YA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/336,066 US10360163B2 (en) 2016-10-27 2016-10-27 Exploiting input data sparsity in neural network compute units
US15/465,774 US9818059B1 (en) 2016-10-27 2017-03-22 Exploiting input data sparsity in neural network compute units
PCT/US2017/047992 WO2018080624A1 (en) 2016-10-27 2017-08-22 Exploiting input data sparsity in neural network compute units

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SG11201903787YA true SG11201903787YA (en) 2019-05-30

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US (6) US10360163B2 (en)
EP (2) EP3533003B1 (en)
JP (2) JP7134955B2 (en)
KR (4) KR102679563B1 (en)
CN (2) CN114595803B (en)
DE (2) DE202017105363U1 (en)
HK (1) HK1254700A1 (en)
SG (1) SG11201903787YA (en)
WO (1) WO2018080624A1 (en)

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