RU2680217C1 - Digital predictor - Google Patents

Abstract

FIELD: data processing.SUBSTANCE: invention relates to information processing means for predicting stationary and non-stationary random processes. Prediction unit of a digital prediction device contains three subtractors, two subblocks for calculating quadratic and linear predictions, subblock for calculating the first derivative, averaging adder, subblock for calculating the increments of the process speed, scheme for correcting the forecast code for dynamics and subunit for correcting the forecast code.EFFECT: technical result consists in expanding the functionality by increasing the forecast time by four times.1 cl, 5 dwg, 1 tbl

Description

The invention relates to automation and computer technology and can be used to predict stationary and non-stationary random processes, improve the quality and accuracy of control in digital control systems and guidance of various (including ballistic) objects.

A digital predictive and differentiating device is known (RF patent No. 2450343, IPC G06F 17/17, 02/10/2012, bull. No. 13), which contains a smoothing unit and a forecast unit, which includes: three subtractors, a forecast dynamics control unit, two subunits quadratic and linear forecasts and two subunits of calculating the first derivative at the (n-1) th and (n-2) th calculation points of the history of the input smoothed process. The device is functionally limited.

The closest in technical essence to the claimed device is selected as a prototype, adaptive digital smoothing and predictive device (RF patent No. 2626338, IPC G06F 15/00, 07/26/2017, bull. No. 21), containing a smoothing unit and a forecast unit, which includes: three subtractors, two sub-blocks of quadratic and linear forecasts, a sub-block for calculating the first lead-in at the (n-1) -th calculation point of the input process history buffer, a forecast code correction scheme and a forecast dynamics control unit. The device has a relatively large amount of equipment and is functionally limited.

In practice, by the nature of the change in time, discrete random processes (SPs) can be divided into two types (modes): steady-state (stationary) and transitional (hereinafter “dynamics”). The first is characterized by the steady-state velocity of the median (deterministic basis) of the joint venture, the second is non-linear and takes a relatively short time to transition the median of the joint venture to a new steady-state speed. The spectrum of changes in the velocity of the median SP can occupy a rather large range: from slowly varying to high speeds (almost a jump).

In the prototype, as well as in analogs, the best approximation of the analytical operators of quadratic and linear forecasts is implemented based on approximating polynomials for 4 points (ordinates) of a three-level buffer storage of the history of the input random discrete process using the least squares method, and the forecast time interval (depth) h is one third of the time (B _t ) of the storage of ordinates in the history buffers B _t = 3h. For example, a forecast for Н = h = 10 sec., Requires storing information about the process in the history memory buffer for a period of B _t = 3h = 30 sec., And with the onset of dynamics (switching to a different speed of the median SP) new (fresh) information ( at _n ) it arrives only at the 1st level of the history buffer, at 2 others (at _n-1 , at _n-2 , at _n-3 ) the data of the old mode are stored and taken into account: naturally, the current forecast discretes for this period is significantly different from reality and cannot be used.

The technical problem for the proposed device is to expand the functionality by increasing the real-time (depth) forecast by four times with the same amount of historical memory buffer, without any significant damage to the accuracy of the forecast, i.e. (see example above) now when setting a new quadruple real-time forecast H = 4h = 40 sec. the storage time of information and the memory size of the history buffers will remain unchanged B _t = 3h = 30 sec., but not B _t = 3Н = 120 sec. in accordance with the analytical formulas for calculating the forecast.

Therefore, in a digital predictive device, which includes a smoothing unit containing m = 32 series-connected channels, the input of the first channel being the information input (x _p ) of the device, the register and the multiplexer, the outputs of each m = 1, 2, 4, 8, 16 and 32 channel channels are connected to the information inputs of a multiplexer, the address input of which is connected to the output of the register, the input of the latter is connected to the second control input of the device to set the degree (efficiency) of smoothing k = 0, 1, 2, 3, 4, or 5 ( m = 2 ^k), and an output (y _n) multi leksora wound on the input of the first subtracter block prediction, and prediction unit comprising first, second and third subtracters, each of which includes a memory buffer register, the multiplexer, and an adder unit inverters; a quadratic prediction calculation subunit containing three adders and an inverter; the output of the third adder is the output of the subunit; a sub-block for calculating a linear forecast from one adder, the output buses of which are mountingly shifted (to the right) by one bit towards the lower digits and are the output of the sub-block; a prediction dynamics control unit comprising a prediction time setting input register, the input of which is the first control input of the device defining a forecast interval, an inverter, a counter and a multiplexer, the output buses of the prediction time setting input register being connected directly to the first input of the multiplexer shifted to the mounting right three digits - to the second input of the multiplexer and, mountingly shifted to the left by one digit, through the inverter, - to the counter input, the multiplexer output is connected to the address inputs of the mul ipleksorov all three subtractors; a subunit of calculating the first derivative, which includes three adders, the output of the latter is the output of the subunit with the code of the first derivative (y ' _n-1 ) at the (n-1) -th calculation point of the input history buffer; a timing unit of a forecast block comprising a delay element, a trigger, a pulse generator, an AND element, and a shift register; adder averaging discrete outputs of sub-blocks of quadratic and linear forecasts; a dynamic prediction code correction scheme containing four adders and a multiplexer; stationary correction code prediction correction sub-unit, comprising an adder; a subunit for counting process speed increments containing a scheme for generating the absolute value of the first derivative (y ' _n-1 ), two series-connected storage registers of the current y' _n-1 [(wT)] and the previous y ' _n-1 [(w-1) T)] process speed discrete, two parallel channels (for increasing and decreasing) for counting process speed increments, each of which includes a comparator, two And elements and a four-digit increment counter, an OR element and a mode trigger, with the output of the first And element in each the channel is connected to the counter input of the counter to the reset bus at “0” of the counter of another channel, the output of the OR element is connected to the installation input at “1” of the mode trigger and to the write bus of the counter of the forecast dynamics control unit, and the direct transfer output of this counter is connected to the reset bus to the “0” of the trigger, direct (“1”) output of which is connected to the address inputs of the multiplexers of the dynamics control unit and the correction scheme of the forecast code for the dynamics, the output of the subunit of calculating the first derivative through the circuit of generating its absolute value is connected to the input of the first register of the subunit of expansions, and the outputs of both registers are connected, respectively, to the inputs of the comparators of both channels, to solve the problem in the correction scheme of the prediction code on the dynamics of the bus of the first input of the first adder, mountingly shifted to the right by one bit (towards the lower digits), connected to the output of the adder averaging, the second input of the first adder is connected to the output of the inverter of the third subtracter, the output buses of the first adder, mounting shifted to the right by one bit, and mounting shifted to the right by two bits, are connected, respectively Actually, to the first and second inputs of the second adder, the output of which is connected to the first input of the third adder, the second input of which is connected to the output busbars of the first adder, three-left shifted, the output of the third adder is connected to the first input of the fourth adder, the second input of which is wound to the output of the third subtractor multiplexer, the output of the fourth adder is connected to the second information input of the multiplexer of the prediction code correction scheme, and the first input of the adder of the code correction subunit is the node in stationary mode is connected to the output buses of the averaging adder that are mounted one-right shifted to the right, the second input of the adder of the prediction code correction subunit is connected to the output of the second adder of the prediction code correction circuit, the output of the subunder adder is connected to the first information input of the correction circuit multiplexer , and the multiplexer output is the output of the device.

The invention is illustrated by drawings, which depict: in FIG. 1 is a block diagram of the proposed device; in FIG. 2 is a block diagram of one channel of a smoothing unit; in FIG. 3 is a block diagram of a timing unit of a forecast block; in FIG. 4 is a diagram of the formation of the absolute value of the velocity of the SP; in FIG. 5 is a graphical interpretation of the derivation of the formulas for the correction of the forecast code in stationary mode and in dynamics; application (table on 4 sheets) - the results of modeling the operation of the device on a computer when processing a non-stationary random process.

The known prediction operator formulas obtained analytically using approximating polynomials at four points (ordinates) of the buffer history of the input random discrete process using the least squares method (Milne V.E. Numerical analysis. M., IL, 1951, p. 212), in particular, by the approximating polynomial of the second degree (quadratic):

first degree (linear):

4, стр. 573), в частности, для четырех точек имеем:In addition, there are known formulas for numerical differentiation for equally spaced points expressed in terms of the function values at these points (Demidovich B.P. and Maron I.A. Fundamentals of Computational Mathematics. M., "FM", 1960, chap. XV,

4, p. 573), in particular, for four points we have:

where y _p is the first (current) calculated point (ordinate);

for _p-1 , _p-2 , _p-3 , respectively, the second, third, and fourth design points (ordinates) of the three-level buffer for storing the history of the input smoothed discrete sequence. In numerical analysis, this is a system of equally spaced points with a step h, in real time h is the forecast time (depth), and the period of storage of current information in the history memory buffers is three forecast intervals B _t = 3h.

By analogy with the methods of calculating finite differences for numerical differentiation and extrapolation, we denote:

Δy ₁ = (2y _p -y _p-1 ) - as the biodiversity of the first level of the history of the input discrete sequence, i.e. the difference between the doubled current and previous ordinates of the process;

Δy ₂ = (2y _p -y _p-2 ) - biodiversity of the second level of history;

Δy ₃ = (2y _p -y _p-3 ) - the biodiversity of the third level of history.

After transforming equations (1), (2) and (3) with the aim of simplification and taking into account biodiversity, we obtain the following empirical expressions for numerical differentiation formulas and quadratic and linear prediction operators:

The proposed device implements prediction and differentiation operators according to formulas (4), (5) and (6), the main elements of the circuit being an adder and an inverter unit, and multiplying the coefficients by the terms is carried out by the corresponding mounting shifts of the latter buses when entering the adder. Such operations in the flowchart (see Fig. 1) are indicated by a circle.

The device contains (see Fig. 1) a smoothing unit 1, consisting of a multi-channel digital smoothing device 2 on m = 32 series-connected channels (see ed. St. USSR No. 686034, class G06F 15/32, 1979 and No. 748417, 1980), register 3 for setting the degree of smoothing (k) and multiplexer 4, and a prediction block containing three series-connected subtractors 5, 6, and 7, each of which includes a buffer of register memory 8 from (A) series-connected registers 9, multiplexer 10, block of inverters 11 (assuming that the multiplexer does not have inverse moves) and the adder 12; a quadratic prediction calculation subunit 13 comprising a block of inverters 14, a first 15, a second 16 and a third 17 adders, the output of the latter being the output of the subunit; a subunit 18 for calculating a linear forecast from the adder 19, the output buses of which are mountingly shifted one bit to the right (towards the lower digits) are the output of the subunit; an adder 20 averaging the outputs of both prediction subunits 13 and 18; a subunit for calculating the first derivative 21 (y ' _ni ), which includes the first 22, second 23, and third 24 adders; at the output of the last, an evaluation code for the first derivative of the process is set at the (n-1) th calculation point of the history buffer; a subunit 25 of the counting of the process speed increments, containing a circuit 26 for generating the absolute value of the speed (y ' _n-1 ), including (see Fig. 4) a multiplexer 27 and an inverter 28, series-connected registers 29 and 30 (forming a buffer of the history of speed increments process), two comparators 31 and 32, two I 33 and 34 elements, two 4-bit counts 35 and 36 increments of the process speed (increase and decrease), two I 37 and 38 elements, OR 39 element and 40 mode trigger (TG ); forecast dynamics control unit 41, comprising a register 42 for inputting a virtual prediction time setting, input 43 of which is the first control input of the device through which the virtual forecast time h = AT is introduced, where T is the device operation cycle, A is the number (max. address) of registers 9 in the buffer 8 of the process history (H = 4h is the real forecast time), an inverter 44, a counter 45 for the duration (2h) of the operation of the forecast block on the dynamics and the multiplexer 46; the second control input 47 to enter the degree of smoothing (k) SP, information (x _n ) 48 and clock (f _T ) 49 device inputs; channel 50 (see Fig. 2) of the smoothing device 2 consists of an adder 51 and a register 52; the timing unit 53 of the forecast block (see Fig. 3) contains a delay element 54, a trigger 55, a pulse generator 56 (f _g ), an And 57 element, and a shift register 58; the dynamics prediction code correction circuit 59 contains four adders 60, 61, 62, 63 and a multiplexer 64, the output of which is the device output 65, and a stationary prediction code correction sub-block 66 from the adder 67.

To determine the moment of transition from the stationary mode to the dynamics, a subunit 25 of counting the increments of the process speed is used, in which a series of 8 successive increments of growth (or decrease) of the process speed is recorded. The increment is the result of comparing, at each step, the current and previous values of the first derivative of the process at the (n-1) -th calculated point of the history buffer. With the transition to dynamics (TG = 1), the device starts to work not with the full (3h), but with the history buffer truncated by 8 times, i.e. Only current (“fresh”) discrete samples of the input process are involved in the calculation of the forecast code, respectively, the resulting forecast code gives a more accurate picture of the change (increase or decrease) in the input process on the dynamics, but only for the forecast time (depth) h _k reduced by 8 times = h / 8 (conditionally, it can be called technological). This buffer truncation operation can be analytically taken as the piecewise linearization of the nonlinear (quadratic) change in the median of the process (MP) on the dynamics and considered as justification (postulate) in the subsequent derivation of the MP correction formula for quadrupling the forecast time both in dynamics and in stationary mode.

The reduction of the forecast code on the dynamics to the four times increased interval (depth) of the forecast H = 4h is implemented in the forecast code correction scheme 59. A graphical interpretation of the operation algorithm of this circuit, based on the postulate of a linear approximation of the median of the input process, is presented in FIG. 5.

Let ΔK = (Y ^k _{n + 1} -Y ^k _n-3 ) be the correcting forecast difference on the dynamics, h _k = h / 8, h = 8h _k , ΔR4 = Y ^d _{n + 4} -Y ^k _n-3 , then , in accordance with the known aspect ratios in similar triangles, we have:

ΔR ₄ / ΔK = 35h _k / 4h _k ; ΔR ₄ = 8ΔK + ΔK / 2 + ΔK / 4 or

The stationary mode is characterized by a steady or slowly changing MP speed: the quadratic and linear components of the forecast almost coincide, and their averaging in adder 20 makes this estimate statistically more reliable. Reduction of the forecast code in stationary mode to the quadrupled forecast interval H = 4h is implemented in sub-block 66 of the forecast code correction. A graphical interpretation of the operation algorithm of this subunit is presented in FIG. 5, where Δ1 = (Y _{n + 1} -Y _n-3 ) and Δ4 = (Y _{n + 4} -Y _n-3 ) are the correction differences of the forecast in the stationary mode, then by the known relations in similar triangles we have:

Δ4 / Δ1 = 7h / 4h; Δ4 = Δ1 + Δ1 / 2 + Δ1 / 4 or

. Эффективность сглаживания выбирается заданием со входа 47 степени k=0, 1, 2, 3, 4 или 5, которая в свою очередь определяет число задействованных каналов сглаживания m=2^k (1, 2, 4, 8, 16 или 32).The cycle of the device consists of two clock cycles. In the first, the smoothing unit 1 ends, each channel of which implements the exponential smoothing operator

. The smoothing efficiency is selected by setting the input k of degree k = 0, 1, 2, 3, 4, or 5 from input 47, which in turn determines the number of smoothing channels involved m = 2 ^k (1, 2, 4, 8, 16, or 32).

In the second clock cycle 53, the first series of mini-tacts ("a", "b", "c") initiates the work of three subtractors 5, 6, and 7, subunits 13, 18, and 21 of calculation according to formulas (6), (4) and (5) the first derivative, quadratic and linear components of the prediction block. The sum of the codes of the latter is averaged Y _{n + 1} = Y _{n + 1} [SR] = (Y _{n + 1} [KB4] + Y _{n + 1} [LN4]) / 2 in adder 20 and is output to subunit 66 and prediction code correction circuit 59 . The second series of mini-tacts ("d", "e", "f") forms the operation of the subunit 25 for counting the increments of the process speed. The subunit is designed to switch the stationary (TG = 0) mode to the dynamics (TG = 1). The clock signal ("d") in register 30 from register 29 overwrites the previous one at ' _n-1 [(w-1) T], and the last one - the current one at' _n-1 [wT] of the absolute value of the process speed. The subunit can be divided into two parallel channels for counting the number of increments in the process speed: decreasing and increasing. Consider the work of the latter: with a positive ratio A> B (y ' _n-1 [wT]>y' _n-1 [(w-1) T]) in the comparator 31, the clock signal ("e") is fed to the counting input of the increment counter 35 and at the same time resets to “0” the counter 36 of the other channel. The receipt of N _d = 8 or more pulses on the counter 35 in a row means that the process has switched from stationary mode to dynamics. The high level (“1”) of the output of the 4th digit of the counter 35 allows the signal (“f”) to set the mode 40 trigger to “1” (TG = 1) and copy from the register 42 to the counter 45 of the dynamic control unit 41 in the inverse code measures (2h) i.e. device runtime in dynamic mode. The direct output (“1”) of trigger 40 enables the generation of a prediction code Y ^d _{n + 2} on the speaker (already corresponding to an increased forecast time 4h) from adder 63 of the correction scheme 59 of the prediction code through the multiplexer 64 to the output of device 65 and switches the node multiplexer 46 41 control the dynamics of the operation of the forecast block with only 1/8 of the buffer of the process history, respectively, with h _k = h / 8 (technological) interval (time) of the forecast.

The device switches from dynamics to stationary mode by resetting the mode trigger (TG = 0) to “0” by the direct transfer pulse of counter 45 of control unit 41, i.e. only after filling the process history buffer with 66% (2h) with new information in the new mode. Accordingly, the multiplexer 46 switches to outputting a predetermined (virtual) time interval h to the history buffer, and the multiplexer 64 switches to the output of the adjusted forecast code Y _{n + 4} device for the quadruple forecast time H = 4h.

The application table shows the simulation results of the device.

Column No. 5:

ΔP _k = (Y _n [w + 4h] -Y _{n + 4} ) - forecast error with correction on the dynamics (TT = 1),% - forecast accuracy in% (column No. 6);

Column number 8:

ΔР = (Y _n [w + 4h] -Y _{n + 4} [SR]) - forecast error without correction on the dynamics. % - forecast accuracy in% (column No. 9);

The implementation of the linearization equations (7) and (8) in the scheme and subunit of the correction of the forecast code, respectively, allowed to increase the real time (depth) of the forecast by four times, without increasing the memory buffer of the history of the input process (B _t = 3h) and damage to the accuracy of the forecast .

Columns 11 and 12 show the data (row numbers w = 553 ÷ 598) for the error and accuracy for the quadruple forecast time in stationary mode:

ΔP _H = Y _n [w + 4h] -Y ^SH _{n + 4} ,

where Y ^SH _{n + 4} is the averaged code of the quadratic [KB4] and linear [KB4] forecast components calculated using analytical formulas (4) and (5), i.e. for a history memory buffer of size B _t = 3H = 12h. The forecast result is identical for both cases.

application

Claims (1)

A digital predictive device, which includes a smoothing unit containing m = 32 series-connected channels, and the input of the first channel is the information input (x _p ) of the device, the register and the multiplexer, the outputs of each m = 1, 2, 4, 8, 16 and 32 channels of the unit are connected to the information inputs of a multiplexer, the address input of which is connected to the register output, the input of the latter is connected to the second control input of the device to set the degree (efficiency) of smoothing k = 0, 1, 2, 3, 4, or 5 (m = 2 ^k ), and the output (y _p ) of the multiplexer in input to the first subtractor of the prediction block, and a forecast block containing the first, second and third subtracters, each of which includes a register memory buffer, multiplexer, inverter block and adder; a quadratic prediction calculation subunit containing three adders and an inverter; the output of the third adder is the output of the subunit; a sub-block for calculating a linear forecast from one adder, the output buses of which are mountingly shifted (to the right) by one bit towards the lower digits and are the output of the sub-block; a prediction dynamics control unit comprising a prediction time setting input register, the input of which is the first control input of the device defining a forecast interval, an inverter, a counter and a multiplexer, the output buses of the prediction time setting input register being connected directly to the first input of the multiplexer shifted to the mounting right three digits - to the second input of the multiplexer and, mountingly shifted to the left by one digit, through the inverter, - to the counter input, the multiplexer output is connected to the address inputs of the mul ipleksorov all three subtractors; a subunit of calculating the first derivative, which includes three adders, the output of the latter is the output of the subunit with the code of the first derivative (y ' _n-1 ) at the (n-1) -th calculation point of the input history buffer; a timing unit of a forecast block comprising a delay element, a trigger, a pulse generator, an AND element, and a shift register; adder averaging discrete outputs of sub-blocks of quadratic and linear forecasts; a dynamic prediction code correction scheme containing four adders and a multiplexer; stationary correction code prediction correction sub-unit, comprising an adder; a subunit for counting process speed increments containing a scheme for generating the absolute value of the first derivative (y ' _n-1 ), two series-connected storage registers for the current y' _n-1 [(wT)] and the previous y ' _n-1 [(w-1) T)] process speed discrete, two parallel channels (for increasing and decreasing) for counting process speed increments, each of which includes a comparator, two And elements and a four-digit increment counter, an OR element and a mode trigger, with the output of the first And element in each the channel is connected to the counter input of the counter and and the reset bus to “0” of the counter of another channel, the output of the OR element is connected to the input of the setting in “1” of the mode trigger and to the write bus of the counter of the forecast dynamics control unit, and the direct transfer output of this counter is connected to the reset bus to “0” of the trigger, direct ("1") output of which is connected to the address inputs of the multiplexers of the dynamics control unit and the correction scheme for the forecast code for the dynamics, the output of the first derivative calculation subunit through the absolute value generation circuit is connected to the input of the first register of the sub-block openings, and the outputs of both registers are connected, respectively, to the inputs of the comparators of both channels, characterized in that in the correction scheme of the prediction code on the dynamics of the bus of the first input of the first adder, the montage is shifted to the right by one bit (towards the lower digits), connected to the output of the adder averaging, the second input of the first adder is connected to the inverter output of the third subtractor, the output buses of the first adder, mountingly shifted to the right by one bit, and mountingly shifted to the right by two digits, are connected, respectively, to the first and second inputs of the second adder, the output of which is connected to the first input of the third adder, the second input of which is connected to the output busbars of the first adder, three-left shifted, the output of the third adder is connected to the first input of the fourth adder, the second input of which is connected to the output the multiplexer of the third subtractor, the output of the fourth adder is connected to the second information input of the multiplexer of the prediction code correction circuit, and the first input of the adder of the prediction code correction subunit the ionic mode is connected to the output buses of the averaging adder, mounted one-bit to the right, the second input of the adder of the prediction code correction subunit is connected to the output of the second adder of the prediction code correction circuit on the speaker, the output of the subunit adder is connected to the first information input of the correction circuit multiplexer, and the multiplexer output is the output of the device.

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