RU2450343C1 - Digital predicting and differentiating device - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: digital predicting and differentiating device includes a unit for estimating first derivatives, having a subunit for calculating a first derivative at a second (n-1)-th reference point of process history consisting of three adders, the output of which is the third data output of the device, and a subunit for calculating a first derivative at the third (n-2)-th reference point of the process history consisting of three adders and a block of inverters, the output of the subunit being the fourth data output of the device.

EFFECT: broader functional capabilities of prediction devices by obtaining estimations of first derivatives using numerical differentiation formulae for prehistory nodes of an input smoothed discrete sequence.

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Description

The invention relates to automation and computer technology and can be used to predict stationary and non-stationary random processes, improve the quality and accuracy of control in digital control systems and guidance of various (including ballistic) objects.

A device for adaptive extrapolation according to auth. No. 1572281 (USSR Author's Certificate No. 1572281, class G06F 15/353, 1988), which contains a smoothing unit, an extrapolation unit, which includes three subtractors, and an evaluation unit for the first derivative. The latter gives an approximate value of the first derivative at the current time, i.e. in the first (n) -th of the four design points (nodes) of the history of the extrapolated (predicted) process, however, according to the formula intended for the third (n-2) -th design point (Demidovich B.P. and Maron I.A. Basics Computational Mathematics. M., “FM”, 1960, chap. XV, §4, p. 573). In addition, the predicted y _{n + 1} process value is used in the formula for numerical differentiation given in the above analogue, i.e. the value that "... will take place in the future, and it cannot be used to determine the unknown parameters of the model" (Chuev Yu.V. Prediction of quantitative characteristics of processes. M., "SR", 1975, p. 254).

The closest in technical essence to the claimed device is a digital predictive device selected as a prototype according to application No. 20111101014/08 (001268) dated 12.01.2011, containing a smoothing unit, a clock unit and a forecast unit that contains three subtractors, a time register (interval) forecast and two sub-blocks: quadratic and linear forecasts. This device is functionally limited. The technical problem for the proposed device is to expand the functionality by obtaining estimates of the first derivatives according to numerical differentiation formulas for equally spaced points (nodes) of the history of the input smoothed discrete sequence.

Therefore, the digital predictive device according to the application No. 201101014/08 (001268) dated 01/12/2011, which includes: a smoothing unit according to the application No.2010125733 / 20 (036608) dated 06/23/2010, containing the adder, the first and second reversible counters, a single-channel smoothing subunit from a series-connected adder and a register, a deviation ratio setting subunit containing a register, a counter and a delay element, a real deviation subunit containing an inverter unit, two comparator units and an I element, a unit increment unit containing two e And ementa and an inverter subunit dynamic characteristic control containing two pulses driver, an OR gate, a counter, two AND gates and the trigger mode, a smoothing information output unit information, the first control inputs and the timing device; a timing unit of a forecast block comprising a delay element, a trigger, a pulse generator, an AND element, and a shift register; a prediction block comprising first, second and third subtracters, each of which contains a register memory block, a multiplexer, an inverter block and an adder, a quadratic prediction block containing three adders and an inverter block, the subblock output being the first information output of the device, the linear prediction subblock from one adder, the output of which is the second information output of the device, the register of ordinates (calculated points) of the history of the input process, the input of which is the second control input m of the device that sets the forecast time (interval), to solve the problem, a unit for estimating the first derivatives is introduced, containing a subunit for calculating the first derivative at the second (n-1) -th calculation point in the history of the input process of three adders, in which the input of the first term of the first adder connected to the output of the first subtracter, the input of the second term of this adder is connected to the output of the multiplexer of the third subtracter, the input of the first term of the second adder is connected to the output of the first adder, and with the busbar mounting offset by one bit in the direction of the least significant bits, the input of the second term of the second adder is connected to the output of the second subtracter, the input of the first term of the third adder is connected to the output of the inverter unit of the second subtractor, and with the busbar mounting one bit to the higher bits of the adder, the input of the second term of this adder - with the output of the second adder, and the output of the third adder is the output of the subunit and the third information output of the device for evaluating the first derivative in the second (n-1) -th design point of the previous process theory, and the subunit of calculating the first derivative at the third (n-2) -th calculation point of the process history of three adders and an inverter block, in which the input of the first term of the first adder is connected to the output of the third subtractor, the input of the second term of this adder is to the output of the second a subtractor, and with the busbar mounting offset by one bit toward the lower bits of the adder, the input of the first term of the second adder is connected to the output of the multiplexer of the second subtractor, the input of the second term of this adder is connected with information the output of the smoothing unit, with the busbar shifting one bit toward the lower digits of the adder, and the output of the second adder through the inverter unit is connected to the input of the second term of the third adder, the input of the first term of which is connected to the output of the first adder, and the output of the third adder is the output subunit and the fourth information output of the device for evaluating the first derivative in the third (n-2) -th calculation point of the process history.

The invention is illustrated by drawings, which depict: in Fig.1 - a block diagram of the proposed device; figure 2 is a block diagram of a smoothing unit; figure 3 is a block diagram of a single-channel anti-aliasing subunit; Fig. 4 is a block diagram of a timing unit of a forecast block; figure 5 is a block diagram of a forecast block and an evaluation unit of the first derivatives.

The device implements modified quadratic [КВ4] and linear [ЛН4] prediction operators obtained using approximating polynomials at four points (nodes) of the ordinates of the prehistory of the input smoothed discrete sequence using the least squares method (Milne V.E. Numerical analysis. M., “IL” , 1951, p. 212):

where Δy ₁ = (2y _n -y _n-1 ) is the biodiversity of the 1st level of the process history;

Δy ₂ = (2y _n-1 -y _n-2 ) - biodiversity of the 2nd level;

Δy ₃ = (2y _n-1 -y _n-3 ) - biodiversity of the 3rd level;

Δy ₄ = (2y _n-2 -y _n-3 ) - additional biodiversity of the 3rd level;

y _n , y _n-1 , y _n-2 , y _n-3 - the first, second, third and fourth design points (nodes) of the ordinates of the three-level background of the input random smoothed discrete process.

The methods for calculating finite differences for numerical differentiation and interpolation (extrapolation) are based on a system of equally spaced nodes with a step h, in this case, the ordinate system (calculated points) in the time continuum of the three-level history of the input discrete sequence, where h is already the interval between the ordinates (points) , respectively, the time (depth) of the forecast.

Known formulas for numerical differentiation for equally spaced points expressed in terms of the function values at these points (Demidovich BP and Maron IA Fundamentals of Computational Mathematics. Moscow, FM, 1960, chap. XV §4, p. 573) , in particular, for four points we have:

The table below shows the correspondence of the numbering of calculated points (nodes) to the history of the numbering of points in the original source.

Historical Settlement Point Number four 3 2 one y _ni y _n-3 y _n-2 y _n-1 y _n y _{n + 1} y _i y ₀ y ₁ y ₂ Y ₃

In order to simplify, we modify (transform) formulas (3), (4), (5) and (6):

Taking into account biodiversity, the resulting expressions are rewritten in the following form:

As can be seen from the obtained modified differentiation formulas, the adder and the inverter unit become the main typical elements during their implementation, and the multiplication of the coefficients by the terms is carried out by the corresponding mounting shifts of the latter buses when entering the adder. Such operations on the block diagram (see figure 5) are indicated by a circle.

The table below shows the hardware costs for the implementation of formulas (11), (12), (13) and (14), where ∑ → adder, inv. → inverter unit:

First derivatives y ' _n y ' _n-1 y ' _n-2 y ' _n-3 Hardware implementation costs 5∑ + inv. З∑ 3∑ + inv. 5∑ + inv.

Obviously, the optimal implementation is advisable for two points: the (n-1) -th and (n-2) -th, in addition, the derivatives at these points (nodes) have a minimum differentiation error (see ibid., P. 573) :

r _{n-1, n-2} = [h ^3/12] y ^{(4) (ξ).}

The device contains (see Fig. 1) a smoothing unit 1, a prediction unit 2, and an estimation unit for the first derivatives 3. The smoothing unit 1 contains (see Fig. 2) an adder 4, a subunit 5 of actual deviations, containing an inverter unit 6, two comparator units 7.1 and 7.2 and the And 8 element, the first reversible counter 9, the subunit 10 for setting the deviation ratio containing the register 11, the counter 12 and the delay element 13, the unit of increments 14 subunit containing the inverter 15 and two And 16.1 and 16.2 elements, the second reversible counter 17 , subunit 18 of the dynamic characteristic control, sod holding two pulse shapers 19.1 and 19.2, an OR element 20, a counter 21, two And 22.1 and 22.2 elements and a mode 23 trigger; information input 24 of the smoothing unit and the device, the first control 25 and clocking 26 inputs of the device and the smoothing unit; single-channel anti-aliasing subunit 27 (see Fig. 3), comprising adder 28 and register 29 connected in series; information output 30. The timing unit 31 of the forecast block contains (see FIG. 4) a delay element 32, a trigger 33, a pulse generator 34, an And 35 element and a shift register 36. Prediction block 2 (see FIG. 5) contains the first 37, the second 38 and third 39 subtractors, each of which contains a block of register memory 40 from (A) series-connected registers 41, a multiplexer 42, a block of inverters 43 (assuming that the multiplexer does not have inverse outputs) and an adder 44; the first prediction subunit 45 containing the inverters 46, the first 47, the second 48 and the third 49 adders, the output 50 of the third adder of the subunit is the first information output of the device; the second subunit 51, comprising an adder 52, the output of which is connected to the second information output 53 of the device; register 54 of the address (A) ordinate of the calculated points of the history of the predicted process, input 55 of which is the second control input of the device that sets the forecast time H = AT (T is the cycle of the device, A is the maximum register (block) address of the register memory block 40). The first derivative evaluation unit 3 contains a subunit 56 for calculating the first derivative at the second (n-1) th calculation point of the process history, which includes the first 57, second 58 and third 59 adders, the output 60 of the latter is the third information output of the device, and the subunit 61 calculation of the first derivative in the third (n-2) -th calculation point of the process history, containing the first 62, second 63, inverter block 64 and third 65 adders, output 66 of which is the fourth information output of the device. The cycle of the device consists of 4 cycles.

The smoothing unit 1 operates in two modes: stationary and dynamic (transitional), and all operations are performed in one 1st cycle. In stationary mode, the unit smooths the input random discrete process, the deterministic basis (median) of which can have constant, linear or non-linear (quadratic) characters of change over time. Transient (dynamic) mode can be caused by acceleration, bend, transition from one stationary mode to another, etc., i.e. an almost abrupt change in the process.

The smoothing unit 1 (see figure 2) implements the following modification of the operator of signature exponential smoothing:

where x _n and y _n are the input and output discrete;

α = 1 / K is the smoothing parameter, K is the adaptation parameter;

Δx _n = (x _n -y _n-1 ) - current deviations from the median of the process.

As a criterion for the effectiveness (accuracy) of smoothing, the ratio d between zero and actual deviations Δx _{n is} chosen. The latter form the current unit increments of both signs of the output discretes in accordance with the signature function in (15):

sign [Δx _n / K] = 0 for [Δx _n -K] <0 (Δx _n are zero deviations),

sign [Δx _n / K] = 1 for [Δx _n -K]> 0 (Δx _n are the actual deviations).

In stationary mode (D = 0 - a sign of mode), block 1 smoothes the input random sequence of discretes to a level specified by the relation d (real range d = 7 ÷ 190), which is entered before starting the device from input 25 to register 11 of subunit 10 of the ratio deviations. The latter is a controllable frequency divider, for example, at d = 7, the output of the direct transfer of counter 12 is every seventh clock pulse from input 26, which, through delay element 13, overwrites the inverse code d from register 11 to counter 12 (for the next divider cycle) and subtracts “1” from the first reverse counter 9 containing the adaptation parameter code K. The adaptive smoothing process is as follows. Let (for a certain code K in counter 9), the variance of the input discrete process increase, i.e. the number of actual deviations Δx _n (of both signs) increased. After comparing them with the adaptation parameter K at the output of the comparator blocks 7.1 and 7.2 of the subunit 5 (playing the role of negative feedback), logical “1” is set (the mode of operation of the comparators: [Δx _n > K] = “1”, [Δx _n <K] = "0") received at the input of element And 8. Since in the stationary mode the trigger of mode 23 is in the state "0" (D = 0), then from its inverse output to the first input of element And 8 of subunit 5, a logical "one". A high level of the signal at all inputs of the And 8 element allows the passage of clock pulses from input 26 to the summing input of the first reverse counter 9 (the K code in the last increases) and to the second inputs of the And 16.1 and 16.2 elements of the subunit of unit increments 14. The signal from the output of one of them (depending on the sign of the deviation) is fed to the summing (or subtracting) input of the second reverse counter 17 of the smoothing result, i.e. the signature function (15) is realized. The growth process of K will lead to a decrease in the number of actual deviations and will continue until a dynamic equilibrium sets in, i.e. the number of pulses received from the subunit 10 to the subtracting input of the counter 9 will be equal to the number of pulses received at its summing input from the subunit 5, and the variance of the output smoothed discrete sequence will remain unchanged (for d = 7: there must be seven zero deviations for one real deviation) .

For smoothing the input sequence of discrete transient (dynamic) mode (D = 1) is used a single-channel smoothing subunit 27 (see Figure 3.), Which implements the following exponential smoothing operator: y _n = _^1/2 (x _n + y _n-1 ), i.e. with a minimum degree of smoothing and, accordingly, with a minimum phase shift (delay) of the output discrete. Subunit 27 operates in both modes, is initiated by clock pulses from input 26 in register 29, but is used only in transition (dynamic) mode.

For a stationary random process, the probability of a series, for example, of m = 8 (eight) deviations from the median (deterministic basis) of a single sign in a row, in accordance with the geometric law of probability distribution, is:

P (x = m) = ^{_(1/2) m} = 1 / 256≈0,004,

those. so small that the appearance of such a series can be considered the beginning of a transitional regime. Subunit 18 captures such a series and works as follows. Since for the stationary mode the deviations of different signs are most likely, when the sign in the adder 4 changes from “plus” to “minus” and vice versa, the pulse shapers 19.1 or 19.2 are triggered and through the element OR 20 they reset counter 21 and trigger 23 to “0” (D = 0). In the dynamic mode (the shapers 19 do not work), the counter 21 (for example, 4-bit) will certainly receive eight pulses in a row from the clock input 26. At the output of the high-order bit of the counter 21, a logical “1” will be set, the high signal level of which will ensure passage through the first element And 22.1 clock pulse, which sets the trigger mode 23 in "1" (D = 1). The last signal from the inverse output will block the operation of the subunit 5 of the actual deviations and, accordingly, the subunit of 14 unit increments, and by the high level of the direct output signal it will allow the discretization from the single-channel smoothing subunit 27 to the second reversal counter 17 of the smoothing result through the second element And 22.2. At the end of the transition mode, in the adder 4, deviations of different signs will inevitably occur, which will lead to the operation of the pulse shapers 19 and, accordingly, to the switching of the trigger of mode 23 to the state “0” (stationary smoothing mode, D = 0).

Prediction and differentiation operations are performed in three cycles, respectively, 2nd, 3rd and 4th. They are formed by a series of three clock pulses from the clock node 31 (see figure 4). A clock pulse from input 26 zeroes trigger 33 and writes “1” to the least significant bit of the shift register 36. The same clock pulse, delayed by delay element 32, sets trigger 33 to “1”, thereby allowing pulses from generator 34 to pass through element I 35 into shift register 36, on the low-order tires of which (“a”, “b”, “c”, etc.) the above series appears. In the 2nd step, the ordinate of the current (first) calculated point y _n is recorded in the first register 41 of the block 40 of the register memory of the first subtractor 37. At the same time, all previous ordinates are rewritten (shifted) to neighboring registers 41. The address code is supplied to the address input of multiplexer 42 (A) the ordinates of the history from the register 54, recorded from the second control input 55 before starting the operation of the device and determining the time (interval) of the forecast Н = AT. In accordance with this address, the ordinate from the output of the multiplexer 42 (already as the second calculation point y _n-1 ) through the inverter block 43 is fed to the input of the second term of the adder 44, the first term of which is doubled the ordinate of the previous calculation point y _n . The output of the adder of the first subtractor 37 establishes the biodiversity of the 1st level of the history of the input discrete sequence.

In the 3rd and 4th steps, operations are performed similar to those described above, but already for the second 38 and third 39 subtracters, the outputs of which are set, respectively, biodities of the 2nd and 3rd levels of history. All adders in the device are combination. At the end of the 4th cycle, at the output 50 of the subunit 45, in accordance with the empirical formula (1), the quadratic (nonlinear) prediction code for the non-stationary input discrete sequence is set, at the output 53 of the subunit 51, in accordance with formula (2), the linear prediction estimation code for a stationary or slowly changing input discrete sequence, the output 60 of subunit 56 in accordance with formula (12) is the code for evaluating the first derivative at the second (n-1) -th calculation point of the process history, and at the output 66 of subunit 61, in accordance etstvii of formula (13) - the first derivative estimation code in the third (n-2) th point calculation process history.

The introduction into the device of subunits for calculating the first derivatives at the second (n-1) -th and third (n-2) -th settlement points of the history (i.e., separated in time) significantly expands the functionality and scope of the device, makes it possible to analyze the nature (trend) changes in the parameters of the predicted process (growth - decrease, acceleration - deceleration, etc.), evaluate its intensity (for example, the gradient of temperature, pressure, etc. fields), which improves the quality of control of especially fast-dynamic objects using well known PID controllers.

Claims (1)

A digital predictive and differentiating device, which includes: a smoothing unit containing an adder, first and second reversible counters, a single-channel smoothing subunit from a series-connected adder and register, a deviation ratio setting subunit containing a register, counter and delay element, a valid deviation subunit, containing a block of inverters, two blocks of comparators and an element And, a subunit of unit increments, containing two elements And and an inverter, a subunit of control of a dynamic nature eristikoy containing two of the pulse, an OR gate, a counter, two AND gates and the trigger mode, a smoothing information output unit information, the first control inputs and the timing device; a timing unit of a forecast block comprising a delay element, a trigger, a pulse generator, an AND element, and a shift register; a prediction block comprising first, second and third subtracters, each of which contains a register memory block, a multiplexer, an inverter block and an adder, a quadratic prediction block containing three adders and an inverter block, the subblock output being the first information output of the device, the linear prediction subblock from one adder, the output of which is the second information output of the device, the register of ordinates (calculated points) of the history of the input process, the input of which is the second control input m of a device that sets the forecast time (interval), characterized in that the first derivatives estimation block is introduced into it, which contains a sub-block for calculating the first derivative at the second (n-1) -th calculation point in the history of the input process of three adders, in which the input of the first term the first adder is connected to the output of the first subtracter, the input of the second term of this adder is connected to the output of the multiplexer of the third subtracter, the input of the first term of the second adder is connected to the output of the first adder, and with the busbar mounting offset by one the discharge toward the lower digits, the input of the second term of the second adder is connected to the output of the second subtracter, the input of the first term of the third adder is connected to the output of the inverter unit of the second subtractor, and with the busbar mounting by one digit toward the higher digits of the adder, the input of the second term of this adder is with the output of the second adder, and the output of the third adder is the output of the subunit and the third information output of the device for evaluating the first derivative at the second (n-1) th calculation point of both the process and the subunit of calculating the first derivative in the third (n-2) th calculation point of the process history of three adders and the inverter block, in which the input of the first term of the first adder is connected to the output of the third subtractor, the input of the second term of this adder is to the output of the second a subtractor, moreover, with the busbar mounting offset by one bit toward the lower bits of the adder, the input of the first term of the second adder is connected to the output of the multiplexer of the second subtractor, the input of the second term of this adder is informational m is the output of the smoothing unit, with the busbar mounting offset by one bit toward the lower bits of the adder, and the output of the second adder through the inverter unit is connected to the input of the second term of the third adder, the input of the first term of which is connected to the output of the first adder, and the output of the third adder is the output subunit and the fourth information output of the device for evaluating the first derivative in the third (n-2) -th calculation point of the process history.

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