RU2262191C1 - Code transformer - Google Patents

Abstract

FIELD: computer science.

SUBSTANCE: device realizes transformation of input self-synchronization pulse series, not requiring additional forming of sign of start of information packet due to conversion of code with necessary change of level at the beginning of each bit interval, while logical zero with lesser length and one with greater length of bit range during this range take on high or low signal level. Code converter has device for forming pulses by front and cut 1, information input 2 and output 3, decimal divider-counter 4, counter 5, clock input 6 and output 7.

EFFECT: broader functional capabilities.

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Description

The invention relates to computer technology and can be used in digital information transmission systems.

The known code converter (see USSR AS No. 1236615 of 04.25.84, MKI: N 03 M 5/12, "Decoder", A.B. Burchenko, V. N. Stepanov, V. D. Trishkin and A .A. Yakovlev, publ. 07.06.86, bull. No. 21), containing the first and second D-flip-flops, delay element, element NOT, the output of which is connected to the synchronization input of the second D-trigger, the zero input of which is connected to the output delay element, RS-trigger and AND element, the output of which is connected to the input of the delay element, the output of which is the synchronization output of the device and connected to the zero input of the first D-trigger, stroke synchronization is combined with an input member and a NOT input device, inverse output of each D-flip-flop is connected to the data input of another D-latch, to the corresponding input AND gate and the corresponding RS-trigger input, whose output is the data output device.

A disadvantage of the known code converter is the complexity of the circuit due to the presence of a large number of connections between elements.

The closest set of essential features to the claimed invention is a code converter (see the article by V.P. Klimov, I.M.Kazanova, I.L.Vishnyakova "Structures of decoding devices of optical channels" in the collection of articles "Electronic Engineering in Automation", edited by Yu.I. Konev, issue 17. - M .: Radio and communications, 1985, p. 259, Fig. 3, d), containing a pulse shaper along the front and a cut (transition shaper), the input of which is connected with the information inputs of the device and the D-trigger, the output of which is connected to the information output of the device triples, clock input - with the output of the counting trigger. The inverse output of the counting trigger is connected to the input of the delay element, the output of which is connected to the inverse input of the reset of the counting trigger, the clock input of which is connected to the output of the pulse shaper along the front and the cut (transition shaper).

A disadvantage of the known code converter is the need to form a sign of the beginning of the information package, providing mutual synchronization of the receiver and transmitter and reliable transmission of messages due to the use of phase-shifted code as the input code of the converter.

The task to which the claimed invention is directed is to create a code converter with advanced functionality, namely: converting an input self-synchronizing pulse sequence that does not require additional formation of a sign of the beginning of an information message.

The technical result, which consists in expanding the functionality, is achieved by the fact that a decimal counter-divider and a counter are introduced into the code converter containing a pulse shaper along the front and a slice, the input of which is connected to the information input of the device, and the information output of the device, the clock inputs of which are combined and are the clock input of the device, while the first output of the decimal counter-divider is the clock output of the device, the second output is connected to the R-input of the counter, and the third output connected to the inverse control input of the decimal counter-divider and the control input of the counter, the output of which is the information output of the device, the output of the pulse shaper along the edge and slice is connected to the R-input of the decimal counter-divider.

The specified set of features allows you to expand the functionality of the code converter, namely: to ensure the conversion of the input self-synchronizing pulse sequence, which does not require additional formation of the sign of the beginning of the information packet, through the use of a code characterized by a mandatory level change at the beginning of each bit interval, logical "0" and logical "1" take a high or low signal level for the duration of the bit interval, while the duration of the bit interval All logical “0” is less than the duration of the bit interval of the logical “1”.

The drawing shows a circuit diagram of a code converter.

The code converter contains (see the drawing) a pulse shaper 1 along the edge and slice, an information input 2, information output 3, a decimal counter-divider 4, counter 5, clock input 6 and clock output 7. The input of the pulse shaper 1 along the edge and slice is connected with information input 2 devices. The clock inputs of the decimal counter divider 4 and counter 5 are combined and are the clock input 6 of the device. The first output of the decimal counter-divider 4 is the clock output 7 of the device, the second output is connected to the R-input of the counter 5, and the third output is connected to the inverse control input of the decimal counter-divider 4 and the control input of the counter 5. The output of the counter 5 is the information output 3 of the device . The output of the pulse shaper 1 along the edge and slice is connected to the R-input of the decimal counter-divider 4.

Shaper 1 pulses along the front and cut can be performed according to the scheme presented in the book Shilo V.L. Popular digital circuits. Directory. - M.: Radio and Communications, 1987, p. 58, Fig. 1.37a.

The code converter works as follows. In the initial state, at the information input 2, information output 3, clock input 6 and clock output 7 there is a logic level of "0". Counters 4 and 5 are in a logical "0" state. Clock input 6 receives clock pulses. On the edges of the pulses arriving at clock input 6, the counter 4 is switched. On the front of the third pulse arriving at clock input 6, at the third output of counter 4, the logic level is set to “1”, which goes to the inverse control input of counter 4, prohibiting its switching , and to the control input of the counter 5, allowing its switching. On the edges of the pulses arriving at clock input 6, the counter 5 is switched. The converter is ready for code conversion. Information input 2 receives the information package, and one pulse interval of the information package corresponding to logical "1" has six pulses at the clock input 6, and one bit interval of the information package corresponding to the logical "0" has two pulses at the clock input 6. Upon arrival at the information input 2 of the information package at the output of the pulse shaper 1 along the edge and slice, a pulse is generated that goes to the R-input of the counter 4 and sets it to zero. At the third output of counter 4, the logic level is set to “0”, which is fed to the inverse control input of counter 4, allowing it to switch, and to the control input of counter 5, prohibiting its switching. On the edges of the pulses arriving at clock input 6, the counter 4 is switched. On the front of the first pulse arriving at clock input 6, at the first output of counter 4 and, respectively, at clock output 7, the logic level is set to “1” to interrogate the state of counter 5. When In the process of converting the first bit of the information package, the state of the counter 5 can be any, and the pulse generated at the clock output 7 can be used as a sign of the beginning of the information package. In the process of converting subsequent bits of the information packet, the state of the counter 5 corresponds to the previous converted bit of the information packet. On the front of the second pulse arriving at clock input 6, at the second output of counter 4, the logic level is set to “1”, which is fed to the R-input of counter 5, setting it to zero. If the current converted bit of the information packet corresponds to logical "1", then on the edge of the third pulse received at clock input 6, at the third output of counter 4, the logic level is set to "1", which goes to the inverse control input of counter 4, prohibiting its switching, and to the control input of the counter 5, allowing it to be switched, and on the edges of the pulses arriving at clock input 6, the counter 5 is switched so that until the conversion of the current bit of the information packet at the output of the counter and 5 respectively, and the information output 3 logicheskogoy established level "1". Conversion of subsequent bits of the information packet is carried out similarly.

To convert the next information package, it is necessary to apply it to information input 2. It should be noted that the number of bits in the information package is odd.

A laboratory model of the code converter was made, tests of which confirmed the feasibility and practical value of the claimed object.

Claims (1)

A code converter containing a pulse generator along the edge and a slice, the input of which is connected to the information input of the device, and the information output of the device, characterized in that a decimal counter-divider and a counter are introduced, the clock inputs of which are combined and are the clock input of the device, with the first output the decimal counter-divider is the clock output of the device, the second output is connected to the R-input of the counter, and the third output is connected to the inverse control input of the decimal counter-divider the counter input, the output of which is the information output of the device, the output of the pulse shaper along the edge and slice is connected to the R-input of the decimal counter-divider.