RU2258304C1 - Code converter - Google Patents

Abstract

FIELD: computer science.

SUBSTANCE: device has T-triggers 1,3,9,10, register 5, XOR element 6, OR-Not element 7, counter 8, front pulse generator 11, RS trigger 12, clock input 2, a group of information inputs 13, launch inputs 14, information output 4.

EFFECT: broader functional capabilities.

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Description

The invention relates to computer technology and can be used in digital information transmission systems.

Known code converter (see AS USSR No. 1332536 dated 03/07/86, MKI: H 03 M 5/12, "Code Converter", IV Keltuyala, publ. 23.08.87, Bull. No. 31), comprising a pulse generator, the direct output of which is connected to the second inputs of the first and second elements AND, the element is NOT, the output of which is connected to the first input of the second element And, a trigger, the output of which is the output of the converter. The first input of the first AND element is combined with the input of the element NOT and is the input of the converter. The trigger D-input is connected to the output of the element NOT. The outputs of the first and second elements And and the inverse output of the pulse generator are connected, respectively, with the S-, R- and C-inputs of the trigger.

A disadvantage of the known code converter is the low speed due to the low conversion speed.

The closest set of essential features to the claimed invention is a code converter (see the article by V.P. Klimov, I.M. Casanova, I.L. Vishnyakova ″ Optical channel encoders ″ in the collection of articles Electronic Engineering in Automation ’, under Edited by Yu.I. Konev, Issue 16. - M .: Radio and Communications, 1985, p.263, Fig. 5, a) containing an inverter, the input of which is the clock input of the converter and connected to the clock input of the first trigger and input selection of the multiplexer, and the output is connected to the clock input of the second trigger. The information input of the first trigger is the information input of the converter, and the output is connected to the first input of the multiplexer and the information input of the second trigger, the inverse output of which is connected to the second input of the multiplexer, the output of which is the output of the converter.

The disadvantages of the known code Converter are:

- the difficulty of highlighting the moment the beginning of the receipt of useful information due to the constant formation of a sequence of pulses at the output of the converter in standby mode;

- the lack of the possibility of forming at the output of the code converter information packets of a certain length due to the absence in the converter code circuit of the device that sets the number of bits in the output information packet;

- the need to form a sign of the beginning of the information package, providing mutual synchronization of the receiver and the transmitter and reliable transmission of messages due to the use of phase-shifted code as the output code of the converter.

The task to which the claimed invention is directed is to create a code converter having advanced functionality, namely: generating a logical "0" signal in the output of the converter in standby mode, generating information packets of a certain length at the converter output, forming a self-synchronizing pulse sequence at the output , which does not require additional formation of the sign of the beginning of the information package.

The technical result, which consists in expanding the functionality, is achieved by the fact that a code, an EXCLUSIVE OR element, an OR-NOT element, a divider counter are entered into the code converter containing the first trigger, the clock input of which is connected to the clock input of the converter, the second trigger and output , the third and fourth triggers, a front-end pulse shaper, RS-trigger, a group of information inputs and a start input, the first, second, third and fourth triggers are made in the form of T-triggers with R-inputs, while the R-input of the first T- The trigger is connected to the inverse output of the RS-trigger and the R-inputs of the divider counter and the second T-trigger, and the output is connected to the first inputs of the EXCLUSIVE OR element and the OR-NOT element, the output of which is connected to the pulse former input and the second input with the output of the register, the information inputs of which are connected to the corresponding inputs of the group of information inputs of the converter, the serial input is with a common bus, the parallel boot enable input is with the start of the converter and the S-input of the RS-trigger, and the clock input is with a clock the inputs of the counter-divider and the second T-trigger, the output of the fourth T-trigger and the second input of the EXCLUSIVE OR element, the output of which is connected to the clock input of the third T-trigger, the R-input of which is connected to the output of the pulse shaper along the front and R-input of the fourth T-flip-flop, and the output with the clock input of the fourth T-flip-flop, the output of the divider counter is connected to the R-input of the RS-flip-flop, the output of the second T-flip-flop is connected to the output of the converter.

The specified set of features allows you to expand the functionality of the code Converter, namely:

- to ensure the formation of the output of the logical signal converter ″ 0 ″ in standby mode by blocking the operation of the converter in standby mode;

- to ensure the formation at the output of the converter of information packages of a certain length by setting the number of bits in the output information package;

- to ensure the formation at the output of a self-synchronizing pulse sequence that does not require additional formation of the sign of the beginning of the information packet by using a code characterized by a mandatory level change at the beginning of each bit interval, the logical ″ 0 ″ and logical ″ 1 ″ take a high or low level for the time of the bit interval signal, while the duration of the bit interval of the logical ″ 0 ″ is less than the duration of the bit interval of the logical ″ 1 ″.

Figure 1 shows a circuit diagram of a code converter; figure 2 is a timing diagram of the operation of the code Converter. The code converter contains (see Fig. 1) the first trigger 1, clock input 2, the second trigger 3, output 4, register 5, element 6 EXCLUSIVE OR, element 7 OR NOT, counter divider 8, third 9 and fourth 10 triggers , a front pulse shaper 11, an RS trigger 12, a group 13 of information inputs and a start input 14. The first 1, second 3, third 9 and fourth 10 triggers are made in the form of T-triggers with R-inputs. The clock input of the first T-flip-flop 1 is connected to the clock input 2 of the converter, and the R-input is connected to the inverse output of the RS-flip-flop 12 and the R-inputs of the counter-divider 8 and the second T-flip-flop 3. The output of the first T-flip-flop 1 is connected to the first the inputs of element 6 are EXCLUSIVE OR and element 7 is OR NOT. The output of the item. 7 OR NOT connected to the input of the pulse shaper 11 on the front, and the second input to the output of the register 5, the information inputs of which are connected to the corresponding inputs of the group 13 of the information inputs of the converter, the serial input to the common bus, the parallel boot enable input to the start input the converter and the S-input of the RS flip-flop 12, and the clock input - with the clock inputs of the counter-divider 8 and the second T-flip-flop 3, the output of the fourth T-flip-flop 10 and the second input of the element 6 EXCLUSIVE OR. The output of element 6 EXCLUSIVE OR is connected to the clock input of the third T-trigger 9, the R-input of which is connected to the output of the pulse former 11 and the R-input of the fourth T-trigger 10, and the output is connected to the clock input of the fourth T-trigger 10. Output the counter-divider 8 is connected to the R-input of the RS-trigger 12. The output of the second T-trigger 3 is connected to the output of the Converter.

Shaper 11 of the pulse along the front can be performed according to the scheme presented in the book Horowitz P., Hill W. "The art of circuitry: In 3 volumes: T.2." Per. from English - 4th ed., Revised. and add. - M.: Mir, 1993, p. 173, Fig. 8.97a.

The code converter works as follows.

In the initial state, the clock input 2, the inputs of the group 13 information inputs, input 14 start and output 4 of the Converter there is a logical level ″ 0 ″. The first 1, second 3, third 9, fourth 10 T-flip-flops, counter-divider 8 and RS-flip-flop 12 are in a logical ″ 0 ″ state.

The converter is ready for code conversion. The information in binary code is fed to the inputs of the group of 13 inputs: the first bit of the information packet to the first information input of register 5, the second bit to the second information input, etc. Input 2 (see figure 2, a) receives clock pulses. Input 14 start (see figure 2, b) is a pulse with a duration of one to two periods of the clock sequence received at input 2. Register 5 is placed in parallel loading mode. The RS-trigger 12 is set to a single state and at its inverse output the logic level is ″ 0 ″ (see FIG. 2, c), which is fed to the R-inputs of T-flip-flops 1, 3 and counter-divider 8, allowing their switching . With the arrival of the first pulse arriving at input 2, the output of the T-trigger 1 is set to the logical level ″ 1 ″ (see figure 2, e), which through element 6 is fed to the clock input of the T-trigger 9 and switches it to a single state (see figure 2, k). This leads to the fact that the T-trigger 10 switches to a single state (see figure 2, l), putting the element 6 in the mode of inverting the information received at its first input (see figure 2, g). At the output of element 7, the logical level ″ 0 ″ is set (see Fig. 2, h). The T-trigger 3, in turn, switches to a single state and, therefore, at the output 4 of the converter, the logical level is ″ 1 ″ (see Fig. 2, m). A positive difference from the output of the T-flip-flop 10 goes to the clock input of the register 5, recording information from the inputs of the group 13 of the inputs to the register 5 and, accordingly, issuing the output of the register 5 (see figure 2, e) the logical level of the first bit of the information package . Next, the conversion takes place depending on the logical state of the bit of the information packet, and after the end of the pulse received at the start input 14, register 5 is transferred to the left shift information mode.

The logical ″ 1 ″ conversion is as follows. For one bit of information sprinkling, having a logical state ″ 1 ″, there are six pulses at clock input 2. With the arrival of a pulse arriving at input 2, the output of T-trigger 1 is set to a logic level ″ 0 ″, which, inverting with element 6, goes to the clock input of the T-flip-flop 9 and switches it to the zero state. With the arrival of the next pulse arriving at input 2, the logic level ″ 1 ″ is set at the output of the T-trigger 1. With the arrival of the next pulse arriving at input 2, the logic level ″ 0 ″ is established at the output of T-trigger 1, which, inverting with element 6, goes to the clock input of T-trigger 9 and switches it to a single state. This leads to the fact that the T-trigger 10 switches to the zero state, putting the element 6 in the mode of direct transmission of information received at its first input. The negative difference from the output of the T-trigger 10 is supplied to the clock input of the counter-divider 8, by switching it. With the arrival of the next pulse arriving at input 2, the logic level ″ 1 ″ is established at the output of T-trigger 1, which, inverting with element 6, goes to the clock input of T-trigger 9 and switches it to the zero state. With the arrival of the next pulse arriving at input 2, the logic level ″ 0 ″ is set at the output of the T-trigger 1. With the arrival of the next pulse arriving at input 2, the logic level ″ 1 ″ is established at the output of T-flip-flop 1, which through element 6 is fed to the clock input of T-flip-flop 9 and switches it to a single state. This leads to the fact that the T-trigger 10 switches to a single state, putting the element 6 in the mode of inverting the information received at its first input. T-trigger 3, in turn, is switched and, therefore, there is a change in the logic level at the output 4 of the Converter. A positive difference from the output of the T-trigger 10 goes to the clock input of the register 5, shifting the information in it to the left and, accordingly, issuing the next bit of the information packet to the output of the register 5 of the logical level.

Converting a logical ″ 0 ″ is as follows. For one bit of the information packet, which has a logical state of ″ 0 ″, there are two pulses at clock input 2. With the arrival of a pulse arriving at input 2, the level of logic ″ 0 ″ is set at the output of T-trigger 1. At the output of element 7, a positive difference is formed, which is fed to the input of the pulse shaper 11 along the front. The output of the shaper 11 produces a pulse (see figure 2, and), which is fed to the R-inputs of the T-flip-flops 9 and 10, setting them to zero. The negative difference from the output of the T-trigger 10 is supplied to the clock input of the counter-divider 8, by switching it. With the arrival of the next pulse arriving at input 2, the logic level ″ 1 ″ is established at the output of T-flip-flop 1, which through element 6 goes to the clock input of T-flip-flop 9 and switches it to a single state. This leads to the fact that the T-trigger 10 switches to a single state, putting the element 6 in the mode of inverting the information received at its first input. At the output of element 7, the logical level ″ 0 ″ is set. T-trigger 3, in turn, is switched and, therefore, there is a change in the logic level at the output 4 of the Converter. A positive difference from the output of the T-trigger 10 goes to the clock input of the register 5, shifting the information in it to the left and, accordingly, issuing the next bit of the information packet to the output of the register 5 of the logical level.

Conversion of subsequent bits of the information packet is carried out similarly.

At the moment of the end of the conversion of the last bit of the information package at the output of register 5, the logical level ″ 0 ″ is set. With the arrival of the pulse received at input 2, at the output of the T-flip-flop 1, the logical level ″ 0 ″ is set. At the output of element 7, a positive difference is formed, which is fed to the input of the pulse shaper 11 along the front. At the output of the shaper 11, a pulse is generated, which is fed to the R-inputs of the T-flip-flops 9 and 10, setting them to zero. A negative difference from the output of the T-trigger 10 goes to the clock input of the counter-divider 8, switching it so that the logic level ″ 1 ″ is set at its output (see FIG. 2, d), which sets the RS-trigger to zero 12, the logical level ″ 1 ″ from the inverse output of which is supplied to the R-inputs of T-flip-flops 1, 3 and counter-divider 8, resetting them to zero and prohibiting their switching.

To convert the next information package, it is necessary to submit information in binary code to the inputs of the group of 13 inputs, and to generate a pulse at the input of start 14 of a duration of one to two periods of the clock sequence received at input 2. It should be noted that the number of bits in the information package is odd.

A laboratory model of the code converter was made, tests of which confirmed the feasibility and practical value of the claimed object.

Claims (1)

A code converter containing a first trigger, the clock input of which is connected to the clock input of the converter, a second trigger and an output, characterized in that a register, an EXCLUSIVE OR element, an OR-NOT element, a divider counter, a third and fourth trigger, a pulse shaper on the edge are entered , RS-trigger, a group of information inputs and a start input, the first, second, third and fourth triggers are made in the form of T-triggers with R-inputs, while the R-input of the first T-trigger is connected to the inverse output of the RS-trigger and R- inputs of the counter-divider and in of the T-flip-flop, and the output - with the first inputs of the EXCLUSIVE OR element and the OR-NOT element, the output of which is connected to the front of the pulse shaper, and the second input - with the output of the register, the information inputs of which are connected to the corresponding inputs of the group of information inputs of the converter, serial input - with a common bus, parallel boot enable input - with a drive start input and an RS-trigger S-input, and a clock input - with clock inputs of a divider counter and a second T-trigger, fourth T-trigger output and the second input of the EXCLUSIVE OR element, the output of which is connected to the clock input of the third T-trigger, the R-input of which is connected to the front of the pulse shaper and the R-input of the fourth T-trigger, and the output - to the clock input of the fourth T-trigger, output the counter-divider is connected to the R-input of the RS-trigger, the output of the second T-trigger is connected to the output of the converter.

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