RU2008124613A - QUEUE PRIORITY ACCESS DEVICE - Google Patents
QUEUE PRIORITY ACCESS DEVICE Download PDFInfo
- Publication number
- RU2008124613A RU2008124613A RU2008124613/09A RU2008124613A RU2008124613A RU 2008124613 A RU2008124613 A RU 2008124613A RU 2008124613/09 A RU2008124613/09 A RU 2008124613/09A RU 2008124613 A RU2008124613 A RU 2008124613A RU 2008124613 A RU2008124613 A RU 2008124613A
- Authority
- RU
- Russia
- Prior art keywords
- output
- input
- key
- inputs
- outputs
- Prior art date
Links
Landscapes
- Bus Control (AREA)
Abstract
Устройство приоритетного доступа с очередью, содержащее регистр запросов, выходы которого соединены со входами элемента ИЛИ, выход которого соединен с выходом устройства и с первым входом элемента И, второй вход которого соединен с управляющим входом устройства, а выход с открывающим входом первого n-разрядного ключа (n - количество разрядов регистра запросов), информационные входы которого подключены к выходам регистра запросов, первый выход - к соответствующему информационному выходу устройства и через инвертор к открывающему входу второго (n-1-разрядного) ключа, а остальные выходы к информационным входам второго (n-1-разрядного) ключа, и т.д. до n-го ключа, открывающий вход которого соединен с первым выходом, информационный вход со вторым выходом предыдущего n-1 ключа, а выход с соответствующим информационным выходом устройства отличающееся тем, что в него дополнительно введен n-разрядный суммирующий счетчик, выходы которого жестко связаны с соответствующими разрядами регистра запросов, а входы подключены к информационным входам устройства.Priority access device with a queue containing a request register, the outputs of which are connected to the inputs of the OR element, the output of which is connected to the output of the device and the first input of the And element, the second input of which is connected to the control input of the device, and the output with the opening input of the first n-bit key (n is the number of bits of the request register), the information inputs of which are connected to the outputs of the request register, the first output to the corresponding information output of the device and through the inverter to the opening input of T cerned (n-1-bit) key, and other outputs to the data inputs of the second (n-1-bit) key, etc. to the nth key, the opening input of which is connected to the first output, the information input with the second output of the previous n-1 key, and the output with the corresponding information output of the device characterized in that an n-bit totalizing counter is added to it, the outputs of which are rigidly connected with the corresponding bits of the request register, and the inputs are connected to the information inputs of the device.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| RU2008124613/09A RU2008124613A (en) | 2008-06-16 | 2008-06-16 | QUEUE PRIORITY ACCESS DEVICE |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| RU2008124613/09A RU2008124613A (en) | 2008-06-16 | 2008-06-16 | QUEUE PRIORITY ACCESS DEVICE |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| RU2008124613A true RU2008124613A (en) | 2009-12-27 |
Family
ID=41642395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| RU2008124613/09A RU2008124613A (en) | 2008-06-16 | 2008-06-16 | QUEUE PRIORITY ACCESS DEVICE |
Country Status (1)
| Country | Link |
|---|---|
| RU (1) | RU2008124613A (en) |
-
2008
- 2008-06-16 RU RU2008124613/09A patent/RU2008124613A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9361106B2 (en) | SMS4 acceleration processors, methods, systems, and instructions | |
| GB2515862A (en) | Processors, methods, and systems to implement partial register accesses with masked full register accesses | |
| US20150206559A1 (en) | Register file module and method therefor | |
| US8693615B2 (en) | RAM-based event counters using transposition | |
| Lim et al. | Bitsliced high-performance AES-ECB on GPUs | |
| RU2014106624A (en) | PRECISE EXCLUSION SIGNALING FOR ARCHITECTURE WITH MANY DATA | |
| CN105814536A (en) | RSA algorithm acceleration processor, method, system and instructions | |
| US20150280909A1 (en) | Instruction and Logic for a Simon Block Cipher | |
| RU2008124613A (en) | QUEUE PRIORITY ACCESS DEVICE | |
| Steinegger et al. | A Fast and Compact Accelerator for Ascon and Friends. | |
| RU2007106125A (en) | DEVICE FOR DETERMINING THE OPTIMAL SYSTEM MAINTENANCE PROGRAM | |
| ERYILMAZ | Extending the Instruction Set Of RISC-V Processor for ASCON Algorithm | |
| RU2007144787A (en) | PRIORITY ACCESS DEVICE WITH POSSIBILITY OF MASKING APPLICATION | |
| CN102662629B (en) | A kind of method reducing the write port number of processor register file | |
| US20170097883A1 (en) | Differential data access | |
| RU2011127076A (en) | METHOD FOR COMBINED CODING AND CALCULATION OF ECHO SIGNALS AND DEVICE FOR ITS IMPLEMENTATION | |
| RU2006125700A (en) | QUEUE PRIORITY ACCESS DEVICE | |
| RU2007117648A (en) | COMPUTER DEVICE | |
| Fang | Privacy preserving computations accelerated using fpga overlays | |
| Taraate | RTL Tweaks and Performance Improvement Techniques | |
| RU122196U1 (en) | GENERALIZED SHIFT REGISTER | |
| RU41887U1 (en) | DEVICE FOR CONTROL OF PARALLEL BINARY CODE FOR PARITY | |
| Pandit | Tomasulo Architecture Based MIPS Processor | |
| Ahmed et al. | Some new methods to reduce the number of blocks for neighbor designs | |
| SU1269145A1 (en) | Microprocessor calculating device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FA92 | Acknowledgement of application withdrawn (lack of supplementary materials submitted) |
Effective date: 20091218 |