KR20240011596A - Memory device for in memory computin and method thereof - Google Patents

Abstract

A memory device according to one embodiment can perform a multiplication operation using a multiplier cell having a memory cell and a switching element. The memory cell has a pair of inverters connected in opposite directions, a first transistor connected to one end of the pair of inverters, and a second transistor connected to the other end of the pair of inverters, wherein a weight can be set. The switching element is connected to an output end of the memory cell and can output a signal corresponding to a multiplication result between an input value and the weight by performing switching in response to the input value.

Description

Memory device for in-memory computing and method of operating the same {MEMORY DEVICE FOR IN MEMORY COMPUTIN AND METHOD THEREOF}

The disclosure below relates to memory devices for in-memory computing.

Vector-matrix multiplication operations, also known as MAC (multiply and accumulate) operations, determine application performance in a variety of fields. For example, in machine learning and authentication operations of a neural network including multiple layers, a MAC operation may be performed. The input signal can be thought of as forming an input vector, and may be data for an image, byte stream, or other data set. The input signal is multiplied by the weight and an output vector is obtained from the accumulated results of the MAC operation, and this output vector can be provided as an input vector for the next layer. Because this MAC operation is repeated for multiple layers, neural network processing performance is mainly determined by the performance of the MAC operation. MAC operations can be implemented through in-memory computing.

A memory device according to an embodiment includes a pair of inverters connected in opposite directions, a first transistor connected to one end of the pair of inverters, and a second transistor connected to the other end of the pair of inverters. A memory cell that has a transistor and a weight is set, is connected to the output terminal of the memory cell, and performs switching in response to an input value, thereby outputting a signal corresponding to the result of the product between the input value and the weight. It may include a multiplier cell having an element.

The switching element may be connected between a supply voltage and an output terminal of the memory cell, and may be turned off when receiving a logic value of 1 as the input value, and may be turned on when receiving a logic value of 0 as the input value.

The switching element may be configured as a pull-up transistor capable of receiving the input value at a gate terminal.

The first transistor and the second transistor may each be an NMOS transistor, and the pull-up transistor may be a PMOS transistor.

The memory device includes driving the voltage at the output terminal of the pull-up transistor to a supply voltage in response to a voltage lower than the supply voltage being applied through the word line in some of a series of multiplication operations; A first operation of outputting the result of the multiplication operation each time according to the supplied input, and driving the voltage of the output terminal of the pull-up transistor to the supply voltage in a pre-charge phase for each multiplication operation and performing an evaluation phase. ), one of the second operations that performs the multiplication operation can be selected and performed.

The memory device may select one of the first operation and the second operation of the memory device based on at least one of an operating frequency or leakage of the memory device.

The memory device may further include an adder connected to an output terminal of the one or more multiplier cells and adding a value obtained by inverting a signal output from the one or more multiplier cells.

The memory device may further include a global bit line and a switch for accessing a memory cell of the one or more multiplier cells to perform at least one of a read operation or a write operation on the weight of the memory cell.

At least one of the one or more multiplier cells may include a plurality of memory cells connected to the same pull-up transistor.

The memory device may further include an input-word line driver that selects a memory cell to be used for a target multiplication operation among the plurality of memory cells.

The input-wordline driver may include a decoding circuit that decodes an input value provided to the one or more multiplier cells from an input signal and a signal designating a memory cell to be used for a target multiplication operation among a plurality of memory cells included in the multiplier cell. You can.

The memory device may activate a word line connected to a memory cell having a weight corresponding to a target operation among the plurality of memory cells included in one multiplier cell and deactivate word lines connected to the remaining memory cells.

The memory device selects a first memory cell among the plurality of memory cells for a first operation among the plurality of operations and outputs a signal corresponding to the product result through the same pull-up transistor, and selects a first memory cell among the plurality of operations. For the second operation, a second memory cell among the plurality of memory cells may be selected and a signal corresponding to the multiplication result may be output through the same pull-up transistor.

The memory device includes a plurality of multiplier cells including the one or more multiplier cells, each of the plurality of multiplier cells performs a multiplication operation in parallel with other multiplier cells, and the same column of the plurality of multiplier cells The outputs of the multiplier cells connected to the line can be summed in the same adder.

The one or more multiplier cells are connected to a pair of local bit lines, a first memory cell among the plurality of memory cells included in the one or more multiplier cells is connected to a first local bit line, and one of the plurality of memory cells is connected to a first local bit line. The second memory cell may be connected to a second local bit line.

The first memory cell connected to the first local bit line may have a value corresponding to the weight, and the second memory cell connected to the second local bit line may have a value obtained by inverting the weight.

The memory device may further include an accumulator that stores the output of an adder that sums the multiplication result of the one or more multiplier cells and accumulates the sum result.

The memory device may further include an output register that stores the final product operation result output from the accumulator.

When receiving an input signal corresponding to the last bit of a single bit or multi-bit, the memory device may store the result of an accumulator operation for the input signal in the output register.

The memory device may further include a memory controller that controls the one or more multiplier cells, input-word line drivers, read-write circuits, adders, accumulators, and output registers.

The memory device performs an operation for precharging the output terminal of the pull-up transistor in response to at least one of when a predetermined period has elapsed or when a multiplication operation using another memory cell is performed within each multiplier cell. It can be done.

A method of operating a memory device according to an embodiment includes the steps of a memory cell having two inverters connected in opposite directions and two transistors connected to both ends of the two inverters receiving an input value through a word line, the memory A pull-up transistor connected to the output terminal of a cell receives the input value at a gate terminal, and outputting a signal corresponding to a product result between the input value and the weight stored in the memory cell at the output terminal of the pull-up transistor. You can.

A memory device according to an embodiment includes a pull-up transistor having a gate and connected to an output line, a pair of inverters connected in opposite directions, and a gate connected to one end of the pair of inverters and the output line. A memory cell including a cell transistor, and an input having the same logic value is applied to the gate of the pull-up transistor and the gate of the cell transistor, resulting in a binary multiplication of the input by a binary weight set in the memory cell. A logic value corresponding to can be output to the output line.

The logical value corresponding to the binary multiplication result may be NAND.

The pull-up transistor may be a PMOS transistor, and the cell transistor may be an NMOS transistor.

The multiplication result may be output every clock cycle.

The multiplication result may be output every two clock cycles.

The cell transistor is a first cell transistor, and the memory cell further includes a second cell transistor having a gate and connected to the other end of the pair of inverters, and applying the same logic value to the gate of the second cell transistor. Input can be accepted.

The output line is a first output line and may further include a second output line.

The cell transistor is a first cell transistor, and the memory cell may further include a second cell transistor having a gate and connected to the other end of the pair of inverters and the second output line.

The pull-up transistor is a first pull-up transistor and may further include a second pull-up transistor connected to the second output line.

It may include a plurality of memory cells connected to the first output line and the second output line.

It may include a plurality of memory cells connected to the output line.

Figure 1 shows an example of implementation of an in-memory computing system for a neural network multiply and accumulate operation (MAC operation, multiply and accumulate operation) according to an embodiment.
Figure 2 shows an example structure of a memory device in an in-memory computing system according to one embodiment.
3A-3F illustrate the structure of an example multiplier cell in a memory device according to one embodiment.
4 shows examples of operation of a multiplier cell according to one embodiment.
FIG. 5 illustrates a memory device in which multiplier cells are arranged in an array structure, according to one embodiment.
6A and 6B illustrate an example structure in which a plurality of memory cells share a pull-up transistor within a multiplier cell according to one embodiment.
FIG. 7 shows a memory device in which the multiplier cells shown in FIG. 6A are arranged in an array structure.
Figure 8 shows an example in which a multiplier cell outputs a multiplication result through a pair of local bit lines, according to one embodiment.
FIG. 9 shows a memory device in which the multiplier cells shown in FIG. 8 are arranged in an array structure.
Figure 10 is a flowchart showing a method of operating a multiplier cell according to an embodiment.
FIG. 11 is a flowchart illustrating a method of operating a memory device according to an embodiment.
Figure 12 shows an example implementation of a multiplier cell according to one embodiment.

Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be changed and implemented in various forms. Accordingly, the actual implementation form is not limited to the specific disclosed embodiments, and the scope of the present specification includes changes, equivalents, or substitutes included in the technical idea described in the embodiments.

Terms such as first or second may be used to describe various components, but these terms should be interpreted only for the purpose of distinguishing one component from another component. For example, a first component may be named a second component, and similarly, the second component may also be named a first component.

When a component is referred to as being “connected” to another component, it should be understood that it may be directly connected or connected to the other component, but that other components may exist in between.

Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as “comprise” or “have” are intended to designate the presence of the described features, numbers, steps, operations, components, parts, or combinations thereof, and are intended to indicate the presence of one or more other features or numbers, It should be understood that this does not exclude in advance the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art. Terms as defined in commonly used dictionaries should be interpreted as having meanings consistent with the meanings they have in the context of the related technology, and unless clearly defined in this specification, should not be interpreted in an idealized or overly formal sense. No.

As used herein, “A or B”, “at least one of A and B”, “at least one of A or B”, “A, B or C”, “at least one of A, B and C”, and “A Each of phrases such as “at least one of , B, or C” may include any one of the items listed together in the corresponding phrase, or any possible combination thereof.

Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the accompanying drawings, identical components will be assigned the same reference numerals regardless of the reference numerals, and overlapping descriptions thereof will be omitted.

Figure 1 shows an example of implementation of an in-memory computing system for a neural network multiply and accumulate operation (MAC operation, multiply and accumulate operation) according to an embodiment.

In the von-Neumann architecture, performance and power limitations occur due to frequent data movement between the operation unit and the memory unit. In-memory computing (IMC) is a computer architecture that performs calculations directly inside the memory where data is stored, and data movement between the processor 120 and the memory device 110 can be reduced and power efficiency can be increased. there is. The processor 120 of the in-memory computing system 100 according to an embodiment may input data to be calculated into the memory device 110, and the memory device 110 may independently perform the calculation. The processor 120 may read the result of the operation from the memory device 110. Therefore, data transmission during the calculation process can be minimized.

For example, the in-memory computing system 100 may perform multiplication and accumulation (MAC) operations, which are frequently used in artificial intelligence (AI) algorithms, among various operations. As shown in FIG. 1, the layer operation 190 in a neural network may include a MAC operation that adds up the results of multiplying each of the input values of the input nodes by a weight. The MAC operation can be exemplarily expressed as Equation 1 below.

In the above-mentioned equation 1, O _t may represent the output to the t-th node, I _m may represent the m-th input, and W _t,m may represent the weight applied to the m-th input to the t-th node. Here, O _t can be calculated as a weighted sum of the input I _m and the weight W _t,m as the output or node value of the node. Here, m is an integer between 0 and M-1, t is an integer between 0 and T-1, and M and T can be integers. M may be the number of nodes of the previous layer connected to one node of the current layer that is the target of the operation, and T may be the number of nodes of the current layer. The memory device 110 of the in-memory computing system 100 according to one embodiment may perform the above-described MAC operation. Memory device 110 may also be referred to as a resistive memory device 110, a memory array, or an in-memory computing device.

IMC can be divided into analog IMC and digital IMC. Analog IMC can perform MAC operations in the analog domain, including current, charge, or time domains. By way of example, the digital IMC may perform a MAC operation using a logic circuit. Digital IMC can be easily implemented with advanced processes and can exhibit excellent performance. The memory device 110 according to one embodiment may have a Static Random Access Memory (SRAM) including a plurality of transistors (eg, six transistors). SRAM consisting of 6 transistors can also be referred to as 6T SRAM. SRAM stores data as logical values of 0 or 1, so no domain conversion process is required. By way of example, the memory device 110 may include a multiplication cell in which a pull-up transistor and a memory cell (eg, SRAM) are combined. Because the multiplication cell includes a plurality of memory cells connected to one pull-up transistor, the memory array of the memory device 110 can be implemented with fewer transistors. Accordingly, the memory device 110 may have hardware with improved area efficiency and power efficiency through the multiplication cell. However, the memory device 110 is not limited to being used for MAC operations, and the memory device 110 may be used to drive an algorithm including memory storage and multiplication operations. A computing structure in which the memory device 110 according to an embodiment performs operations directly within the memory without moving data will be described below.

Figure 2 shows an example structure of a memory device in an in-memory computing system according to one embodiment.

The memory device 200 (e.g., the memory device 110 of FIG. 1) according to an embodiment includes a multiplier cell 210, an input-word line driver 220, an adder 230, an output unit 240, and a read -May include a writing circuit 280 and a memory controller 290. In a digital in-memory computing system and/or circuit, all data is expressed as logical values and operations are performed, so input values, weights, and output values may all have a binary format. The components described in FIG. 2 may be implemented based on digital logic circuits.

The input-word line driver 220 may transmit input data to perform an operation to the multiplier cell 210. The input-word line driver 220 may generate a pull-up signal and a word line signal that are applied to the memory cell and pull-up transistor of each multiplier cell 210. The pull-up signal and word line signal are signals determined based on the input value of input data, and are explained in FIG. 6A below. Input data may be digital data having an input value of multi bits or single bits. The input-word line driver 220 may receive input data from an external module (eg, processor 110 of FIG. 1). For example, when the input value is multi-bit, the input-word line driver 220 may sequentially transmit the multi-bit values to the multiplier cell 210 for each bit position. For reference, in the example shown in FIG. 2, the input/word line driver 220 may sequentially receive 4-bit input values from the least significant bit (LSB) to the most significant bit (MSB). When the memory device 200 operates for neural network operation, the input-word line driver 220 inputs the input received from M nodes of the layer to the word lines (WL ₀ , WL ₁ to WL _M-1 ). Values can be applied. For example, the input value from the mth node may be applied to WL _m , and the input value applied to WL _m may be multi-bit or single bit. Here, m may be an integer greater than or equal to 0 and less than or equal to M-1, and M may be an integer greater than or equal to 1. When the input value applied to WL _m is multi-bit, the bit value for each bit position may be sequentially transmitted to the multiplier cell 210 as described above. The input-word line driver 220 may individually transfer M input values received from the above-described nodes to M multiplier cells. As will be described later, each of the M multiplier cells performs a multiplication operation in parallel on other multiplier cells, so M multiplication operations can be performed in parallel for each output line (eg, column line).

For reference, if the weight is multi-bit, output lines equal to the number of bits for expressing the weight may be grouped. Grouped output lines can be referred to as an output line group. For example, when the weight is X bits, X output lines may be grouped, and the grouped Here, X may be an integer of 2 or more. Exemplarily, the first output line among the Similarly, the x-th output line can output the result of multiplication between the input bit value and the weight bit value of the x-1th bit position from the LSB. Here, x may be an integer between 2 and X. In this case, the accumulator circuit 241 applies bit shifting of the bit position corresponding to the output line of the same output line group to the sum result output from the corresponding output line, and accumulates the bit-shifted values to obtain the final MAC. Calculation results can be output.

Additionally, when one multiplier cell 210 includes a plurality of memory cells, the input-word line driver 220 may select a memory cell for which a weight to be applied to the received input data is set. The input-word line driver 220 may extract a value indicating a memory cell in which a weight to be applied to input data is set through a decoding unit (eg, a decoding circuit). The operation of a structure in which the multiplier cell 210 includes a plurality of memory cells is explained in FIG. 6A below.

The multiplier cell 210 may perform a multiplication operation between the received input value and the weight stored in the memory cell. The multiplier cell 210 according to one embodiment may output a signal corresponding to the multiplication result through a structure in which a memory cell, a pull-up transistor, a word line (WL), and a pull-up line (PU) are connected. For example, as described in FIGS. 3A to 3F below, the multiplier cell 210 may output a NAND result value of a logical operation between an input bit value and a weight value. Since the multiplication result is the result of logical AND, it can correspond to the inverted value of the NAND result. As will be described later, the results output from the multiplier cell 210 may be inverted and added.

The adder 230 may be connected to the output terminal of the multiplier cell 210. The output stage of the multiplier cell 210 may correspond to an output line. The output terminal of the multiplier cell 210 may be connected to one output line. The adder 230 may add a value obtained by inverting the signal output from the multiplier cell 210. The adder 230 may add the multiplication results of a plurality of multiplier cells 210 connected to the same output line. The adder 230 may be implemented as a full adder, a half adder, and/or a flip-flop, and may be implemented as an adder tree circuit. In addition, as described above, since the output result of the multiplier cell 210 is a NAND result value, the adder 230 is implemented by including an inverting function or inverter that inverts the output result of each multiplier cell 210. It could be. The adder 230 may add the inverted value of the output result of each multiplier cell 210. The adder 230 may transfer the result of adding up multiple multiplication results to the accumulator circuit 241. The adder 230 may be arranged for each output line. When there are T output lines, T adders can be individually arranged. T summed multiplication result values from T adders may be transmitted to the accumulator circuit 241.

The output unit 240 may include an accumulator circuit 241 and an output register 242. The accumulator circuit 241 may combine the results and output the final MAC operation result.

The accumulator circuit 241 (eg, an accumulator) may store the output of an adder that sums the product result of the multiplier cell 210 and accumulates the sum result. For example, when the input-word line driver 220 receives multi-bit input data, the input-word line driver 220 may sequentially transmit the bit value for each bit position to each multiplier cell 210. . Accordingly, each multiplier cell 210 can also output the multiplication result value of the corresponding bit position. The adder 230 may transmit the result of adding up the multiplication results of the corresponding bit positions to the accumulator circuit 241. The accumulator circuit 241 may bit-shift the sum result of the corresponding bit positions. The accumulator circuit 241 can obtain a result in which the multiplication results are accumulated according to the bit position by combining the bit-shifted sum result with the sum result of the next bit position. As will be described later, when the input-word line driver 220 receives input data as a single bit, bit shifting is not necessary, so the accumulator circuit 241 directly transfers the sum result of the adder 230 to the output register 242. You can also pass it on.

The output register 242 may store the final multiplication operation result (eg, multiplication accumulation result) output from the accumulator. For reference, the final multiplication accumulation result (e.g., MAC result) stored in the output register 242 may be read by the processor and used for other operations. For example, if the memory device 200 can only perform MAC operations corresponding to some layers of the neural network at a time, the MAC result stored in the output register 242 is used by the input-wordline driver 220 for the operation of the next layer. It may also be passed on. The input-word line driver 220 of the memory device 200 may perform a multiplication operation by selecting a memory cell in which a weight set corresponding to the next layer is set.

A weight set may represent a set of weights that are multiplied by the input in a MAC operation. For example, the weight set may be a set of connection weights between nodes of one layer and another layer in a neural network. However, the weight set is not limited to being a connection weight between nodes of a neural network, and different weight sets may be used for various tasks. For example, when the first weight set is required in the MAC operation for the first task, the memory device 200 uses a memory set with a weight belonging to the first weight set among the plurality of memory cells included in the multiplier cell 210. You can select cells. Similarly, when the second weight set is required in the MAC operation for the second task, the memory device 200 may select a memory cell with a weight set belonging to the second weight set.

The read-write circuit 280 can read and write data in memory cells included in the multiplier cell 210. The data in the memory cell may include weights to be multiplied by the input value, for example in a MAC operation. The read-write circuit 280 can access the memory cells of the multiplier cell 210 through global bit lines (GBL, GBLB). When the multiplier cell 210 includes a plurality of memory cells, the read-write circuit 280 can access a memory cell connected to an activated word line among the plurality of word lines. The read-write circuit 280 can set a weight in the accessed memory cell or read the set weight. Access through global bit lines (GBL, GBLB) is explained in FIG. 5 below.

The memory controller 290 controls the multiplier cell 210, input-word line driver 220, read-write circuit 280, adder 230, accumulator circuit 241, and output register 242. You can.

The memory device 200 may be implemented as a neural network device, an in-memory computing circuit, a multiplier and accumulator (MAC) circuit, and/or a device. Memory device 200 may include area-efficient SRAM multiply cells for in-memory computing. The memory device 200 may receive an input value through a word line and output a signal (e.g., a NAND result signal) corresponding to the result of multiplication between the input value and the weight stored in the 6T SRAM memory cell through a bit line. The memory device 200 can function as a control and multiplier with fewer transistors.

3A-3F illustrate the structure of an example multiplier cell in a memory device according to one embodiment.

The multiplier cell 310 according to one embodiment may perform a multiplication operation between an input value and a weight set in a memory cell 311. Each of the multiplier cells 310 may include a memory cell 311 and a switching element 319 (eg, a pull-up transistor). Each multiplier cell 310 is connected to two local bit lines, and one switching element 319 may be disposed on at least one of the two local bit lines. For example, each multiplier cell 310 may include only one switching element 319 in one local bit line. In the example shown in FIGS. 3A to 3E, a single switching device 319 may be disposed on the first local bit line LBLB, and no switching device 319 may be disposed on the second local bit line LBL. In FIG. 8 , which will be described later, an example in which one switching element 319 is disposed on each of the two local bit lines (LBL and LBLB) is shown.

According to one embodiment, the memory cell 311 may have a set weight. The memory cell 311 may selectively provide a signal based on a weight to an output line in response to an input value. For example, the memory cell 311 may be disconnected from the output line when receiving a first logic value (eg, a logic value of 0 or a logic value of L) through the word line. When the memory cell 311 receives a second logical value (e.g., a logical value of 1 or a logical value of H) through a word line, a signal based on a weight is sent to the output line (e.g., a value in which the logical value of the set weight is inverted) (signal representing QB)) can be provided to the output line.

The memory cell 311 may include two inverters (INV1 and INV2) and a cell transistor (eg, first transistor TR1). The cell transistor has a gate and may be connected to one end and an output line of the pair of inverters (INV1 and INV2). Two transistors (eg, cell transistors) may be connected to both ends of the two inverters (INV1 and INV2). For example, a pair of inverters (INV1 and INV2) may be connected in opposite directions. A memory device may include a plurality of memory cells connected to an output line.

The first transistor TR1 (eg, a first cell transistor) may be connected to one end of a pair of inverters INV1 and INV2. The second transistor TR2 (eg, a second cell transistor) may be connected to the other terminal of the pair of inverters INV1 and INV2. The memory cell 311 described above may be composed of six transistors including two inverters (INV1 and INV2), a first transistor (TR1), and a second transistor (TR2). The memory cell 311 may be an SRAM implemented with six transistors. A value (QB) with an inverted weight may be set at one end of a pair of inverters (INV1 and INV2). A weight may be set at the other end of a pair of inverters (INV1 and INV2) in the memory cell 311. Gate terminals of the first transistor TR1 and the second transistor TR2 may be connected to the word line WL _m . One end of the first transistor TR1 may be connected to the first local bit line LBLB, and the other end of the first transistor TR1 may be connected to a pair of inverters INV1 and INV2. One end of the second transistor TR2 may be connected to the second local bit line LBL, and the other end of the second transistor TR2 may be connected to a pair of inverters INV1 and INV2. Each of the cell transistors (eg, the first transistor TR1 and the second transistor TR2) may be an NMOS transistor. An input having the same logic value may be applied to the gate of the pull-up transistor, the gate of the first cell transistor, and the gate of the second cell transistor. The first cell transistor may be connected to a first output line (e.g., first local bit line (LBLB)), and the second cell transistor may be connected to a second output line (e.g., second local bit line (LBL)). .

The switching element 319 may be connected to the output terminal (N _out ) of the memory cell 311. The switching element 319 may output a signal corresponding to the result of the product of the input value and the weight by performing switching in response to the input value. The switching element 319 may be connected between the supply voltage (V _DD ) and the output terminal (N _out ) of the memory cell 311. The switching element 319 may be turned off when it receives a logic value of 1 as an input value. The switching element 319 may be turned on when it receives a logic value of 0 as an input value. For example, the switching element 319 may be configured as a pull-up transistor capable of receiving an input value at a gate terminal. In this specification, an example in which the switching element 319 is a pull-up transistor will mainly be described.

A pull-up transistor has a gate and can be connected to an output line. Additionally, in FIGS. 3A to 3E, the gate terminal of the pull-up transistor 319 is connected to a pull-up line, and the pull-up line may be connected to the word line (WL _m ). However, it is not limited to this, and as described later in FIG. 6A, the pull-up line may be connected to the input-word line driver separately from the word line (WL _m ), and the input-word line driver may send an input value to the pull-up line. It may also be approved. The pull-up transistor can output a signal corresponding to the result of the product of the input value and the weight. One end of the pull-up transistor may be connected to the supply voltage (V _DD ), and the other end may be connected to the output terminal (N _out ) of the memory cell 311. The output terminal (N _out ) of the memory cell 311 may be connected to the local bit line bar, and in FIGS. 3A to 3E, a signal corresponding to the multiplication result may be output from the first local bit line (LBLB). The pull-up transistor may be a PMOS transistor.

In a memory device (e.g., multiplier cell 310) according to an embodiment, an input having the same logic value is applied to the gate of the pull-up transistor and the gate of the cell transistor, and the binary weight set in the memory cell 311 and the input The logical value corresponding to the binary multiplication result can be output to the output line. The logical value corresponding to the binary multiplication result may be NAND. For example, multiplier cell 310 may operate like the truth table shown in Figure 3A. The pull-up line (PU) can receive a signal (e.g., an input value) such as the word line (WL _m ). A signal corresponding to the weight may appear at the node Q inside the memory cell 311. The multiplier cell receives the input value through the word line (WL _m ) and sends the result (e.g., NAND result) corresponding to the multiplication between the input value and the weight stored in the node (Q) to the first local bit line (LBLB). Can be printed. LBL may represent a local bit line, and LBLB may represent a local bit line bar. As shown in the truth table, the operation of the multiplier cell 310 may be a NAND operation. 3B to 3E below show the circuit state of the multiplier cell 310 for each proposition.

3B and 3C show the multiplier cell 310 in cases 390b and 390c where the input value received through the pull-up line (PU) and the word line (WL _m ) is 0. The pull-up transistor may provide the supply voltage (V _DD ) to the first local bit line (LBLB). The supply voltage (V _DD ) may represent a logic value of 1. A ground voltage (e.g. 0V) can represent a logic value of 0. The first transistor TR1 may be open due to an input value of 0 received through the word line WL _m . When the first transistor TR1 is opened, the node QB of the memory cell 311 may be disconnected from the first local bit line LBLB. Accordingly, if the input value received through the pull-up line (PU) and the word line (WL _m ) is 0, the output of the multiplier cell 310 may be independent of the weights set at the nodes (Q, QB). The multiplier cell 310 can output a logical value of 1 to the output terminal (N _out ) regardless of whether the weight set at the node (Q) is 0 or 1.

3D and 3E show the multiplier cell 310 in cases 390d and 390e where the input value received through the pull-up line (PU) and the word line (WL _m ) is 1. The pull-up transistor may be open due to an input value of 1 received through the pull-up line (PU). By opening the pull-up transistor, the supply voltage (V _DD ) can be separated from the first local bit line (LBLB). Accordingly, if the input value received through the pull-up line (PU) is 1, the output of the multiplier cell 310 becomes independent of the supply voltage (V _DD ) and may depend on the weights set at the nodes (Q, QB). there is. The multiplier cell 310 may output a value corresponding to the node QB on the first local bit line LBLB. Referring to Figure 3e, when the input value of the pull-up line (PU) and the word line (WL _m ) is 1 and the weight of the node (Q) is 1, the logic of the node (QB) in the first local bit line (LBLB) A ground voltage corresponding to the value 0 (e.g. 0V) may appear. Referring to FIG. 3D, when the input values of the pull-up line (PU) and the word line (WL _m ) are 1 and the weight of the node (Q) is 0 (390), the multiplier cell 310 operates on the first local bit line ( LBLB) voltage can be driven up to V _DD -V _TH . Although V _DD -V _TH does not correspond to the exact logical value 1, it can be substantially treated as a logical value of 1. For reference, during most operations, the first local bit line (LBLB) may be pre-charged with the supply voltage (V _DD ). Since the word line (WL _m ) is turned on while the first local bit line (LBLB) is precharged with the supply voltage (V _DD ), the first local bit line (LBLB) is charged with the supply voltage (V _DD ) or the supply voltage ( It can be maintained at a voltage close to V _DD ). Therefore, a digital logic circuit (e.g., an adder) connected later can correctly recognize the logic value as 1 and operate normally.

However, in the multiplier cell 310 operating in FIG. 3D, as shown in FIG. 3F, due to the parasitic capacitance 380f of the first transistor TR1 and the pull-up transistor, a kind of bootstrapping circuit is formed. You can. If the multiplier cell 310 repeats the operation according to FIG. 3D, power leakage may occur. If power leakage occurs, the operation may be performed as shown in FIG. 4 below.

For reference, signals in an inverse relationship may appear in the second local bit line (LBL) and the first local bit line (LBLB). In this specification, an example in which the same logic value is applied to the pull-up line (PU) and the activated word line (WL _m ) will mainly be described.

4 shows examples of operation of a multiplier cell according to one embodiment.

A memory device (eg, the memory device 200 of FIG. 2 ) according to an embodiment may select and perform one of the first operation 410 and the second operation 420 . Depending on the operation, the multiplication result may be output every clock cycle or every two clock cycles. Figure 4 shows a timing diagram for each operation in one multiplier cell of a memory device. The memory device may perform the first operation 410 and the second operation 420 by selecting and/or combining them. However, it is not limited to this, and the memory device may be designed to perform only one of the first operation 410 and the second operation 420. In the first operation 410, multiplication may be performed every clock cycle, and in the second operation 420, multiplication may be performed every two clock cycles. In the timing diagram, M1 represents the first multiplication operation, M2 represents the second multiplication operation, and the remaining M3 to M8 may represent the third to eighth multiplication operations, respectively. For reference, in the example shown in FIG. 4, in the initial state (init.), there is always no input value received through the word line (WL), so it is 0, so the local bit line (LBLB) is pulled by the pull-up transistor. It can be driven with a supply voltage (V _DD ). In this state, the following operations can be performed.

The first operation 410 may represent an operation of outputting the result of a multiplication operation each time according to the supplied input. The first operation 410 changes the voltage at the output terminal of the pull-up transistor to the supply voltage in response to a sufficiently lower voltage (e.g., 0V) than the supply voltage being applied through the word line (WL) in some of the series of multiplication operations. It may include a driving operation. In other words, the voltage at the output stage can be initialized to the supply voltage. The multiplier cell of the memory device can receive an input signal (e.g., an input value) to be operated on every clock cycle through a word line (WL). The multiplier cell can output the result of a multiplication operation between the input value and the weight stored in the node (Q).

For example, in the M1 state, if the input value received over the word line (WL) is 1 and the weight of the node (Q) is 0, the multiplier cell will maintain the supply voltage (V _DD ) on the local bit line (LBLB). You can. This is because when there is no leakage current or is below the threshold, the voltage of the local bit line (LBLB) does not drop but is maintained at the supply voltage (V _DD ). In the M2 state, since the input value of the word line (WL) is 0, the local bit line (LBLB) can be driven toward the supply voltage (V _DD ). Even if a small leakage current occurs in the M1 state, the voltage of the local bit line (LBLB) can be restored due to driving in the M2 state. When the input becomes 1 again in the M3 state, similar to the M1 state, the multiplier cell can maintain the supply voltage (V _DD ) on the local bit line (LBLB). Therefore, unless the leakage is large, the multiplier cell actually transmits the result of multiplication of all input bit values and weight bit values to the local bit line (LBLB) through the output stage to a voltage corresponding to a logic value (e.g., 0 or V). _DD ) can be output correctly.

For reference, the memory device performs an operation for precharging the output terminal of the pull-up transistor in response to at least one of when a predetermined period has elapsed or when a multiplication operation using another memory cell is performed within each multiplier cell. You can also perform . During the operating time, if no input value of 0 is received through the word line (WL) and pull-up line and the local bit line (LBLB) is not driven to the supply voltage, the voltage on the local bit line (LBLB) gradually decreases to V _DD. -V can be reduced to _TH . The memory device may periodically perform an initialization operation (e.g., applying a voltage of 0 to the word line (WL)) to maintain the voltage at the output terminal of the multiplier at the supply voltage.

The second operation 420 drives the voltage at the output terminal of the pull-up transistor to the supply voltage in the pre-charge phase (P) for each multiplication operation and performs the multiplication operation in the evaluation phase (E). It can represent an action. For example, in the second operation 420, two clock cycles may be divided into a precharge phase (P) and an evaluation phase (E). The operation in the evaluation phase (E) may be the same as the first operation. The memory device can always force the voltage of the word line (WL) to 0 in the clock cycle corresponding to the precharge phase. In other words, the memory device can drive the voltage of the local bit line (LBLB) to which the output terminal of the multiplier cell is connected to the supply voltage (V _DD ). Afterwards, the memory device may perform an operation by transferring the input value to the word line (WL) in the evaluation phase (E). The second operation 420 may be used in a structure in which a large leakage current occurs due to the structure and layout of the circuit, or in a circuit that uses a clock cycle with a frequency slower than the threshold.

Memory devices can be used by selectively determining operation options in an advantageous manner according to the situation. For example, the memory device may select one of the first operation 410 or the second operation 420 based on at least one of the operating frequency or leakage of the memory device. The memory device may perform the second operation 420 when the operating frequency is lower than the threshold frequency, and may perform the first operation 410 when the operating frequency is higher than the threshold frequency. The memory device may perform the second operation 420 when the leakage is greater than the threshold value, and may perform the first operation 410 when the leakage is less than the threshold value. The memory device may further include circuitry for monitoring the above-described operating frequency or leakage current, and the memory controller, input-wordline driver, or external processor of the memory device may determine the operation mode.

FIG. 5 illustrates a memory device in which multiplier cells are arranged in an array structure, according to one embodiment.

A memory device (e.g., the memory device 200 of FIG. 2) according to an embodiment may include a memory array in which several multiplier cells 510 described above in FIG. 3A are arranged. A plurality of multiplier cells 510 may be arranged along a plurality of word lines (WL ₀ to WL _M-1 ) and output lines. The input-word line driver 520 can transmit input values to a plurality of word lines (WL ₀ to WL _M-1 ). An adder 530 may be arranged for each output line. A memory device having the memory array shown in FIG. 5 may also be referred to as an SRAM IMC macro circuit. As described above, the input value may be transmitted to each multiplier cell 510 through word lines (WL ₀ to WL _M-1 ). The multiplier cell 510 may output the result of multiplication between the weight stored in the memory cell and the input value to the local bit line (LBLB). Several local bit lines may be connected to adder 530. The adder 530 may add the multiplication results and transmit the summed result to the accumulator. The accumulator of the output unit 540 may output the final MAC operation result by combining the summed results for each bit position based on bit shifting.

Additionally, the memory device may further include a global bit line (GBL, GBLB) and a switch (SW) for accessing the memory cell of the multiplier cell 510 for at least one of a read operation or a write operation for the weight of the memory cell. there is. The global bit lines (GBL, GBLB) may be connected to the first and second transistors of the multiplier cell 510 via the switch (SW). GBLB may represent a global bit line bar. Global bit lines (GBL, GBLB) may be connected to the read-write circuit 580. For example, a memory device may turn on switches (SW) located at both ends of a memory cell that is the target of a read or write operation. A memory device can access a corresponding memory cell by activating a word line connected to the corresponding memory cell. The memory device may read the weight value written in the corresponding memory cell through the read-write circuit 580, or change and/or set the weight value of the corresponding memory cell.

FIG. 6A below explains a structure in which area efficiency is improved by connecting a plurality of memory cells within one multiplier cell 510 to share one pull-up transistor.

6A and 6B illustrate an example structure in which a plurality of memory cells share a pull-up transistor within a multiplier cell according to one embodiment.

The multiplier cell 610 according to one embodiment may be implemented in a structure in which a plurality of memory cells 611 share the same multiplication circuit. For example, at least one of the multiplier cells 610 may include a plurality of memory cells 611 connected to the same pull-up transistor 619. The pull-up transistor 619 may be connected to the same node and the same local bit line as the output terminals of the plurality of memory cells 611. FIG. 6A shows an example in which the input-word line driver 620 applies the mth input to the ith memory cell 611 among the memory cells 611 inside the multiplier cell 610. i may be an integer between 0 and N-1.

The input-word line driver 620 may select a memory cell 611 to be used for the target multiplication operation from among the plurality of memory cells 611. The input-word line driver 620 may include a decoding circuit. The decoding circuit decodes the input value provided from the input signal to the multiplier cell 610 and a signal designating a memory cell 611 to be used in the target multiplication operation among the plurality of memory cells 611 included in the multiplier cell 610. can do. For example, in FIG. 6A, the signal designating the memory cell 611 to be used in the target multiplication operation may indicate the i-th memory cell 611. The memory device activates the word line connected to the memory cell 611 having a weight corresponding to the target operation among the plurality of memory cells 611 included in one multiplier cell 610, and Connected word lines can be disabled. Inside the multiplier cell 610, only one memory cell 611 can be activated for one multiplication operation. An input signal is always applied to the pull-up line (PU _m ), and the input signal can be applied only to the activated word line among the word lines. The input-word line driver 620 may apply the same logic value to the pull-up line (PU _m ) and the activated word line (WL _m,i ).

Illustratively, the input-word line driver 620 outputs the mth input value (IN) to the ith word line (WL _m,i ) within the multiplier cell 610 for the mth pull-up line (PU _m ) and the mth input. _m ) can be applied. The remaining word lines (WL _m,k ) can be deactivated. As shown in the timing diagram, the m-th multiplier cell 610 multiplies the result (P _m,i ) between the input value received through the i-th word line and the weight of the i-th memory cell 611 in the local bit line. It can be output through a shared pull-up transistor (619). In other words, the multiplier cell 610 may output the product result (P m,i) between the m-th input value (IN _m ) and the ith weight (Q _{m,i )} .

In Figure 6a, examples are shown in which an input value is applied to the ith word line (WL _m,i ) and the mth pull-up line (PU _m ), and the ith weight (Q _m,i ) is 1 or 0. In the example where the ith weight (Q _m,i ) is 1, in cycle 601 where the input value (IN _m ) is 1, the product result (P _m,i ) represents 0 as shown in Figure 3e, and the input value (IN In cycle 602 where _m ) is 0, the product result (P _m,i ) may represent 1, as shown in FIG. 3C. In the example where the ith weight (Q _m,i ) is 0, the product result (P _m,i ) may appear as 1 in all cycles 601 and 602, as shown in FIGS. 3B and 3D.

For reference, the truth table in FIG. 3A assumes that the same input value is applied to the memory cell and the pull-up transistor connected to one word line. Since the logical values of the signal applied to the remaining word line (WL _m,k ) deactivated in FIG. 6A and the pull-up transistor are independent of each other and may be different, the memory cells connected to the remaining word line (WL _m,k ) are shown in FIG. 3A. Truth tables may not apply. As an example, the first transistor and the second transistor are turned off in the memory cells connected to the remaining deactivated word lines (WL _m,k ), so the node to which the weight of the corresponding memory cell is set may be separated from the output terminal. The weights set for the memory cells connected to the remaining deactivated word lines (WL _m,k ) become unrelated to the output terminal, and the memory cells connected to the remaining word lines (WL _m,k ) may be excluded from forming the output. Therefore, in the structure shown in FIG. 6A, the multiplier cell can only output signals corresponding to the multiplication result by the memory cell and pull-up transistor 619 connected to the activated ith word line (WL _m,i ) from the output terminal. As the number of memory cells 611 sharing the same pull-up transistor 619 within one multiplier cell 610 increases, area efficiency may be improved.

According to one embodiment, a memory device may sequentially perform a plurality of operations while selectively activating memory cells corresponding to each operation. If M multiplier cells are arranged in one output line, and each multiplier cell includes N memory cells, the total number of memory cells may be M×N. Since one memory cell is selected from each of the M multiplier cells for each operation, the memory device can select M memory cells among the M×N memory cells. For a first operation among a plurality of operations, the memory device may select a first memory cell among the plurality of memory cells and output a signal corresponding to the multiplication result through the same pull-up transistor 619. For the second operation among the plurality of operations, the memory device may select a second memory cell among the plurality of memory cells and output a signal corresponding to the multiplication result through the same pull-up transistor 619.

Referring to FIG. 6B as an example, the memory device may divide and execute the operation of the large neural network 690b into a plurality of operations. The weights of the neural network corresponding to each operation may be distributed and set to a plurality of memory cells. When performing the first operation among the neural network operations, the memory device may activate the first memory cell 611b in which the first weight for the first operation is set for each multiplier cell 610. The remaining memory cells within each multiplier cell 610 may be deactivated. When performing the second operation among the neural network operations after performing the first operation, the memory device may activate the second memory cell 612b in which the second weight for the second operation is set for each multiplier cell 610. there is. The remaining memory cells, including the first memory cell 611b, may be deactivated. For simplicity of explanation, Figure 6b shows that a first operation corresponding to an arbitrary node in the neural network 690b and a second operation corresponding to a subsequent node connected to that node are performed on different memory cells within the same multiplier cell 610. An example performed using (611b, 612b) will be described. In this example, the first operation is an operation that multiplies one input value (IN _m ) among the plurality of input values (IN) propagated to the corresponding node by the first weight (Q _m,i ), and the second operation is propagated to the subsequent node. It may be an operation that multiplies one input value (IN' _m ) among a plurality of input values (IN') by a second weight (Q _m,j ). However, it is not limited to this, and memory cells within the same multiplier cell have weights for operations in different parts of the same task (e.g., the same neural network operation) or different tasks (e.g., face recognition and object recognition). It may also have weights for . Figure 7 below explains an array structure that allows the use of selective memory cells for each operation.

FIG. 7 shows a memory device in which the multiplier cells shown in FIG. 6A are arranged in an array structure.

A memory device according to an embodiment may include a plurality of multiplier cells including a multiplier cell 710. For example, multiplier cells can be arranged in an array structure. A plurality of multiplier cells may be arranged along a plurality of output lines and a plurality of word lines. As shown in FIG _. 7, the input-wordline driver 720 selects one memory cell (e.g., The memory cell corresponding to i) can be selected. The input-word line driver 720 may transfer an input value (IN _m ) to a memory cell in which a weight (Q _m,i ) corresponding to a target task is individually set for a plurality of multiplier cells. Accordingly, when a memory device performs various tasks in a plurality of cycles, the weight (Q _m,i ) required in each cycle can be set in advance to the memory cells in each multiplier cell. When the target task is changed, the memory device performs a multiplication operation by selecting a memory cell with a weight (Q _m,i ) corresponding to the target task among preset memory cells without the need to externally load the weight corresponding to the changed task. It can be done.

Multiplier cells connected to the same word line can receive the same input value (IN _m ). Each of the plurality of multiplier cells may perform a multiplication operation in parallel with other multiplier cells. The memory device may sum the outputs of multiplier cells connected to the same column line (eg, the same output line) among a plurality of multiplier cells in the same adder 730. One multiplier cell and another multiplier cell can output multiplication results in parallel. Within one multiplier cell 710, a multiplication operation based on one memory cell may be performed. In other words, if each multiplier cell 710 includes N memory cells, the input-wordline driver 720 may select one memory cell among the N memory cells every cycle. M multiplication operations can be performed in parallel in M multiplier cells connected to the output line. When there are T output lines, M×T multiplication operations can be performed in parallel in the memory array of the memory device. Since the results of M multiplication operations connected to the same output line are summed, the output unit 740 can generate T accumulated output values.

In the memory device shown in FIG. 7, as the number of memory cells included in the multiplier cell 710 increases, the number of transistors required for one multiplication operation may decrease. For example, if the multiplier cell 710 includes four memory cells, one multiplication operation can be interpreted as being implemented by 7.25 transistors. Since each memory cell contains 6 transistors, 1 transistor for pull-up, and each of the 2 switches for the global bit line contains 2 transistors, (6 × 4 + 5) = 29 transistors in 4 This is because the memory cells are divided. If the multiplier cell 710 includes eight memory cells, one multiplication operation can be interpreted as being implemented by 6.625 transistors. Similarly, (6×8+5)=53 transistors are divided into 8 memory cells. If the multiplier cell 710 includes 16 memory cells, one multiplication operation can be interpreted as being implemented by 6.3125 transistors. Similarly, (6×16+5)=101 transistors are divided into 16 memory cells. Since a plurality of multiplier cells arranged in an array along a word line can be driven by one input-word line driver 720, area overhead can also be reduced. In the memory device according to one embodiment, a large area reduction effect can be achieved compared to the comparative example.

As shown in FIG. 7, a pattern of one pull-up line (PU) and a plurality of word lines (WL _0,0 to WL _0,N-1 ) may appear repeatedly in the layout 790. .

FIG. 8 shows an example in which the multiplier cell 810 outputs a multiplication result through a pair of local bit lines, according to one embodiment.

The multiplier cell 810 according to one embodiment may be connected to a pair of local bit lines. The multiplier cell 810 outputs the multiplication result based on the first memory cell 811 among the plurality of memory cells to the first local bit line 850R, and outputs the multiplication result based on the second memory cell 812 to the second local bit line 850R. Can be output to bit line (850L). In FIG. 8 , the first memory cell 811 is a memory cell with a weight (Q _m,i ) set, and the second memory cell 812 is a memory cell with a weight (Q _m,j ) set. For reference, in FIG. 3A, the first local bit line 850R is shown as an output terminal, but in FIG. 8, the multiplication result can be output from both the first local bit line 850R and the second local bit line 850L. . Here, as a result corresponding to the product operation, the first local bit line 850R outputs a NAND result between the input value IN _m and the weight Q _m,i, as described in FIGS. 1 to 7. You can. On the other hand, in the second local bit line 850L, a NAND result between the inverted value of the weight (Q _m,j ) and the input value (IN _m ) may be output as a result corresponding to the multiplication operation. The memory device may set a value corresponding to the weight to be calculated in the first memory cell 811 and set an inverse value of the weight to be calculated in the second memory cell 812.

The memory device includes a second local bit line 850L (e.g., a second local bit line 850L) together with a first pull-up transistor 819-R for outputting the multiplication result to the first local bit line 850R (e.g., a first output line). It may also include a second pull-up transistor (819-L) for outputting the multiplication result to the output line. Accordingly, the first memory cell 811 connected to the first local bit line 850R may have a value corresponding to the weight. The second memory cell 812 connected to the second local bit line 850L may have an inverted weight value. A memory device may include a plurality of memory cells connected to a first output line and a second output line.

The multiplication result output through the first local bit line 850R of the first memory cell 811 is added to the multiplication result output through the second local bit line 850L of the second memory cell 812 in the adder. You can. In other words, even if it is the same multiplier cell, the product results of memory cells connected to different local bit lines can be summed in the adder. The structure shown in FIG. 8 can be interpreted as two column lines merged into one multiplier cell 810. The multiplier cell 810 shown in FIG. 8 may include N memory cells. A first memory cell 811 (e.g., ith memory cell) among N/2 memory cells connected to the first local bit line 850R, and among N/2 memory cells connected to the second local bit line 850L. A multiplication operation may be performed in each of the second memory cells 812 (e.g., the jth memory cell). Here, N may be an integer that is a multiple of 2. A first word line (RWL) and a second word line (LWL) may be connected to each memory cell. The input-word line driver 820 activates one word line (RWL m, _i ) among the first word lines (RWL _m,0 to RWL _m,N-1 ) and the remaining word line (RWL _m,k ) can be disabled. The input-word line driver 820 activates one word line (LWL m, _j ) among the second word lines (LWL _m,0 to LWL _m,N-1 ) and the remaining word lines (LWL _m,p ) can be disabled. i, j, k, and p are each integers greater than 0, i may be different from k, and p may be different from j.

For reference, the memory device performs a multiplication operation based on a memory cell with one of the even-numbered weights within the multiplier cell 810 to the first local bit line 850R, and a memory cell with one of the odd-numbered weights. A multiplication operation based on can be output to the second local bit line 850L. However, the weight setting method is not limited to the above-described method. For example, in this specification, for a symmetrical structure, the number of memory cells connected to the first local bit line 850R and the number of memory cells connected to the second local bit line 850L within one multiplier cell 810 are Although the same example has been described, it is not necessarily limited to this. Depending on the design, the number of memory cells connected to each local bit line may vary.

The memory device according to one embodiment simultaneously performs multiplication of the first weight (Qm, _i ) and the second weight (Q _m,j ) on the same input value (IN _m ) within one multiplier cell 810. can do. The input-word line driver 820 applies the logical value of the input value (IN _m ) to the pull-up line (PU _m ), the second word line (LWL _m,j ), and the first word line (RWL _m,i ) at once. can do. The input-word line driver 820 can apply a logical value of 0 to all remaining word lines. The first multiplication result (RP) and the second multiplication result (LP) may be simultaneously output from the first local bit line 850R and the second local bit line 850L, respectively. The structure shown in FIG. 8 may be advantageous in terms of layout because it is a symmetrical structure.

FIG. 9 shows a memory device in which the multiplier cells shown in FIG. 8 are arranged in an array structure.

In the array structure shown in FIG. 7, the multiplier cell 910 shown in FIG. 8 may be placed. Two word lines (RWL, LWL) may be required for each multiplier cell 910. Additionally, each multiplier cell 910 can simultaneously output two multiplication results through two local bit lines (LBL and LBLB). By way of example, the first local bit line 950R of FIG. 9 may correspond to LBLB, and the second local bit line 950L may correspond to LBL. The input-word line driver 920 selects a first memory cell corresponding to the first local bit line 950R and a second memory cell corresponding to the second local bit line 950L for each multiplier cell 910, and , parallel multiplication operations can be performed individually. For reference, even if the memory device outputs the product result using one memory cell to the first local bit line 950R in a random cycle, the product result of the corresponding memory cell is always output to the first local bit line 950R. It is not fixed. The memory device may operate to output the product result using the corresponding memory cell to the second local bit line 950L in another cycle. In this case, the memory device may set an inverted weight to the corresponding memory cell.

The multiplication results of the local bit lines may be individually transmitted to the adder 930. For example, in the example shown in Figure 9, the first and second memory cells of multiplier cell 910 are mapped to the first local bit line 950R, and the third and fourth memory cells are mapped to the first local bit line 950R. It can be assumed that it is mapped to the second local bit line 950L. The memory device may add the product result based on the first memory cell and the product result based on the third or fourth memory cell in the adder 930. Similarly, the memory device may add the product result based on the second memory cell with the product result based on the third or fourth memory cell in the adder 930 . As described above in FIG. 8, even if the memory cells are arranged within the same multiplier cell 910, the multiplication results based on memory cells corresponding to different local bit lines can be performed in parallel, and further, the adder 930 can be summed up. The output unit 940 may accumulate the outputs of the adder 930 connected to each output line and output the final product result.

Figure 10 is a flowchart showing a method of operating a multiplier cell according to an embodiment.

First, in step 1010, the memory device may transfer the input value to the multiplier cell. For example, a memory cell can receive input values through a word line. As described above, a memory cell may have two inverters connected in opposite directions and two transistors connected to both ends of the two inverters. A pull-up transistor connected to the output terminal of the memory cell can receive the input value at the gate terminal.

And in step 1020, the multiplier cell of the memory device may output a signal corresponding to the multiplication result. For example, a memory device may output a signal corresponding to a product result between an input value and a weight stored in a memory cell at the output terminal of a pull-up transistor. According to the truth table described above in FIG. 3A, a signal (eg, NAND result) corresponding to the product result may be output from the output terminal of the pull-up transistor and the memory cell.

FIG. 11 is a flowchart illustrating a method of operating a memory device according to an embodiment.

First, in step 1101, the memory device can manage data in the memory array. For example, a memory device can use a read-write circuit to set a weight for each memory cell in a memory array. An external processor may instruct the memory device of the data to be written and the address of the memory cell where the weight will be set.

And in step 1102, the memory device may determine whether to initiate MAC operation. For example, when the memory device receives an input value that is the target of the MAC operation, it may initiate the MAC operation.

Next, in step 1010, the memory device may transfer the input value to the multiplier cell. For example, in step 1111, the memory device may transmit the input signal and the weight set address to the input-word line driver. An external processor may transmit the above-described input signal and a weight set address (eg, a signal indicating the ith memory cell among memory cells included in a multiplier cell) to the memory device. At step 1112, the input-wordline driver may generate a control signal. For example, the input-word line driver may decode the input signal and the weight set address, and apply the same logic value as the input value to the pull-up line (PU _m ) and word line (WL _m,i ). The input-word line driver can apply a logical value of 0 to the remaining word lines.

And in step 1120, the memory device may output a signal corresponding to the multiplication result of the memory cell selected within the multiplier cell. For example, each multiplier cell may output a signal (e.g., NAND result value) corresponding to the result of multiplication between the input value (IN _m ) and the weight (Q _m,i ) of the selected memory cell to the local bit line. The outputs of multiple multiplier cells connected to the same output line may be transmitted to the adder of the corresponding output line.

In step 1130, an adder may perform a sum operation of each product result. As described above, since the adder receives the NAND result, it can sum the inverted value of the NAND result. The adder can transfer the summed multiplication result values to the accumulator.

At step 1140, an accumulator may accumulate the results of the sum operation. As will be described later, when the input value is multi-bit, the accumulator can perform bit shifting according to the corresponding bit position and accumulate the product result for the next bit position.

In step 1150, the memory device may determine whether the input value on which the multiplication operation has been performed is the last bit. For example, when performing an operation on the last bit, the memory device may transfer the output of the accumulator to an output register. If the input value is a single bit, there is no need for accumulation, so the accumulator may bypass the product result to the output register. If the current input bit value is not the last bit, the memory device can perform the same operation on the input bit value of the next bit position. When the product result is output from the adder, the memory device can accumulate by bit-shifting the previously stored accumulation result through an accumulator, adding it to the current product result, and storing the result again in the accumulator.

In step 1160, the memory device may store the accumulated result in an output register. For example, when the memory device receives an input signal corresponding to the last bit of a single bit or multiple bits, the memory device may store the result of an accumulator operation for the input signal in an output register.

In step 1170, the memory device initializes the accumulator and terminates when the MAC operation is completed.

In the memory device according to one embodiment, compared to the comparative embodiment that implements a 128Kb crossbar array structure with 10 or 12 transistors, the required number of transistors and total transistors for implementing the multiplication function is improved by more than 30% and/ Or it may be reduced.

Figure 12 shows an example implementation of a multiplier cell according to one embodiment.

According to one embodiment, the electronic device 1200 includes a High Density (HD) In-Memory Computing (IMC) macro 1210, a CPU 1220, a RAM 1230, a logical block 1240, and a High Efficiency (HE) May include IMC macro 1250.

The HD IMC macro 1210 may represent a memory macro unit in which the multiplier cells described above in FIGS. 1 to 11 are arranged. HD IMC macro 1210 may have high memory density and high memory capacity. The HD IMC macro 1210 may have a structure in which the above-described multiplier cells are arranged in a crossbar shape. Since a plurality of memory cells are integrated into a multiplier cell, the number of transistors required to manufacture a memory macro unit can be reduced.

The CPU 1220 may include a High Speed (HS) IMC macro 1221. The HS IMC macro 1221 has high throughput and operating speed and can represent a cell structure of a register file type.

RAM 1230 may include memory for use as system memory.

Logic block 1240 may include logic circuits used for various logical operations.

The High Efficiency (HE) IMC macro 1250 may have high energy efficiency and low supply voltage operation.

The electronic device 1200 according to one embodiment may be implemented as a dedicated hardware accelerator for an AI algorithm (eg, face recognition).

The embodiments described above may be implemented with hardware components, software components, and/or a combination of hardware components and software components. For example, the devices, methods, and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, and a field programmable gate (FPGA). It may be implemented using a general-purpose computer or a special-purpose computer, such as an array, programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and software applications running on the operating system. Additionally, a processing device may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, a single processing device may be described as being used; however, those skilled in the art will understand that a processing device includes multiple processing elements and/or multiple types of processing elements. It can be seen that it may include. For example, a processing device may include multiple processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are possible.

Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing unit to operate as desired, or may be processed independently or collectively. You can command the device. Software and/or data may be used on any type of machine, component, physical device, virtual equipment, computer storage medium or device to be interpreted by or to provide instructions or data to a processing device. , or may be permanently or temporarily embodied in a transmitted signal wave. Software may be distributed over networked computer systems and thus stored or executed in a distributed manner. Software and data may be stored on a computer-readable recording medium.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. A computer-readable medium may store program instructions, data files, data structures, etc., singly or in combination, and the program instructions recorded on the medium may be specially designed and constructed for the embodiment or may be known and available to those skilled in the art of computer software. there is. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. -Includes optical media (magneto-optical media) and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, etc. Examples of program instructions include machine language code, such as that produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

The hardware devices described above may be configured to operate as one or multiple software modules to perform the operations of the embodiments, and vice versa.

As described above, although the embodiments have been described with limited drawings, those skilled in the art can apply various technical modifications and variations based on this. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims (33)

In the memory device,
A memory having a pair of inverters connected in opposite directions, a first transistor connected to one end of the pair of inverters, and a second transistor connected to the other end of the pair of inverters, and a weight is set. cell (memory cell);
A switching element connected to the output terminal of the memory cell and performing switching in response to an input value to output a signal corresponding to the result of the product of the input value and the weight.
A multiplier cell with
A memory device containing a. According to paragraph 1,
The switching element is,
Connected between the supply voltage and the output terminal of the memory cell,
Turns off when receiving a logical value of 1 as the input value,
Turned on when receiving a logical value of 0 as the input value,
memory device. According to paragraph 1,
The switching element is,
Consisting of a pull-up transistor capable of receiving the input value at the gate terminal,
memory device. According to paragraph 3,
The first transistor and the second transistor are
Each is an NMOS transistor,
The pull-up transistor is,
PMOS transistor,
memory device. According to paragraph 3,
The memory device is,
Some of the series of multiplication operations include driving the voltage at the output stage of the pull-up transistor to the supply voltage in response to a voltage lower than the supply voltage being applied through the word line, each time depending on the supplied input. a first operation that outputs the result of the product operation, and
A second operation of driving the voltage of the output terminal of the pull-up transistor to a supply voltage in a pre-charge phase and performing a multiplication operation in an evaluation phase for each multiplication operation.
Selecting and performing one of the actions,
memory device. According to clause 5,
The memory device is,
selecting one of the first operation or the second operation of the memory device based on at least one of an operating frequency or leakage of the memory device,
memory device. According to paragraph 1,
The memory device is,
An adder connected to the output terminal of the multiplier cell and adding a value obtained by inverting the signal output from the multiplier cell.
A memory device further comprising: According to paragraph 1,
The memory device is,
A global bit line and switch for accessing the memory cell of the multiplier cell and performing at least one of a read operation or a write operation on the weight of the memory cell
A memory device further comprising: According to paragraph 1,
The multiplier cell is,
Multiple memory cells connected to the same pull-up transistor
A memory device containing a. According to clause 9,
The memory device is,
An input-word line driver that selects a memory cell to be used for a target multiplication operation among the plurality of memory cells.
A memory device further comprising: According to clause 10,
The input-word line driver,
A decoding circuit that decodes an input value provided from an input signal to the multiplier cell and a signal designating a memory cell to be used for a target multiplication operation among a plurality of memory cells included in the multiplier cell.
A memory device containing a. According to clause 9,
The memory device is,
Activating a word line connected to a memory cell having a weight corresponding to a target operation among the plurality of memory cells included in one multiplier cell and deactivating a word line connected to the remaining memory cells,
memory device. According to clause 9,
The memory device is,
For the first operation among the plurality of operations, a first memory cell among the plurality of memory cells is selected and a signal corresponding to the product result is output through the same pull-up transistor,
For the second operation among the plurality of operations, a second memory cell among the plurality of memory cells is selected and a signal corresponding to the product result is output through the same pull-up transistor.
memory device. According to paragraph 1,
The memory device is,
comprising a plurality of multiplier cells including the multiplier cell,
Performing a multiplication operation in parallel with other multiplier cells in each of the plurality of multiplier cells,
Summing the outputs of multiplier cells connected to the same column line among the plurality of multiplier cells in the same adder,
memory device. According to paragraph 1,
The multiplier cell is,
connected to a pair of local bit lines,
A first memory cell among the plurality of memory cells included in the multiplier cell is connected to a first local bit line,
A second memory cell among the plurality of memory cells is connected to a second local bit line,
memory device. In paragraph 15:
The first memory cell connected to the first local bit line has a value corresponding to a weight,
The second memory cell connected to the second local bit line has a weight inverted value,
memory device. According to paragraph 1,
The memory device is,
An accumulator that stores the output of an adder that sums the multiplication results of the multiplier cells and accumulates the sum results.
A memory device further comprising: According to clause 17,
An output register that stores the final product operation result output from the accumulator.
A memory device further comprising: According to clause 14,
The memory device is,
When receiving an input signal corresponding to the last bit of a single bit or multi-bit, storing the result of an accumulator operation for the input signal in the output register,
memory device. According to paragraph 1,
A memory controller that controls the multiplier cells, input-word line drivers, read-write circuits, adders, accumulators, and output registers.
A memory device further comprising: According to paragraph 1,
The memory device is,
In response to at least one of when a predetermined period has elapsed or when a multiplication operation using another memory cell is performed within each multiplier cell, an operation for precharging the output terminal of the pull-up transistor is performed.
memory device. In a method of operating a memory device,
A memory cell having two inverters connected in opposite directions and two transistors connected to both ends of the two inverters receives an input value through a word line;
A pull-up transistor connected to the output terminal of the memory cell receives the input value at a gate terminal; and
Outputting a signal corresponding to a product result between the input value and the weight stored in the memory cell at the output terminal of the pull-up transistor.
An operation method comprising: A pull-up transistor having a gate connected to an output line; and
a memory cell including a pair of inverters connected in opposite directions, and a cell transistor having a gate and connected to one end of the pair of inverters and the output line;
contains
An input having the same logic value is applied to the gate of the pull-up transistor and the gate of the cell transistor, and a logic value corresponding to a result of binary multiplication of the input and the binary weight set in the memory cell is output to the output line,
memory device. According to clause 23,
The logical value corresponding to the binary multiplication result is NAND,
memory device. According to clause 23,
The pull-up transistor is a PMOS transistor,
The cell transistor is an NMOS transistor,
memory device. According to clause 23,
The multiplication result is output every clock cycle,
memory device. According to clause 23,
The multiplication result is output every two clock cycles,
memory device. According to clause 23,
The cell transistor is,
It is a first cell transistor,
The memory cell is,
It further includes a second cell transistor having a gate and connected to the other end of the pair of inverters,
An input having the same logic value is applied to the gate of the second cell transistor,
memory device. According to clause 23,
The output line is a first output line,
further comprising a second output line,
memory device. According to clause 29,
The cell transistor is,
It is a first cell transistor,
The memory cell is,
Further comprising a second cell transistor having a gate and connected to the other end of the pair of inverters and the second output line,
memory device. According to clause 30,
The pull-up transistor is,
It is a first pull-up transistor,
Further comprising a second pull-up transistor connected to the second output line,
memory device. According to clause 31,
Comprising a plurality of memory cells connected to the first output line and the second output line,
memory device. According to clause 23,
Comprising a plurality of the memory cells connected to the output line,
memory device.

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