KR102665969B1 - In memory computing(imc) circuir, neural network device including imc circuit and operating method of imc circuit - Google Patents

Abstract

Apparatus and methods including in-memory computing (IMC) are provided. The in-memory computing (IMC) circuit includes a static random access memory (SRAM) bit cell circuit including memory banks each containing a bit cell, and for each memory bank a static random access Bit cells grouped into the same word line of memory, operators configured to output signals corresponding to operation results corresponding to each bit cell, and a target memory for multi-accumulate (MAC) operation among a plurality of memory banks. It includes a gate logic circuit configured to transmit an operation result corresponding to each bit cell belonging to the bank to an adder.

Description

IMC (IN MEMORY COMPUTING) circuit, neural network device including IMC circuit, and operating method of IMC circuit {IN MEMORY COMPUTING (IMC) CIRCUIR, NEURAL NETWORK DEVICE INCLUDING IMC CIRCUIT AND OPERATING METHOD OF IMC CIRCUIT}

The following embodiments relate to an IN MEMORY COMPUTING (IMC) circuit, a neural network device including an IMC circuit, and a method of operating the IMC circuit.

Various types of neural networks trained with machine learning and/or deep learning to provide high performance, for example, accuracy, speed, and/or energy efficiency, in many application areas. ; NN) can be used. Algorithms that enable machine learning of neural networks have a very large computational load, but can be performed by processing simple operations, such as the MAC (Multiplication and Accumulation) operation, for example, dot product of two vectors and cumulative sum of their values. there is. Non-complex operations such as MAC operations can be implemented through IN MEMORY COMPUTING.

According to one embodiment, an in-memory computing circuit includes a plurality of memory banks; and a logic gate that receives a logical operation result of each of the memory banks, where each of the memory banks includes a bit cell that stores a weight. and an operator that receives an input value, where the operator is connected to the bit cell and receives the input value and outputs a result of a logical operation between the input value and the weight.

The logical operation result of each of the memory banks may be a NAND operation value for the input value and the weight.

The logic gate may be a NAND gate.

The logic gate may output a result of multiplication between an input value of one selected memory bank among the memory banks and a weight.

Each of the unselected memory banks among the memory banks may receive an input value of 0.

The in-memory computing circuit may further include an adder coupled to the logic gate.

The operator may include a plurality of transistors that output signals corresponding to the result of a bit-wise multiplication operation.

The operator includes a two transistor (2T) circuit including a first transistor and a second transistor, and the input value is applied to the first gate terminal of the first transistor and the second gate terminal of the second transistor, , the output value of the first transistor that passes through the first gate terminal is connected to the output value of the second transistor that passes through the second gate terminal, thereby outputting the logic operation result.

A value based on the weight stored in the bit cell is applied to the drain terminal of the first transistor, and the source terminal of the first transistor may be connected to the input terminal of the logic gate through the drain terminal of the second transistor.

The first transistor may include an NMOS transistor, and the second transistor may include a PMOS transistor.

The operator includes a three transistor (3T) circuit including a transmission gate and a third transistor, and the input value is input from an enable terminal of the transmission gate and a third transistor of the third transistor. It is applied to the gate terminal, and each of the output value of the transmission gate and the output value of the third transistor that passes through the third gate terminal is connected to the input of the logic gate to output the logic operation result.

The logic gate may transfer the result of the logic operation corresponding to the bit cell to the adder depending on whether the input value is applied to the operator.

The in-memory computing circuit may be used in a mobile device, mobile computing device, mobile phone, smartphone, personal digital assistant, fixed location terminal, tablet computer, computer, wearable device, laptop computer, server, music device, etc. to at least one device selected from the group consisting of players, video players, entertainment units, navigation devices, communication devices, navigation devices, GPS devices, televisions, tuners, automobiles, vehicle parts, avionics systems, drones, multicopters, and medical devices. can be integrated.

According to one embodiment, a neural network device including in-memory computing circuitry includes an array circuit including in-memory computing circuits; and a controller that inputs second values corresponding to the input signal of the neural network device to each of the in-memory computing circuits according to a clock signal and controls the in-memory computing circuits, wherein the in-memory Each of the computing circuits includes a plurality of memory banks, each of the memory banks comprising a bit cell for storing weights and an operator for receiving an input value; and a logic gate that receives the result of the logical operation of each of the memory banks, wherein the operator is connected to the bit cell and receives the input value, and outputs the result of the logical operation between the input value and the weight. do.

The logical operation result of each of the memory banks may be a NAND operation value for the input value and the weight.

The logic gate may be a NAND gate.

The controller includes an input feature map (IFM) buffer that stores an input feature map including the input value; a control circuit that controls whether the input value is applied to the plurality of IMC circuits; and a read write (RW) circuit that reads or writes the weight.

According to one embodiment, an in-memory computing device includes memory banks each including respective bit cell units; a logic gate receiving outputs of operators of each bit cell unit; and an adder that receives the output of the logic gate to perform at least a portion of a MAC operation, wherein each bit cell unit includes a bit cell and an operator, none of the bit cells sharing the same operator.

An output of each bit cell unit is connected to the logic gate, each of the bit cells stores a respective stored value, and the bit cell units each have an input that provides a respective input value to the bit cell units. connected to a line, and the in-memory computing device allows input values provided to the bit cell units to select which one of the bit cell units will be the target of an operation to be performed on the stored value by a corresponding operator. You can.

The stored values of the bit cell units that are not the target of the operation may not affect the output of the logic gate.

1 is a diagram illustrating an example of a neural network in which operations can be performed in an in-memory computing (IMC) circuit according to an embodiment.
2A to 2D are diagrams illustrating an in-memory computing (IMC) circuit structure according to an embodiment.
FIG. 3 is a diagram for explaining the operation of an in-memory computing (IMC) circuit including four memory banks, according to an embodiment.
Figure 4 is a block diagram of an in-memory computing (IMC) circuit according to one embodiment.
FIGS. 5A and 5B are diagrams for explaining an operation when an operator of an in-memory computing (IMC) circuit is composed of two transistors, according to an embodiment.
6A and 6B are diagrams to explain how an in-memory computing (IMC) circuit selects a memory bank, according to an embodiment.
FIG. 7 is a diagram illustrating the operation of an in-memory computing (IMC) circuit when the operator is composed of three transistors, according to an embodiment.
FIG. 8 is a diagram for explaining the operation of an in-memory computing (IMC) circuit when the operator is composed of three transistors according to another embodiment.
Figure 9 is a block diagram of a neural network device including an in-memory computing (IMC) circuit according to one embodiment.
Figure 10 is a block diagram of an electronic system including a neural network device according to one embodiment.
Figure 11 is a flowchart showing a method of operating an in-memory computing (IMC) circuit according to an embodiment.

Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be changed and implemented in various forms. Accordingly, the actual implementation form is not limited to the specific disclosed embodiments, and the scope of the present specification includes changes, equivalents, or substitutes included in the technical idea described in the embodiments.

Terms such as first or second may be used to describe various components, but these terms should be interpreted only for the purpose of distinguishing one component from another component. For example, a first component may be named a second component, and similarly, the second component may also be named a first component.

When a component is referred to as being “connected” to another component, it should be understood that it may be directly connected or connected to the other component, but that other components may exist in between.

Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "have" are intended to designate the presence of the described features, numbers, steps, operations, components, parts, or combinations thereof, but are not intended to indicate the presence of one or more other features or numbers, It should be understood that this does not exclude in advance the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art. Terms as defined in commonly used dictionaries should be interpreted as having meanings consistent with the meanings they have in the context of the related technology, and unless clearly defined in this specification, should not be interpreted in an idealized or overly formal sense. No.

Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the accompanying drawings, identical components will be assigned the same reference numerals regardless of the reference numerals, and overlapping descriptions thereof will be omitted.

1 is a diagram illustrating an example of a neural network in which operations can be performed in an in-memory computing (IMC) circuit according to an embodiment. 1, a neural network 110 is shown whose operations may be performed by corresponding in-memory computing circuitry.

In-Memory Computing (IMC) is a method of computing data directly inside the memory where data is stored in order to overcome the performance and power limitations caused by frequent data movement between the computational unit (e.g. processor) and memory that occurs in the von-Neumann architecture. It may correspond to a computing architecture that allows calculations to be performed. In-memory computing (IMC) circuits can be divided into analog in-memory computing (IMC) circuits and digital in-memory computing (IMC) circuits, depending on the domain in which the calculation is performed. Analog in-memory computing (IMC) circuits can perform operations in the analog domain, for example, current, charge, time, etc. Digital in-memory computing (IMC) circuits can use logic circuits to perform operations in the digital domain. The embodiments below describe a digital in-memory computing circuit.

In-memory computing (IMC) circuits can accelerate matrix operations that perform addition to multiple multiplications at once, and/or MAC (Multiplication and Accumulation) operations, which are used for artificial intelligence (Artificial Intelligence). It is very common in learning and inference in AI. The MAC operation for learning or inference of the neural network 110 may be performed through a memory array, and the memory array includes bit cells of a memory element in an in-memory computing (IMC) circuit. Hereinafter, for convenience of explanation, the case where the neural network 110 is composed of fully connected layers will be described as an example, but the present invention is not necessarily limited thereto. The neural network 110 may be a convolutional neural network composed of convolutional layers. An in-memory computing (IMC) circuit may enable machine learning and inference of the neural network 110 by performing the corresponding MAC operation through an operation function by a memory array including bit cells.

The neural network 110 may be, for example, a deep neural network (DNN) or an n-layer neural network including two or more hidden layers. The neural network 110 may be, for example, a deep neural network (DNN) including an input layer (Layer 1), two hidden layers (Layer 2 and Layer 3), and an output layer (Layer 4), and must include: It is not limited. When the neural network 110 is implemented with a DNN architecture, it includes more layers that can process valid information, so the neural network 110 can process more complex data sets than a neural network with a single layer. Meanwhile, the neural network 110 is shown as including four layers, but this is only an example and the neural network 110 may include fewer or more layers, or fewer or more channels. The neural network 110 may include layers of various structures different from those shown in FIG. 1 .

Each of the layers included in the neural network 110 may include a plurality of nodes 115. A node is a plurality of artificial nodes, known as 'neurons', 'processing elements (PEs)', 'units', 'channels' or similar terms. nodes). For example, the neural network 110 may include an input layer containing 3 nodes, each of the hidden layers containing 5 nodes, and an output layer containing 3 output nodes, but is not necessarily limited thereto. No. The example in FIG. 1 corresponds to one embodiment, and each of the layers included in the neural network 110 may include various numbers of nodes. Nodes 115 included in each layer of the neural network 110 may be connected to each other to process data. For example, one node can receive data from other node(s), perform calculations, and output the calculation results to other nodes.

A plurality of nodes 115 of one layer are connected to nodes of another layer through a connection line, and a weight (w) may be set on the connection line. For example, the result of a node's operation (o ₁ ) is the input data propagated from other nodes of the previous layer connected to that node (e.g., i ₁ , i ₂ , i ₃ , i ₄ , i ₅ ) and the corresponding It can be determined based on the weights (w ₁₁ , w ₂₁ , w ₃₁ , w _41, w ₅₁ ) of the node's connection lines.

For example, the lth output o _l among the L output values can be expressed as Equation 1 below. Here, L may be an integer greater than or equal to 1, and l may be an integer greater than or equal to 1 and less than or equal to L.

In Equation 1, i _k represents the kth input among the P inputs, and w _kl may represent a weight set between the kth input and the lth output. Here, P is an integer greater than or equal to 1, and k may represent an integer greater than or equal to 1 but less than P.

In other words, input and output between nodes 115 in the neural network 110 can be expressed as a weighted sum between input (i) and weight (w). A weighted sum is a multiplication operation and repetitive addition operation between a plurality of inputs and a plurality of weights, and can also be referred to as a 'MAC (Multiplication and Accumulation) operation.' Since the MAC operation is performed using a memory with an added calculation function, the circuit in which the MAC operation is performed may be referred to as an 'in-memory computing (IMC) circuit.'

For example, the neural network 110 performs a weighted sum operation in layers based on input data (e.g., i ₁ , i ₂ , i ₃ , i ₄ , i ₅ ), and provides the result of the operation (e.g., Output data (e.g. u ₁ , u ₂ , u ₃ ) can be generated based on o ₁ , o ₂ , o ₃ , o ₄ , o ₅ ).

2A, 2B, 2C, and 2D are diagrams illustrating an example structure of an IMC macro including an in-memory computing (IMC) circuit according to an embodiment. Referring to FIG. 2A, the IMC macro 200 according to one embodiment includes a write word line (WWL) driver 210, an in-memory computing (IMC) circuit 220, and an adder. (230), accumulation operator 240, input driver (or read word line driver (RWL) driver) 250, memory controller (control unit) 260, and write bit line The IMC macro 200 may include a driver (WBL (Write Bit Line) driver) 270, for example, but is not limited to a 64 kb SRAM IMC macro as shown in FIG. 2A. .

As described below, an IMC circuit (e.g., IMC circuit 220) may include a bit cell circuit (e.g., SRAM bit cell circuit 225), each bit cell circuit having a bit cell circuit. It may have cell units (e.g., bit cell units 223a-223d). The bit cell units of each bit cell circuit may be included in each memory bank of the IMC circuit (e.g., bit cell units 223a-223d may be included in banks 0-3, respectively). Each bit cell unit may include a bit cell and an operator (e.g., bit cell unit 223a may include a bit cell 221 and an operator 222). The bit cell circuits of the IMC circuit may also have respective gate logic circuits (e.g., the SRAM bit cell circuit 225 may have a corresponding gate logic circuit 227). The bit cell units of the bit cell circuit may each be connected to a gate logic circuit corresponding to the bit cell circuit (for example, the bit cell units 223a-223d may be connected to the gate logic circuit 227).

As described above, the in-memory computing (IMC) circuit 220 includes a gate logic circuit 227 that includes bit cells (e.g., bit cells 221) with respective operators arranged in respective memory banks. ) and operators (e.g., operators 222). The operators output signals corresponding to the results of operations on each bit cell. For example, Figure 2C shows a four SRAM bit cell circuit with each bit cell 221-0 through 221-3 in Bank0. That is, the bit cell circuit may be included in each of four memory banks, such as memory bank Bank 0, memory bank Bank 1, memory bank Bank 2, and memory bank Bank 3. Bit cell units corresponding to the same memory bank (eg, bank 0) may receive the same input value.

As described above, for example, in the SRAM bit cell circuit 225, one bit cell 221 corresponding to one memory bank and (outputting an operation result corresponding to one bit cell 221) One operator 222 may be referred to as a 'bit cell unit' 223 in that it is the basic operation unit of a bit cell. For example, one bit cell 221 may have an 8-transistor (8T) SRAM cell structure for storing bit values. One operator 222 may include, for example, two transistor (2T) circuits for performing operations. For example, the bit cell unit 223 includes 10 transistors (10T) in which operators 222 of a two-transistor (2T) circuit are combined with bit cells 221 having an 8-transistor (8T) SRAM cell structure. It may have a SRAM cell structure composed of . The operator(s) 222 may be, for example, a general logic multiplier or pass transistor logic. The gate logic circuit 227 produces an operation result corresponding to each bit cell belonging to a target memory bank for MAC (Multiplication and Accumulation) operation among the bit cells 221 corresponding to a plurality of memory banks. is transmitted to the adder 230.

Hereinafter, for convenience of explanation, 'read word line (RWL) and write word line (WWL)' are simplified and expressed as 'word line (WL)', and 'write word line driver (WWL driver) and read word line'. ‘Driver (RWL driver)’ can be simplified and expressed as ‘word line driver (WL driver)’. ‘Write Bit Line (WBL)’ can also be simplified and expressed as ‘bit line (BL)’.

The IMC macro 200 can perform digital operations that express all data as digital logic values such as '0' and/or '1', including input data 201, weight 203, and output data 205. ) may have a binary format. For example, input data 201 and weight 203 can be converted into output data 205 by an activation function (f _act )dp. 2A to 2D may be implemented as a digital logic circuit.

The read word line (RWL) is the same as the path through which the input data 201 is applied, so the input driver 250 may correspond to a read word line driver (RWL driver). The input driver 250 may transmit the input data 201 on which an operation (e.g., a multiplication operation or a convolution operation) of the in-memory computing (IMC) circuit 220 is to be performed (e.g., an external operator). . The read word line (RWL) signal may be determined based on the input value of the input data 201. The input data 201 may be multi bit or single bit digital data.

The input data 201 read through the input driver 250 may be converted into an input signal of the IMC circuit 220 through an encoding (ENC) block 255. The encoding block 255 may provide the IMC circuit 220 with a signal for selecting a target memory bank for MAC operation from among a plurality of memory banks along with the converted input signal. The operation of the input driver 250 will be described in detail with reference to FIG. 2B. In addition, the process in which operations are performed in the memory banks will be described with reference to FIG. 2C below, and the data (e.g., weight value or input value) read by the write bit line (WBL) driver 270 is stored in the memory banks ( The process of writing to bit cells is explained in more detail with reference to FIG. 2D below.

Referring to FIG. 2B, an example of a process in which input data read by the input driver 250 according to an embodiment is input to the IMC circuit 220 through the encoding block 255 is shown. For example, if the IMC macro 200 is a 64kb SRAM IMC macro as shown in FIG. 2A, the input driver 250 can read 64 input data such as IN[63:0]. At this time, each of the 64 input data may consist of 4 bits. The input driver 250 may sequentially input 4-bit input data 201 (e.g., “0011 0100 1010”) one bit at a time into the encoding block 255. The encoding block 255 encodes the input data 201 (e.g., “0011 0100 1010”) into any one of four memory banks according to a 2-bit control signal (e.g., “00” or “10”). It can be passed on. At this time, each of the four memory banks may correspond to corresponding bit cells.

For example, when the first memory bank (bank 0) is used as an operator, the IMC macro 200 may apply a 2-bit control signal (“00”) to the encoding block 255. As the 2-bit control signal (“00”) is applied to the encoding block 255, the encoding block 255 encodes the input data (e.g., “0011 0100 1010”) into the first memory bank (bank 0). 1 It can be provided sequentially to bit cell units through output (e.g. O0).

When the second memory bank (bank 1) is used as an operator, the IMC macro 200 can apply a 2-bit control signal (“01”) to the encoding block 255, and the encoding block 255 is the second The same input data can be provided to the bit cell units of the second memory bank Bank1 through the second output O1 connected to the memory bank Bank1.

When the third memory bank (bank 2) is used as an operator, the IMC macro 200 may apply a control signal (“10”) to the encoding block 255, and the encoding block 255 may use the third memory bank (Bank2) ) The same input data can be provided to the bit cell units of the third memory bank (Bank2) through the third output (O2) connected to ).

When the fourth memory bank (bank 3) is used as an operator, the IMC macro 200 may apply a control signal (“11”) to the encoding block 255, and the encoding block 255 may transfer input data to the fourth memory. It can be output to the fourth memory bank (Bank3) through the fourth output (O ₃ ) connected to the bank (Bank3). In each case, whichever output (e.g., O0) of encoding block 255 is activated by a control signal to provide input data to the corresponding target/selected memory bank (e.g., Bank0) 255 may cause other outputs (e.g., O ₁ , O ₂ and O ₃ ) to output “0” to other (unselected/non-target) memory banks. In this way, the output of the IMC macro's gate logic circuit can depend only on the output of each operation of the operator in the selected memory bank (since it operates on the input bits and bits in the bit cells of the selected memory bank).

Referring to FIG. 2C, according to one embodiment, the input data 201 read by the input driver 250 is transferred to the memory banks of the SRAM bit cell circuit 225, and an operation is performed in each memory bank. A drawing for explanation is shown. For example, as described with reference to FIG. 2B, as the control signal (“00”) is applied to the encoding block 255, the encoding block 255 converts the input data (e.g., “0011 0100 1011”) into the IMC. It can be provided sequentially in bit units to the bit cell units 221-0, 221-1, 221-2, and 221-3 corresponding to the first memory bank (bank 0) of the circuit 220. At this time, the encoding block 255 may provide '0' to the remaining memory banks (e.g., bank 1, bank 2, bank 3) except the first memory bank (bank 0). Each of the bit cell units of the first memory bank (bank 0) contains values of input data sequentially provided from the encoding block 255 and each bit cell (221-0, 221-1, 221-2, 221-3). The results of an operation (e.g., multiplication operation) between stored weight values (e.g., weights (w ₀ , w ₁ , w ₂ , w ₃ ) containing random “0” or “1”) can be output.

For example, if the weight value w ₀ stored in the bit cell is “0”, the gate logic circuit 227 connected to the bit cell unit outputs the input data (e.g., “0011 0100 1010”) and w ₀ (“0”). ) can be multiplied in bits to output "0000 0000 0000". The weight contents of the remaining memory banks other than Bank0 do not affect the output of the gate logic circuit 227 for this operation, as the remaining memory banks all receive a “0” from the encoding block 255 during each multiplication operation. Because it does. with weight value w ₀ = 1 In this case, the logic circuit 227 connected to the bit cell unit 221-0 may output "0011 0100 1011", which is the result of a multiplication operation between input data (e.g., "0011 0100 1011") and "1", as an operation result. there is. Again, the weight values of memory banks other than Bank0 do not affect the output of gate logic circuit 227 for these operations because these memory banks all receive "0" from encoding block 255 during each multiplication operation. No.

Referring to FIG. 2D, the write bit line (WBL) driver 270 according to an embodiment stores the read data (e.g., weight value or input value) in memory banks (bit cells) (e.g., the first memory bank (bank). A drawing is shown to explain the writing process in 0)). Write word line (WWL) driver 210 may select memory banks (and thus bit cells) to write data to in-memory computing (IMC) circuitry 220. For example, if you want to write data to the first memory bank (bank 0), the write word line (WWL) driver 210 applies (applies) “1000” to the write word line (WWL) [3:0]. You can select the first memory bank (bank 0). If you want to write data to the fourth memory bank (bank 3), the write word line (WWL) driver 210 applies “0001” to the write word line (WWL) [3:0] to write data to the fourth memory bank (bank 3). ) can be selected. Additionally, the write bit line (WBL) driver 270 may provide data (eg, weight values) to be stored in bit cells selected by the write word line (WWL) driver 210. WBL[255:0] shown in FIG. 2A may correspond to a path for writing data to bit cells. In a 64 x 64 operator as shown in Figure 2a, 256 bits of data are simultaneously recorded in 64 rows, each with a weight of 4 bits (e.g., w ₀ , w ₁ , w ₂ , w ₃ ). It can be. Depending on the structure, 64 bits of data can be recorded simultaneously in column direction. When 256 bits of input (for storage) continuously transmit data to each column (one column per cycle), the data of the entire operator can be recorded for a total of 64 cycles. When the write bit line (WBL) driver 270 performs a write operation, '0' may be input to the read word line (RWL).

The input driver 250 may receive input data 201 from an external module, for example, a processor (e.g., see processor 1010 in FIG. 10), or an input feature map (IFM) buffer. (For example, see IFM buffer 931 in FIG. 9) Input data 201 may be read from an input feature map stored in the input feature map. The source of the input data is not critical; any source may be used.

For example, when the input value of the input data 201 shown in FIG. 2A is multi-bit, the input driver 250 sequentially stores the multi-bit values by bit position through an in-memory computing (IMC) circuit. It can be delivered to (220). For example, when the IMC macro 200 operates for neural network operation, the input driver 250 may operate like a read word line driver (RWL driver). Hereinafter, the input driver 250 and the read word line driver (RWL driver) may be understood to have the same meaning.

In this case, the input driver 250 may apply input values received from M nodes of each layer of the neural network to read word lines (e.g., RWL ₀ , RWL ₁ to RWL _M-1 ). At this time, RWLm and IN[m] may correspond to the same node.

For example, the input value from the mth node may be applied to RWLm, and the input value applied to RWLm may be multi-bit or single bit. Here, m is an integer from 0 to M-1, and M may be an integer from 1 to 1. For example, when the input value applied to RWLm is multi-bit, the bit value for each bit position may be sequentially transmitted to the in-memory computing (IMC) circuit 220 as described above. The input driver 250 may individually transfer M input values received from the above-described nodes to M bit cells. As will be described later, each of the M bit cells performs a multiplication operation on other bit cells in parallel, so M multiplication operations can be performed in parallel for each bit line.

Alternatively, when the weight 203 is multi-bit, output lines equal to the number of bits for expressing the weight 203 may be grouped. Grouped output lines can be called an ‘output line group’. For example, if the weight 203 is The result of summing the multiplication between the weights 203 can be output. Here, X may be an integer of 2 or more.

The SRAM bit cell circuit 225 may be composed of several bit cells to express multi-bit weights. At this time, the input can be applied to each bit cell simultaneously for multiplication with the multi-bit weight. Exemplarily, the first output line among the Similarly, the x-th output line can output the result of multiplication between the input bit value and the weight bit value of the x-1th bit position from the LSB. Here, x may be an integer between 2 and X. In this case, the accumulation operator 240 applies the result of shifting the bit positions corresponding to the output lines of the same output line group by a certain bit (e.g., one bit) to the sum result output from the corresponding output line, The final MAC operation result can be output by accumulating the values obtained by shifting the bit positions. The accumulation operator 240 may be implemented with, for example, a shifter and an adder, or a separate accumulator, but is not necessarily limited thereto.

Each of the bit cells may store, for example, a weight 203 value (eg, a first value). The structure and operation of the in-memory computing (IMC) circuit 220 including a plurality of bit cells will be described in more detail with reference to FIGS. 3 and 4 below.

The in-memory computing (IMC) circuit 220 may perform a multiplication operation between the value of the input data 201 received through the input driver 250 and the weight 203 stored in the bit cell. The in-memory computing (IMC) circuit 220 according to one embodiment has a structure in which bit cell(s), operator(s) 222, and gate logic circuit are connected to calculate operation results (e.g., corresponding to each of the bit cells). A signal corresponding to the bit-wise product operation result can be output. For example, as described in Figure 3 below, as an overall computational effect, the in-memory computing (IMC) circuit 220 stores a weight 203 value (e.g., a first value) and a word stored in each of the bit cells. The result value of the AND logic operation on the signals corresponding to the result of the multiplication operation between the input values (e.g., the second value) applied as the input signals of the bit cells corresponding to the memory banks through the line is transmitted to the adder 230. You can.

For example, the operator 222 may be in the form of pass transistor logic that minimizes the number of transistors.

Adder 230 may be connected to the output of one or more in-memory computing (IMC) circuits 220. The output stage of the in-memory computing (IMC) circuit 220 may correspond to an output line. The output terminal of one or more in-memory computing (IMC) circuits 220 may be connected to one output line. Adder 230 may add signals output from one or more in-memory computing (IMC) circuits 220. The adder 230 may add the multiplication results of a plurality of in-memory computing (IMC) circuits 220 connected to the same output line. Adder 230 may be implemented as, for example, a full adder, a half adder, and/or a flip-flop. For example, the adder 230 may correspond to a digital adder such as an adder tree circuit, but is not necessarily limited thereto.

In addition, as described above, since the output result of the in-memory computing (IMC) circuit 220 is overall the result of the AND logic operation, the adder 230 is the result of each in-memory computing (IMC) circuit 220. It may also be implemented including an inverter that inverts the output result. In this case, the adder 230 may add a value obtained by inverting the output result of the in-memory computing (IMC) circuit 220. The adder 230 may transfer the sum of the multiplication results corresponding to each bit cell to the accumulation operator 240. Adder 230 may be disposed on each output line of the in-memory computing (IMC) circuit 220.

The accumulation operator 240 may store the output of the adder 230, which sums the product operation results of one or more in-memory computing (IMC) circuits 220, and accumulates the sum results. The accumulation operator 240 sums the multiplication results corresponding to each bit cell in the adder 230, and finally combines the summed results to produce a MAC operation result (e.g., Q ₀ [13:0] to Q ₆₃ [ 13:0]).

For example, when the input driver 250 receives multi-bit input data 201, the word line driver 210 generates write word lines (for example, WWL ₀ [3:0 ] ~ WWL ₆₃ [3:0]), the bit value for each bit position of the input data 201 can be sequentially transmitted to the in-memory computing (IMC) circuit 220. Accordingly, the in-memory computing (IMC) circuit 220 may also output the result of the multiplication operation of the corresponding bit digit. The adder 230 may transfer the result of adding up the product operation result values of the corresponding bit positions to the accumulation operator 240.

The accumulation operator 240 can add the sum results of the corresponding bit positions by bit shifting. The accumulation operator 240 may accumulate product operation results according to bit positions by combining the sum result of the next bit position with the corresponding bit shifted sum result. As will be described later, when the input driver 250 receives input data in a single bit, bit shifting is not necessary, so the accumulation operator 240 directly outputs the sum result of the adder 230, or uses an output register. It can be saved at (not shown).

The output register may store the final multiplication operation result (eg, multiplication accumulation result) output from the accumulation operator 240. The accumulation operator 240 performs not only shift operations and sum operations. It can also be called "Shift & adder + accumulaor" (240) in that it also performs accumulation operations. The final multiplication accumulation result (e.g., MAC operation result) stored in the output register may be read by, for example, a processor of the electronic system (e.g., see processor 1010 in FIG. 10) and used for other operations. For example, when the IMC macro 200 performs a MAC operation corresponding to some layers of the neural network at once, the MAC operation result stored in the output register is sent to the word line driver 210 for the operation performed in the next layer. It may also be transmitted as . The word line driver 210 of the IMC macro 200 may perform a multiplication operation by selecting bit cell(s) for which a weight set corresponding to the next layer is set.

The write bit line driver (WBL driver) 270 can write data of one or more bit cells included in the in-memory computing (IMC) circuit 220. The write bit line driver (WBL driver) 270 can be simplified and expressed as a ‘write circuit’. Hereinafter, 'write bitline driver' and 'write circuit' may be used interchangeably.

The data of one or more bit cells may include a weight 203 value to be multiplied by the input value, for example, in a MAC operation. The write bitline driver 270 may access a bit cell of the in-memory computing (IMC) circuit 220 through a bit line (eg, WBL, WBLB). When the in-memory computing (IMC) circuit 220 includes a plurality of bit cells, the write bit line driver 270 is connected to a bit cell connected to an activated word line among the plurality of word lines (RWL). You can access it. The write bitline driver 270 can set (write) a weight to the accessed bit cell or read the weight set to the bit cell.

The memory controller 260 includes a word line driver 210, one or more in-memory computing (IMC) circuits 220, and an accumulation operator 240 (e.g., accumulation operator <0> to accumulation operator <63>). ), the adder 230, the input driver 250, and/or the output register can be controlled.

The IMC macro 200 may be implemented as, for example, a neural network device, an in-memory computing circuit, a MAC operation circuit, and/or a device, but is not necessarily limited thereto. The IMC macro 200 may receive an input value through a word line and output a signal corresponding to the result of multiplication between the input value and the weight stored in the 10T SRAM bit cell through the bit line.

FIG. 3 is a diagram for explaining the structure of an in-memory computing (IMC) circuit according to an embodiment. Referring to FIG. 3, an in-memory computing (IMC) circuit 220 according to an embodiment may include an SRAM bitcell circuit 225 and a gate logic circuit 340.

The SRAM bit cell circuit 225 may include a plurality of bit cell units 223 corresponding to each of a plurality of memory banks. The bit cell unit 223 may include one bit cell 310 and an operator 320 that outputs a signal corresponding to an operation result between an input bit and a value stored in one bit cell 310. The operator 320 may correspond to the operator 222 described above with reference to FIG. 2 . _The bit cell 310 may include a word line transistor consisting of two inverters (311 and 313) and two transmission gates (315 and 317). Here, the 'transmission gate' is a bidirectional switch in which an NMOS transistor and a PMOS transistor are connected in parallel and can be controlled by an externally applied logic level. For example, when '1' is applied to the enable (E) terminal of the transmission gates 315 and 317, the transmission gates 315 and 317 may function as a 'closed' switch. In contrast, when '0' is applied to the enable terminal of the transmission gates 315 and 317, the transmission gates 315 and 317 may function as an 'open' switch. Each of the inverters 311 and 313 and the transmission gates 315 and 317 may be composed of two transistors.

The operator 320 may include a plurality of transistors (eg, a first transistor 321 and a second transistor 323). A plurality of transistors (e.g., the first transistor 321 and the second transistor 323) are applied as an input signal to the bit cell 310 through the first value stored in the bit cell 310 and the input driver 250. A signal corresponding to the result of a bit-wise product operation between the second values may be output.

Operator 320 may be composed of two transistors 2T as shown in FIGS. 3, 5, and/or 6, or three transistors as shown in FIGS. 7 and/or 8. It may also be composed of (3T).

For example, as shown in FIG. 3, when the operator 320 is composed of two transistors, the bit cell unit 223 is composed of 10 transistors (2 x 2 + 2 x 2 + 2 = 10). In that it is configured, the SRAM bit cell circuit 225 can be called a '10T SRAM cell' structure or a '10T' structure.

The same input value may be applied to bit cell units 310 of the SRAM bit cell circuit 225 corresponding to the same memory bank. A 'memory bank' may correspond to one block when the entire memory area is divided into a plurality of blocks. A memory bank corresponds to a logical bundle of one or more memories within a channel, which is a bundle that shares one data path when there are multiple pairs of identical addresses representing memory areas and 64-bit input/output occurs. can do. Memory banks may be used in multiple pairs or sets. For example, a memory bank may correspond to a memory group that shares an adder 230, such as an adder tree. Bit cells 310 may correspond to four memory banks, for example.

Each of the operators 320 performs a bitwise (bit-) operation between the first value stored in each of the bit cells corresponding to the corresponding memory bank among the plurality of memory banks and the second value applied as the input signal of the corresponding memory bank through the word line. wise) may include a plurality of transistors (eg, 321, 323) that output signals corresponding to the result of the multiplication operation. Each of the operators 320 may correspond to each of the bit cells 310.

The gate logic circuit 340 can transmit the operation results corresponding to each bit cell belonging to the target memory bank for MAC (Multiplication and Accumulation) among the plurality of memory banks to the adder 230. there is. The gate logic circuit 340 may transmit the operation result corresponding to each bit cell belonging to the corresponding memory bank to the adder 230 depending on whether the second value is applied to each of the operators 320. The gate logic circuit 340 may include, but is not necessarily limited to, any one of, for example, a NAND gate, a NOR gate, an XOR gate, an XNOR gate, an AND gate, and an OR gate. For example, if the gate logic circuit 340 includes a NOR gate, an It can be changed to a suitable form.

In the in-memory computing (IMC) circuit 220, the size of the layout and the complexity of routing of the SRAM bit cell circuit 225 will greatly affect the power efficiency and/or area efficiency of the SRAM IMC circuit. You can.

Additionally, the area efficiency (D _M ) of the memory can be obtained as shown in Equation 2 below.

Here, WE may correspond to memory capacity for multi-bit. For example, to express 8 bits, WE can be 8, and to express 4 bits, WE can be 4.

Area density can be improved by reducing the area of the memory or increasing the number of memory banks according to Equation 3. For example, the area of the memory may correspond to the area occupied by bit cells, adder 230, and/or peripheral control lines.

In the same principle, by reducing the number of transistor(s) included in the in-memory computing (IMC) circuit 220, reducing the number of transistor(s) constituting the memory cell, or increasing the number of memory banks, The area of the memory computing (IMC) circuit 220 can be reduced.

In one embodiment, the bit cells of the SRAM are configured to correspond to a plurality of memory banks, and the plurality of memory banks are configured by an operator 320 and a gate logic circuit 340 composed of a small number (e.g., 2 or 3) of transistors. By allowing the operation result corresponding to the target memory bank among the memory banks to be transmitted to the adder 230, the number of control lines in the in-memory computing (IMC) circuit is reduced, enabling low-voltage write operation. Meanwhile, the area efficiency of in-memory computing (IMC) circuits can also be improved. Here, 'target memory bank' may be a term referring to a corresponding memory bank when the operation result corresponding to each cell belonging to the corresponding memory bank among a plurality of memory banks is used in the MAC operation.

A method of configuring the bit cells of the in-memory computing (IMC) circuit 220 into a plurality of memory banks will be described in more detail with reference to FIG. 4 below.

4 is a block diagram of an in-memory computing (IMC) circuit according to one embodiment. Referring to FIG. 4, SRAM bit cells 415 (e.g., bit cells 221 of FIG. 2) and SRAM bit cells (e.g., Bank ₀ to Bank _{n) corresponding to a plurality of memory banks (e.g., Bank 0 to Bank n} ). In-memory computing including an SRAM bitcell circuit 225 and an adder 440 (e.g., an adder tree) including operators 420 (e.g., operators 222 of FIG. 2) corresponding to 415) A diagram 400 showing the structure of an (IMC) circuit is shown.

Among the bit cells 415 of the SRAM bit cell circuit 410 for each of the four memory banks, the bit cells corresponding to the same memory bank contain the same word line of the SRAM read by the input driver (e.g., IN<0: n-1> The values of <0>, .., IN<0: n-1><63>) can be applied. Here, n may be, for example, 64, but is not necessarily limited thereto.

The SRAM bit cell circuit 225 of the IMC circuit 220 includes operators ( 420) may be included. The IMC circuit 220 can adjust the inputs of the operators 420 that perform the operation so that the operation results corresponding to each SRAM bit cell 415 belonging to the target memory bank for the MAC operation are delivered to the adder 440. (That is, non-target computation results do not contribute to the computation result).

The output of each of the operators 420 may be transmitted to an adder 440 such as an adder tree through a logic operation (eg, NAND logic operation) of the gate logic circuit 430.

The in-memory computing (IMC) circuit 220 ensures that the operation result corresponding to the bit cells belonging to the target memory bank for MAC operation is '1' or 0' depending on the bit cell value of the target memory bank and the input bit value. And, the operation result corresponding to the bit cells belonging to the remaining memory banks except the target memory bank can be set to '0'. By doing this, the operation result corresponding to the target memory bank can be used in the MAC operation, and memory banks other than the target memory bank do not affect the operation result.

In one embodiment, the number of control lines that control the operator(s) 420 is reduced by configuring the SRAM bit cells 415 into a plurality of memory banks, thereby reducing the implementation area of the in-memory computing (IMC) circuit 220. By reducing, the area efficiency of the in-memory computing (IMC) circuit 220 can be improved.

Additionally, in one embodiment, the total number of transistors constituting the in-memory computing (IMC) circuit 220 can be reduced by reducing the number of transistors for the multiplication operation by the operator(s) 420.

The in-memory computing (IMC) circuit 220 partially separates the power applied to each of the SRAM bitcell circuit 225, the gate logic circuit 430, and the adder 440 to form the SRAM bitcell circuit 225, Different voltages may be applied to each of the gate logic circuit 430 and/or the adder 440.

FIGS. 5A and 5B are diagrams for explaining an operation when an operator of an in-memory computing (IMC) circuit is composed of two transistors, according to an embodiment. Referring to FIG. 5A, a diagram 500 showing the structure of an in-memory computing (IMC) circuit including an SRAM bitcell circuit 225 and a gate logic circuit (e.g., NAND gate) 430 according to an embodiment. This is shown.

The SRAM bit cell circuit 225 includes, for each bit cell unit, a bit cell 310 consisting of eight transistors (8T), an operator 320 consisting of two transistors (2T), and a gate logic circuit 430. ) may be a multiplication cell implemented by combining. For example, the SRAM bit cell circuit 225 is connected to each of the four memory banks (Bank0, Bank1, Bank2, Bank3) connected to each of the 4-bit input signals (IN ₀ , IN ₁ , IN ₂ , IN ₃ ). It may include corresponding bit cells 310 and operators 320 corresponding to each of the bit cells 310.

The operator 320 may be composed of a two transistor (2T) circuit including a first transistor (N ₁ ) (321) and a second transistor (P ₁ ) (323). The first transistor 321 may correspond to, for example, an NMOS transistor, but is not necessarily limited thereto. Additionally, the second transistor 323 may correspond to a PMOS transistor, but is not necessarily limited thereto.

For example, the second value (e.g., input signal IN ₀ ) corresponding to the input signal of the target memory bank (e.g., memory bank 0 (Bank ₀ )) is the read word of the bit cell 310 corresponding to memory bank 0. It may be applied to the first gate terminal of the first transistor 321 and the second gate terminal of the second transistor 323 through the line RWL. The drain terminal of the first transistor 321 contains an inverted weight of the weight (W) stored in the bit cell 310 belonging to memory bank 0, which is the target memory bank. ) value can be applied. The source terminal of the first transistor 321 may be connected to the input terminal of the gate logic circuit 430 via the drain terminal of the second transistor 323.

The output value of the first transistor 321 that passes through the first gate terminal of the first transistor 321 is connected to the output value of the second transistor 323 that passes through the second gate terminal of the second transistor 323, thereby performing a bitwise multiplication operation. It may be output as a signal (for example, O ₁ ) corresponding to the result.

Referring to FIG. 5B, a truth table showing the operation of the SRAM bitcell circuit 225 when memory bank 0 (Bank ₀ ) is the target memory bank in the in-memory computing (IMC) circuit shown in FIG. 5A. 530 is shown.

The headings of the columns in FIG. 5A may correspond to the same points/lines in the circuit of FIG. 5A.

For example, the input signal IN ₀ corresponding to memory bank 0 (Bank ₀ ) is '1', and corresponds to memory bank 1 (Bank ₁ ), memory bank 2 (Bank ₂ ), and memory bank 3 (Bank ₃ ), respectively. The input signals IN _1, IN _{2, and} IN ₃ may be '0'. In addition, if the weight (W) stored in the bit cell 310 of memory bank 0 (Bank ₀ ) is '1', the inverted weight ( ) may be '0'.

At this time, when the input signal IN ₀ of '1' is applied to the gate terminal of the first transistor 321 (NMOS transistor of memory bank 0 (Bank ₀ )), between the gate terminal and the source terminal of the first transistor 321 As a potential difference occurs, a channel is formed and the first transistor 321 can be turned 'ON'. When the first transistor 321 is 'ON', the inverted weight connected to the drain terminal of the first transistor 321 ( ) = '0' may be output as the output value (O ₀ ) of the bit cell 310 corresponding to memory bank 0 (Bank ₀ ). In addition, when the input signal IN ₀ of '1' is applied to the gate terminal of the second transistor 323, which is the PMOS transistor of memory bank 0 (Bank ₀ ), between the second gate terminal and the source terminal of the second transistor 323 Since no potential difference occurs, a channel is not formed and the second transistor 323 may be turned 'OFF'.

At this time, if the input signals IN _1, IN ₂ , and IN 3 corresponding to each of the non-target memory bank 1, memory bank 2, and memory bank ₃ are '0', memory bank 1 and memory bank 3 are inputted in the same manner as described above. 2, and the output value (O _1, ) of the operators 320 of the bit cells corresponding to memory bank 3 may be '1'. Accordingly, the output of the NAND gate 430 depends on the output O ₀ . Since the output value (O ₀ ) of the operators 320 of the bit cell 310 corresponding to memory bank 0 among the output values of the bit cells corresponding to each memory bank is '0', the output of the NAND gate 430 The value (O) can be '1'.

Alternatively, the input signal IN ₀ corresponding to memory bank 0 is '0', and the input signals IN _1, IN _{2, IN 3, corresponding to memory bank 1, memory bank 2,} and memory bank 3 _, respectively, are '0'. You can. Additionally, if the weight (W) stored in the bit cell 310 of memory bank 0 is '0', the inverted weight ( ) may be '1'.

When the input signal IN ₀ of '0' is applied to the gate terminal of the first transistor 321 (NMOS transistor of memory bank 0), a potential difference does not occur between the gate terminal and the source terminal of the first transistor 321, so the first 1 Since a channel is not formed at the terminal of the transistor 321, the first transistor 321 may be turned 'OFF'. In addition, when the input signal IN ₀ of '0' is applied to the gate terminal of the second transistor 323 (PMOS transistor of memory bank 0), the potential difference generated between the second gate terminal and the source terminal of the second transistor 323 Since a channel is formed by , the second transistor 323 can be turned 'ON'. When the second transistor 323 is 'ON', the output value (O ₀ ) of the operator 320 of the bit cell 310 corresponding to memory bank 0 is changed to the Vdd voltage applied to the source terminal of the second transistor 323. The corresponding '1' may be output.

When the input signals IN _1, IN 2, and IN 3 corresponding to each of memory bank 1, memory bank ₂ , and memory bank ₃ are '0', memory bank 1, memory bank 2, and memory are inputted in the same manner as described above. The output values (O ₁ ) of the bit cells corresponding to each of bank 3 may be '1'. If the output values of the bit cells corresponding to each memory bank are all '1', the output value (O) of the NAND gate 430 may be '0', and as a result, the same as performing the AND logic operation. You can get results.

In Figure 5a, the product operation between the input signal IN ₀ applied to the operator 320 corresponding to memory bank 0 connected to the input signal I0 and the weight (W) stored in the bit cell 310 is the weight stored in the bit cell 310 ( Inverted Weight of W) ( ) and the input signal IN ₀ can be performed through a pass transistor logic structure. Here, 'pass transistor logic' can be used to reduce the number of transistors to implement logic by driving the gate terminal, source terminal, and drain terminal using basic input. In complementary CMOS logic, the primary input can drive the gate terminal. Here, the primary input may correspond to, for example, input, inverting input, VDD, and GND.

As described above, Figure 5A shows an example of an AND function being implemented by an in-memory computing (IMC) circuit using NMOS pass transistors. When the gate input in the NMOS pass transistor is high, the left NMOS transistor, that is, the first transistor 321, is turned on, and the source input can be copied to the output. In contrast, when the gate input of the NMOS pass transistor is low, the right NMOS pass transistor, that is, the second transistor 323, is turned on and '0' can be transmitted to the output.

The truth table 530 shown in FIG. 5B may correspond to the truth table of the AND gate for verification of the above-described operation.

At this time, the input signal '1' is applied through the read word line (RWL) of the bit cells corresponding to the memory bank used for MAC operation, and the operation results of the bit cells belonging to the corresponding memory bank are transmitted to the adder (e.g., in FIG. 4). By being transmitted to the adder 440, it can be processed as if the corresponding memory bank has been selected. In contrast, the input signal '0' is applied to the read word line (RWL) of the bit cells corresponding to the memory bank that is not used for MAC operation, and the operation results of the bit cells belonging to the corresponding memory bank are not transmitted, thereby It can be treated as if the bank was not selected.

In one embodiment, a bitwise product operation is performed using the gate logic circuit 430 (e.g., NAND gate) consisting of two transistors even without a separate read word line (RWL) control signal to read the input signal IN _0. Therefore, the number of control lines of the interface is 4 per bit cell 310 (e.g., Write Bit Line (WBL), Write Word Line (WWL), Write Bit line inverted (WWBL), and Read Word Line (RWL). ) can be reduced to

Therefore, the total number of transistors constituting the in-memory computing (IMC) circuit is 4 banks x (SRAM bit cell (8T) + operator (2T)) + gate logic circuit (8 T) = 4 , and the total number of control lines can be 4 banks x 4 = 16. In FIG. 5, the output value (O0) of the product operation of the bit cell 310 corresponding to memory bank 0 connected to the input signal IN ₀ is sent to the NAND gate 430 together with the output values (O1) of the product operation of other bit cells. It can be delivered. The NAND gate 430 transfers the result (O) of performing a NAND logic operation on the output values (O ₀ and O ₁ ) of the four bit cells as shown in the truth table 530 to the input of the adder 230, thereby performing MAC Calculations can be performed.

FIGS. 6A and 6B are diagrams to explain how an in-memory computing (IMC) circuit selects a memory bank according to an embodiment. Referring to FIG. 6A, according to one embodiment, memory bank 0 (Bank ₀ ) 610 of the in-memory computing (IMC) circuit is selected as the target memory bank, and memory bank 1 of the in-memory computing (IMC) circuit is selected as the target memory bank. A case where (Bank ₁ ) 630 is not selected as the target memory bank is shown. FIG. 6B shows a truth table 650 with input and output values of the in-memory computing (IMC) circuit of FIG. 6A. In FIG. 6A, V _DD may represent a power supply voltage.

As shown in Figure 6a, the weight (W) stored in the bit cell of memory bank 0 (610) selected as the target memory bank is '0', and is applied as the input signal (IN ₀ ) of memory bank 0 through the word line. If the value is '1', the output (O ₀ ) value corresponding to memory bank 0 may be '1'. If the output (O ₀ ) value of the bit cell corresponding to memory bank 0 (e.g., one of (O _0, O ₁ ) of the bit cell input to the NAND gate) is '1', the output value of the NAND gate ( Since O) is '0', it does not affect the MAC operation in the adder 230.

That is, when the corresponding bit cell units of other memory banks (e.g., memory bank 1, memory bank 2, memory bank 3) have an input of “0”, each bit cell operator all inputs “1” to the NAND gate. Print out. Therefore, the output of the NAND gate can be determined by the output of the bit cell units of memory bank 0 (610). The weights of other memory banks (e.g., memory bank 1, memory bank 2, memory bank 3) cannot affect the output of the NAND gate. In other words, since only the bit cell unit in memory bank 0 has an input of "1", the bit cell unit in memory bank 0 is the only one of the four bit cell units whose weight W can affect the output of the NAND gate. It can be a bit cell unit.

When the weight (W) stored in the bit cell corresponding to memory bank 0 (610) is '1' and the value applied to the input signal (IN ₀ ) of memory bank 0 (610) through the word line is '1'. , the output (O ₀ ) value corresponding to memory bank 0 may be '0'. When the output (O ₀ ) value of the bit cell corresponding to memory bank 0, which is one of the output values (O _0, O ₁ ) of the bit cells corresponding to each memory bank, is '0', the output value of the NAND gate Since (O) becomes '1', it may affect the MAC operation in the adder 230. In this way, since the output corresponding to the memory bank to which the input signal '1' is applied affects the MAC operation in the adder 230, in one embodiment, the input through RWL (Read Word Line) is performed without a separate control signal. Application of a signal can cause the target memory bank (e.g., memory bank 0) to act as if it has been selected for MAC operation.

Or, for example, as shown in the figure 600, the weight (W) stored in the bit cell corresponding to memory bank 1 is '1', and the value applied to the input signal (IN ₃ ) of memory bank 1 through the word line is If it is '0', the output (O ₁ ) value corresponding to memory bank 1 is '1' (e.g., has a high level high value), so the MAC operation in the adder 230 is the output of the NAND gate. may not be affected.

In summary, among the bit cell groups of each memory bank, each bit cell has its own respective operator (eg, bit multiplier). A “deactivation” or “control” input signal (“0”) may be supplied to bit cell units of a memory bank that are not subject to operation. These signals may be provided by the memory bank's targeting/selection circuitry rather than actual input data signals. The actual input data signal may be supplied to the bit cell unit of the memory bank that is currently the target of operation. If the data input is "0", the operation result/output is "0", but if the data input is "1", the operation result may vary depending on the value (e.g. weight bit) stored in the target bit cell. If the weight bit value stored in the target bit cell is “1”, the operation result may be “1”, and if the weight bit value stored in the target bit cell is “0”, the operation result may be “0”.

FIG. 7 is a diagram illustrating the operation of an in-memory computing (IMC) circuit when the operator is composed of three transistors, according to an embodiment. Referring to FIG. 7, according to one embodiment, a bit cell 310 and bit cells corresponding to each of four memory banks connected to each of the input signals (I _0, I ₁ , I ₂ , I ₃ ) A diagram 700 is shown showing the structure of an in-memory computing (IMC) circuit including an SRAM bit cell circuit including an operator 710 and a gate logic circuit 430 (e.g., a NAND gate).

The operator 710 may be composed of a three transistor (3T) circuit including a transmission gate 711 and a third transistor 713. The third transistor 713 may correspond to, for example, a PMOS transistor, but is not necessarily limited thereto.

A second value (e.g., input signal I ₀ ) corresponding to the input signal of the target memory bank (e.g., memory bank 0) is transmitted to the transmission gate 711 through the read word line (RWL) of the bit cell corresponding to memory bank 0. It can be applied to the enable (E) terminal of and the gate terminal ('third gate terminal') of the third transistor 713.

In addition, the input (In) terminal of the transmission gate 711 contains an inverted weight (Inverted Weight) of the weight (W) stored in the bit cell 310 belonging to memory bank 0, which is the target memory bank. ) may be approved. Inverted input of the bit cell 310 ( ) is the enable bar ( ) terminal and the source terminal of the third transistor 713.

The output value of the transmission gate 711 and the output value of the third transistor 713 that passed through the third gate terminal of the third transistor 713 are each connected to the input of the NAND gate 430 to produce a signal corresponding to the result of the bitwise product operation. It can be output as .

For example, as shown in table 730, the weight (W) stored in the bit cell 310 of memory bank 0 is '1', the input signal I ₀ corresponding to memory bank 0 is '1', Input signals I _1, I 2, and I 3 corresponding to memory bank 1, memory bank ₂ , and memory bank 3 _, respectively, may be '0'.

At this time, when the input signal I ₀ of '1' is applied to the enable terminal of the transmission gate 711, the transmission gate 711 functions as a 'closed' switch, so the input of the transmission gate 711 Inverted weight connected to the terminal ( ) The value '0' can be output to the output terminal of the transmission gate 711. In addition, as the input signal I ₀ = '1' is applied to the gate terminal of the third transistor 713, the inverted input connected to the source terminal of the third transistor 713 ( ) = '0' may be output as the output value of the third transistor 713.

Since both the output value ('0') output from the transmission gate 711 and the output value ('0') of the third transistor 713 are '0', the output value of the bit cell 310 corresponding to memory bank 0 ( O ₀ ), '0' can be output. Since the output value (O ₀ ) of the operator 710 corresponding to memory bank 0 among the output values of the bit cells corresponding to each memory bank is '0', the output value (O) of the NAND gate 430 is '1''It can be.

In the in-memory computing (IMC) circuit structure shown in FIG. 7, when the input signal is '1', the data stored in the bit cell ( ) Since the value is transmitted through the transmission gate 711 that operates as a switch, it can be operated at a lower voltage than the in-memory computing (IMC) circuit structure shown in FIG. 5.

Additionally, the total number of transistors constituting a unit bit cell of the in-memory computing (IMC) circuit shown in FIG. 7 is 4 bank x (SRAM bit cell (8T) + operator (3T)) + gate logic circuit. (430)(8T NAND gate) = 4 It could be a dog.

FIG. 8 is a diagram for explaining the operation of an in-memory computing (IMC) circuit when the operator is composed of three transistors according to another embodiment. Referring to FIG. 8, according to one embodiment, a bit cell 310 and a bit cell 310 corresponding to each of four memory banks connected to each of the input signals (I _0, I _1, I _2, I ₃ ). A diagram 800 is shown showing the structure of an in-memory computing (IMC) circuit including a gate logic circuit 430 and an SRAM bit cell circuit including an operator 810 corresponding to each.

The operator 810 may be composed of a three-transistor (3T) circuit including a transmission gate 811 and a fourth transistor 813 in which an NMOS transistor and a PMOS transistor are connected in parallel. The transmission gate 811 can be switched on or off by the input I applied to the gate of each transistor. The fourth transistor 813 may correspond to, for example, a PMOS transistor, but is not necessarily limited thereto.

A second value (e.g., input signal I ₀ ) corresponding to the input signal of the target memory bank (e.g., memory bank 0) is transmitted to the transmission gate 811 through the read word line (RWL) of the bit cell corresponding to memory bank 0. It can be applied to the enable (E) terminal of and the gate terminal ('fourth gate terminal') of the fourth transistor 813.

In addition, the input (In) terminal of the transmission gate 811 contains an inverted weight (Inverted Weight) of the weight (W) stored in the bit cell 310 belonging to memory bank 0, which is the target memory bank. ) may be approved. Inverted input of the bit cell 310 ( ) is the enable bar ( ) can be connected to the terminal.

The source terminal of the fourth transistor 813 is connected to Vdd, and the drain terminal of the fourth transistor 813 is the inverted weight (W) of the weight (W) stored in the bit cell 310. ) can be connected to.

The output value of the transmission gate 811 and the output value of the fourth transistor 813 that passed through the fourth gate terminal of the fourth transistor 813 are each connected to the input of the NAND gate 430 to produce a signal corresponding to the result of the bitwise product operation. It can be output as .

For example, as shown in table 830, the weight (W) stored in the bit cell 310 of memory bank 0 is '1', the input signal I ₀ corresponding to memory bank 0 is '1', Input signals I _1, I 2, and I 3 corresponding to memory bank 1, memory bank ₂ , and memory bank 3 _, respectively, may be '0'.

At this time, when the input signal I ₀ of '1' is applied to the enable (E) terminal of the transmission gate 811, the transmission gate 811 functions as a 'closed' switch, so the transmission gate 811 ) connected to the input terminal of the inverted weight ( ) The value '0' can be output to the output terminal of the transmission gate 811. In addition, when the input signal I ₀ = '1' is applied to the gate terminal of the fourth transistor 813, no potential difference occurs between the gate terminal ('fourth gate terminal') and the source terminal of the fourth transistor 813. Therefore, a channel is not formed and the fourth transistor 813 may be turned 'OFF'. Accordingly, the output value of the fourth transistor 813 may be '0'.

Since the output value ('0') output from the transmission gate 811 and the output value ('0') of the fourth transistor 813 are both '0', the operator 810 of the bit cell 310 corresponding to memory bank 0 '0' may be output as the output value (O ₀ ). Since the output value (O ₀ ) of the operator 810 of the bit cell 310 corresponding to memory bank 0 among the output values of the bit cells corresponding to each memory bank is '0', the output value of the NAND gate 430 (O) can be '1'.

Figure 9 is a block diagram of a neural network device including an in-memory computing (IMC) circuit according to one embodiment. Referring to FIG. 9, the neural network device 900 according to one embodiment includes an array circuit 910 and a controller 930.

Array circuitry 910 includes in-memory computing (IMC) circuits 915 . Each of the in-memory computing (IMC) circuits 915 includes a first value stored in each of the bit cells corresponding to the corresponding memory bank among the plurality of memory banks. Operators that output signals corresponding to calculation results between second values are provided corresponding to each bit cell. Each of the in-memory computing (IMC) circuits 915 may include a SRAM bitcell circuit containing operators, and a gate logic circuit. Each of the in-memory computing (IMC) circuits 915 may correspond to the in-memory computing (IMC) circuit described above with reference to FIGS. 2 to 8 .

The SRAM bit cell circuit includes bit cells corresponding to a plurality of memory banks, and the bit cells may be connected to a word line of the SRAM for each memory bank.

Operators may output signals corresponding to operation results corresponding to each bit cell. The operators calculate the result of a bit-wise multiplication between the first value stored in each of the bit cells corresponding to the corresponding memory bank among the plurality of memory banks and the second value applied as the input signal of the corresponding memory bank through the word line. It may include a plurality of transistors that output signals corresponding to . Each of the operators may be composed of two transistor (2T) circuits, or three transistor (3T) circuits.

For example, each of the calculators may be composed of a two transistor (2T) circuit including a first transistor and a second transistor. In this case, the second value corresponding to the input signal of the corresponding memory bank may be applied to the first gate terminal of the first transistor and the second gate terminal of the second transistor. Additionally, the output value of the first transistor that passes through the first gate terminal can be connected to the output value of the second transistor that passes through the second gate terminal, thereby outputting a signal corresponding to the result of the bitwise product operation.

Alternatively, each of the operators may be composed of a three transistor (3T) circuit including a transmission gate and a third transistor. In this case, the second value corresponding to the input signal of the corresponding memory bank may be applied to the enable terminal of the transmission gate and the third gate terminal of the third transistor. The output value of the transmission gate may be connected to the output value of the third transistor through the third gate terminal and output as a signal corresponding to the result of the bitwise multiplication operation.

The gate logic circuit (or logic gates) may transfer the operation result corresponding to each bit cell belonging to the target memory bank to an adder for MAC operation. Each of the in-memory computing (IMC) circuits 915 may correspond to the in-memory computing (IMC) circuit described above with reference to FIGS. 3 to 8 .

The controller 930 inputs second values corresponding to the input signal of the neural network device 900 to each of the in-memory computing (IMC) circuits 915 according to the clock signal, and performs the in-memory computing (IMC) circuits 915. Each of the circuits 915 can be controlled.

The controller 930 includes, for example, an input feature map (IFM) buffer 931 that stores an input feature map including second values, and in-memory computing (IMC) circuits ( 915) It may include at least one of a control circuit 933 that controls whether to apply the second values to each, and a read write (RW) circuit 935 that reads or writes the first values.

The control circuit 933 can control whether to apply a second value to a plurality of transistors included in the operators so that the gate logic circuit transmits the operation result corresponding to each bit cell in the corresponding memory bank to the adder. there is.

Although the IMC device is described above with reference to neural network data such as weights, input data/maps, etc., the IMC device is not limited to any particular type of data. In other words, circuits and devices can be novel and beneficial, regardless of the type of data they are used to process. Neural network data processing is just one of many potential applications.

Figure 10 is a block diagram of an electronic system including a neural network device according to one embodiment. Referring to FIG. 10, the electronic system 1000 according to one embodiment extracts valid information by analyzing input data in real time based on a neural network (e.g., the neural network 110 of FIG. 1), and extracts the extracted information. Based on this, the situation can be judged or the configurations of the electronic device on which the electronic system 1000 is mounted can be controlled. For example, the electronic system 1000 may include robotic devices such as drones, advanced driver assistance systems (ADAS), smart TVs, smartphones, medical devices, mobile devices, video display devices, measurement devices, and IoT devices. It can be applied to the like, and in addition, it can be mounted on at least one of various types of electronic devices.

The electronic system 1000 may include a processor 1010, random access memory (RAM) 1020, a neural network device 1030, a memory 1040, a sensor module 1050, and a transmission/reception module 1060. The electronic system 1000 may further include an input/output module, a security module, a power control device, etc. Some of the hardware components of the electronic system 1000 may be mounted on at least one semiconductor chip.

The processor 1010 controls the overall operation of the electronic system 1000. The processor 1010 may include one processor core (Single Core) or may include a plurality of processor cores (Multi-Core). The processor 1010 may process or execute programs and/or data stored in the memory 1040. In some embodiments, the processor 1010 may control the functions of the neural network device 1030 by executing programs stored in the memory 1040. The processor 1010 may be implemented as a Central Processing Unit (CPU), Graphics Processing Unit (GPU), or Application Processor (AP).

RAM 1020 may temporarily store programs, data, or instructions. For example, programs and/or data stored in the memory 1040 may be temporarily stored in the RAM 1020 according to the control or booting code of the processor 1010. The RAM 1020 may be implemented as a memory such as, for example, Dynamic RAM (DRAM) or Static RAM (SRAM).

The neural network device 1030 may perform a neural network operation based on received input data and generate various information signals based on the performance results. Neural networks may include, for example, Convolution Neural Network (CNN), Recurrent Neural Network (RNN), Fuzzy Neural Networks (FNN), Deep Belief Networks, Restricted Boltzman Machines, etc., but are not necessarily limited thereto. For example, the neural network device 1030 may be a neural network-specific hardware accelerator itself and/or a device including the same, or may correspond to the neural network device 900 described above with reference to FIG. 9 .

The neural network device 1030 controls the SRAM bitcell circuits of the in-memory computing (IMC) circuit to share and/or process the same input data, and selects at least some of the operation results output from the SRAM bitcell circuits. can do.

Here, the 'information signal' may include one of various types of recognition signals, such as, for example, a voice recognition signal, an object recognition signal, an image recognition signal, a biometric information recognition signal, etc. For example, the neural network device 1030 may receive frame data included in a video stream as input data and generate a recognition signal for an object included in the image represented by the frame data from the frame data. The neural network device 1030 may receive various types of input data depending on the type or function of the electronic system on which the electronic system 1000 is mounted, and may generate a recognition signal according to the input data.

The memory 1040 is a storage location for storing data and can store an operating system (OS), various programs, and various data. In an embodiment, the memory 1040 may store intermediate results generated during the operation of the neural network device 1030.

The memory 1040 may include at least one of volatile memory or non-volatile memory. Non-volatile memory includes, for example, Read Only Memory (ROM), Programmable Read Only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), and flash memory. It may include, but is not necessarily limited to this. Volatile memory includes, for example, Dynamic RAM (DRAM), Static RAM (SRAM), SDRAM, Phase Change Memory RAM (PRAM), Magnetoresistive RAM (MRAM), Resistive RAM (RRAM), and/or Ferroelectric RAM (FRAM), etc. It may include, but is not necessarily limited to this. Depending on the embodiment, the memory 1040 may include a Hard Disk Drive (HDD), Solid State Driver (SSD), Compact Flash (CF) card, Secure Digital (SD) card, Micro-SD, Mini-SD, or Xd Picture Card ( It may include at least one of an extreme Digital Picture Card or a Memory Stick.

The sensor module 1050 may collect information around electronic devices on which the electronic system 1000 is mounted. The sensor module 1050 can sense or receive signals (e.g., video signals, audio signals, magnetic signals, biological signals, touch signals, etc.) from outside the electronic system 1000, and convert the sensed or received signals into data. there is. The sensor module 1050 is at least one of various types of sensing devices, such as a microphone, an imaging device, an image sensor, a LIDAR (light detection and ranging) sensor, an ultrasonic sensor, an infrared sensor, a biosensor, and a touch sensor. may include.

The sensor module 1050 may provide converted data to the neural network device 1030 as input data. For example, the sensor module 1050 may include an image sensor, capture the external environment of the electronic system 1000, generate a video stream, and transmit successive data frames of the video stream to the neural network device 1030. Input data can be provided in order. However, it is not limited to this, and the sensor module 1050 can provide various types of data to the neural network device 1030.

The transmitting/receiving module 1060 may be equipped with various wired or wireless interfaces capable of communicating with external devices. For example, the transmitting and receiving module 1060 may be connected to a wired local area network (LAN), a wireless local area network (WLAN) such as Wi-fi (Wireless Fidelity), or a wireless personal communication network (Wireless) such as Bluetooth. Personal Area Network (WPAN), Wireless USB (Wireless Universal Serial Bus), Zigbee, NFC (Near Field Communication), RFID (Radio-frequency identification), PLC (Power Line communication), or 3G (3rd Generation), 4G (4th) Generation), LTE (Long Term Evolution), and other communication interfaces that can be connected to mobile cellular networks.

Figure 11 is a flowchart showing a method of operating an in-memory computing (IMC) circuit according to an embodiment. In the following embodiments, each operation may be performed sequentially, but is not necessarily performed sequentially. For example, the order of each operation may be changed, and at least two operations may be performed in parallel.

Referring to FIG. 11, an in-memory computing (IMC) circuit according to an embodiment may perform a MAC operation by transferring the operation result corresponding to each bit cell to an adder through steps 1110 to 1140. there is. In-memory computing (IMC) circuitry may include SRAM bitcell circuitry and gate logic circuitry. For example, the SRAM bit cell circuit may include bit cells corresponding to a plurality of memory banks and operators that output signals corresponding to operation results corresponding to each of the bit cells. At this time, the bit cells may be connected to the word line of the SRAM for each memory bank. For example, the in-memory computing (IMC) circuit may correspond to the in-memory computing (IMC) circuit described above with reference to FIGS. 2 to 9, but is not necessarily limited thereto.

At step 1110, the in-memory computing (IMC) circuit stores a first value in each of the bit cells corresponding to the plurality of memory banks of the SRAM bitcell circuit. An in-memory computing (IMC) circuit can store a first value in each bit cell using a read write (RW) circuit.

In step 1120, the in-memory computing (IMC) circuit applies a second value as an input signal to a target memory bank for MAC operation among a plurality of memory banks through the word line of static random access memory (SRAM). . At this time, the second value is read by the in-memory computing (IMC) circuit from, for example, an input feature map stored in an input feature map (IFM) buffer through an input driver. It may be, but is not necessarily limited to this.

In step 1130, the in-memory computing (IMC) circuit corresponds to each of the bit cells by operators and outputs a signal corresponding to the result of a multiplication operation between the first value and the second value. The operators may include a plurality of transistors that output signals corresponding to the results of the multiplication operation. The in-memory computing (IMC) circuit uses a bit wise ( A signal corresponding to the bit-wise) product operation result can be output through operators.

In step 1140, the in-memory computing (IMC) circuit transfers the operation result corresponding to each of the bit cells belonging to the target memory bank to the adder through the gate logic circuit so that the adder performs a sum operation on the operation result. . The adder may correspond to, for example, the adder 230 of FIG. 2, the adder 230 of FIG. 3, and/or the adder 230 of FIG. 4. Afterwards, the adder may perform a sum operation on the operation results received through step 1140 and store the sum operation result in the accumulation operator. The accumulation operator may correspond to, for example, the accumulation operator 240 of FIGS. 2A to 2D or FIG. 3 .

The neural network, neural network device, electronic system, IMC macro, IMC circuit, IMC device, memory, storage device, and components described in FIGS. 1 to 11 are collectively composed of components or represent hardware components. You can. For example, the devices, methods, and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, and a field programmable gate (FPGA). It may be implemented using a general-purpose computer or a special-purpose computer, such as an array, programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and software applications running on the operating system. Additionally, a processing device may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, a single processing device may be described as being used; however, those skilled in the art will understand that a processing device includes multiple processing elements and/or multiple types of processing elements. It can be seen that it may include. For example, a processing device may include multiple processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are possible.

Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing unit to operate as desired, or may be processed independently or collectively. You can command the device. Software and/or data may be used on any type of machine, component, physical device, virtual equipment, computer storage medium or device to be interpreted by or to provide instructions or data to a processing device. , or may be permanently or temporarily embodied in a transmitted signal wave. Software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored on a computer-readable recording medium.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. A computer-readable medium may include program instructions, data files, data structures, etc., singly or in combination, and the program instructions recorded on the medium may be specially designed and constructed for the embodiment or may be known and available to those skilled in the art of computer software. It may be possible. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. -Includes optical media (magneto-optical media) and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, etc. Examples of program instructions include machine language code, such as that produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

The hardware devices described above may be configured to operate as one or multiple software modules to perform the operations of the embodiments, and vice versa.

As described above, although the embodiments have been described with limited drawings, those skilled in the art can apply various technical modifications and variations based on this. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent. Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

200: IMC macro
210: Write Word Line (WWL) driver
220: In-memory computing (IMC) circuit
230: adder
240: Accumulative operator
250: input driver (or read word line driver (RWL) driver)
260: memory controller
270: Write Bit Line (WBL) driver

Claims (20)

In an in-memory computing circuit,
a plurality of memory banks; and
A logic gate that receives the logical operation results of each of the memory banks
Including,
Each of the memory banks is
Bit cells that store weights; and
Operator that receives input values
Including,
The calculator is
comprising a two transistor (2T) circuit including a first transistor and a second transistor,
The input value is applied to the first gate terminal of the first transistor and the second gate terminal of the second transistor, and the output value of the first transistor that passes through the first gate terminal is the second gate terminal of the second transistor. 2 An in-memory computing circuit in which the operator, which is connected to the bit cell and receives the input value by being connected to the output value of a transistor, outputs a result of a logical operation between the input value and the weight. According to paragraph 1,
An in-memory computing circuit, wherein the logical operation result of each of the memory banks is a NAND operation value for the input value and the weight. According to paragraph 1,
An in-memory computing circuit, wherein the logic gate is a NAND gate. According to paragraph 1,
The logic gate is
An in-memory computing circuit that outputs a multiplication result between an input value of one selected memory bank among the memory banks and a weight. According to paragraph 4,
An in-memory computing circuit, wherein each of the unselected memory banks receives an input value of 0. According to paragraph 1,
Adder connected to the logic gate
An in-memory computing circuit further comprising: According to paragraph 1,
The calculator is
A plurality of transistors that output a signal corresponding to the result of a bit-wise product operation
In-memory computing circuitry comprising: delete According to paragraph 1,
A value based on the weight stored in the bit cell is applied to the drain terminal of the first transistor,
The source terminal of the first transistor is
An in-memory computing circuit connected to the input terminal of the logic gate through the drain terminal of the second transistor. According to paragraph 1,
The first transistor includes an NMOS transistor,
In-memory computing circuit, wherein the second transistor includes a PMOS transistor. In an in-memory computing circuit,
a plurality of memory banks; and
A logic gate that receives the logical operation results of each of the memory banks
Including,
Each of the memory banks is
Bit cells that store weights; and
Operator that receives input values
Including,
The calculator is
It includes a three transistor (3T) circuit including a transmission gate and a third transistor,
The input value is applied to an enable terminal of the transmission gate and a third gate terminal of the third transistor,
The output value of the transmission gate and the output value of the third transistor that passed through the third gate terminal are each connected to the input of the logic gate and thus connected to the bit cell, so that the operator receiving the input value calculates the input value and the weight. An in-memory computing circuit that outputs the results of logical operations between nodes. According to clause 6,
The logic gate is
An in-memory computing circuit that transfers the logical operation result corresponding to the bit cell to the adder, depending on whether the input value is applied to the operator. According to claim 1,
The in-memory computing circuit,
Mobile device, mobile computing device, mobile phone, smartphone, personal digital assistant, fixed location terminal, tablet computer, computer, wearable device, laptop computer, server, music player, video player, entertainment unit , in-memory computing, integrated into at least one device selected from the group consisting of navigation devices, communication devices, navigation devices, GPS devices, televisions, tuners, automobiles, vehicle components, avionics systems, drones, multicopters, and medical devices. Circuit. In a neural network device including in-memory computing circuitry,
an array circuit including in-memory computing circuits; and
A controller that inputs second values corresponding to the input signal of the neural network device to each of the in-memory computing circuits according to a clock signal and controls the in-memory computing circuits.
Including,
Each of the in-memory computing circuits
comprising a plurality of memory banks,
Each of the memory banks is
A bit cell that stores weights and an operator that receives input values; and
A logic gate that receives the logical operation results of each of the memory banks
Includes,
The calculator is
comprising a two transistor (2T) circuit including a first transistor and a second transistor,
The input value received by the operator is applied to the first gate terminal of the first transistor and the second gate terminal of the second transistor, and the output value of the first transistor after passing through the first gate terminal is applied to the second gate terminal. A neural network device in which the operator, which is connected to the bit cell and receives the input value by being connected to the output value of the second transistor that has passed through, outputs a result of a logical operation between the input value and the weight. According to clause 14,
A neural network device wherein the logical operation result of each of the memory banks is a NAND operation value for the input value and the weight. According to clause 14,
A neural network device, wherein the logic gate is a NAND gate. According to clause 14,
The controller is
an input feature map (IFM) buffer that stores an input feature map including the input values;
a control circuit that controls whether the input value is applied to the plurality of IMC circuits; and
RW (read write) circuit that reads or writes the weights
A neural network device comprising at least one of the following: An in-memory computing device, comprising:
memory banks each containing a respective bit cell unit;
a logic gate receiving outputs of operators of each bit cell unit; and
An adder that receives the output of the logic gate to perform at least a portion of the MAC operation.
Including,
Each bit cell unit is
comprising a bit cell and an operator, none of the bit cells sharing the same operator,
The calculator is
comprising a two transistor (2T) circuit including a first transistor and a second transistor,
The input value received by the operator is applied to the first gate terminal of the first transistor and the second gate terminal of the second transistor, and the output value of the first transistor after passing through the first gate terminal is applied to the second gate terminal. An in-memory computing device in which the operator, which is connected to the bit cell and receives the input value by being connected to the output value of the second transistor that has passed through, outputs a result of a logical operation between the input value and the weight. According to clause 18,
The output of each bit cell unit is connected to the logic gate,
Each of the bit cells stores a respective stored value,
The bit cell units are connected to respective input lines that provide respective input values to the bit cell units,
The in-memory computing device is
An in-memory computing device wherein input values provided to the bit cell units select one of the bit cell units to be the target of an operation to be performed on the stored value by a corresponding operator. According to clause 19,
The stored values of the bit cell units that are not the target of the operation do not affect the output of the logic gate.

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