KR20130107065A - Nonvolatile memory device and method fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method for manufacturing the same, which can realize a high speed, low voltage, high performance, and highly integrated multi-bit volatile memory device while simplifying a manufacturing process.
In one example, a semiconductor substrate; A tunnel oxide film formed on the semiconductor substrate; A charge trap layer having a first region and a second region spaced apart from each other on the tunnel oxide layer and formed of a nano adsorption material; A blocking oxide film formed on the charge trap layer; And a gate electrode formed on the blocking oxide film.

Description

Nonvolatile memory device and method of manufacturing the same {Nonvolatile memory device and method fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method for manufacturing the same, and more particularly, to a nonvolatile memory device and a method for manufacturing the same, which can realize a high speed, low voltage, high performance, and highly integrated multi-bit volatile memory device while simplifying a manufacturing process. It is about.

Recently, as the demand for portable information devices such as smartphones and tablet PCs increases rapidly, nano-sized nonvolatile memory (MVM) capable of securing ultra-high density (terabit), ultra-small, ultra-fast, and high reliability Device development is required. However, due to the limitations of fine process technology, increasing memory density faces limitations.

Currently, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory devices, which are compatible with existing processes and exhibit high performance memory characteristics, are becoming a realistic alternative as the next generation of flash memory. Methods of increasing the same memory capacity are being developed.

US Patent No. 6, 670, 669, issued by Shoichi Kawamura et al., Filed February 28, 2000, using the SONOS structure, has a multi-cell of 1-cell in "MULTIPLE-BIT NON-VOLATILE MEMORY UTILIZING NON-CONDUCTIVE TRAPPING GATE." A bit operated nonvolatile memory is disclosed.

The above-described multi-bit operating nonvolatile memory maintains a conventional planar-type SONOS structure, while reverse and forward reading of locally injected charges into the nitride layer near the source and drain junctions. forward read). In this case, the program uses a hot carrier injection method to locally inject charges, and the erase uses a hot hole injection method.

This multi-bit technology is expected to be used in 3D NAND structure, so the market is very large. However, in the conventional multi-bit device, the locally-injected charge is mixed with the storage spaces of the bit 1 (source) and the bit 2 (drain) due to lateral diffusion, which causes errors in read operations due to noise. I have a problem.

In addition, in a multi-bit device, the programming method uses high-temperature charge injection generated in a source or drain junction depletion region, and in a device having a short channel length, the depletion region is insignificant so it is easy to inject charge into a local area. In addition, there is a problem in reliability because a mismatch occurs in which the high temperature electron injection space does not coincide with the high temperature hole injection space.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device and a method of manufacturing the same, which can realize a high speed, low voltage, high performance, and highly integrated multi-bit volatile memory device while simplifying a manufacturing process.

A nonvolatile memory device according to an embodiment of the present invention for achieving the above object is a semiconductor substrate; A tunnel oxide film formed on the semiconductor substrate; A charge trap layer having a first region and a second region spaced apart from each other on the tunnel oxide layer and formed of a nano adsorption material; A blocking oxide film formed on the charge trap layer; And a gate electrode formed on the blocking oxide film.

The nano adsorption material may be carbon nanotubes or graphene.

The blocking oxide layer may contact the tunnel oxide layer exposed to the spaced space between the first region and the second region.

The width of the separation space between the first area and the second area may be greater than the width of each of the first area and the second area.

In addition, a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention for achieving the above object comprises a substrate preparation step of preparing a substrate on which a tunnel oxide film material is deposited; A photoresist pattern layer forming step of forming a photoresist pattern layer on the tunnel oxide film material; A first nanomaterial region and a second nanomaterial region are formed on both sides of the tunnel oxide layer based on the photoresist pattern layer by dipping the semiconductor substrate into a solution in which nano-adsorbent materials are dispersed. A nano pattern layer forming step of removing the pattern layer; Depositing a blocking oxide material and a gate electrode material to deposit a blocking oxide material and a gate electrode material on the nanopattern layer; And etching the tunnel oxide layer material, the nano pattern layer, the blocking oxide layer material, and the gate electrode material to form a tunnel oxide layer, a charge trap layer, a blocking oxide layer, and a gate electrode.

In the forming of the nanopattern layer, a third nanomaterial region may be formed together on the photoresist pattern layer when the semiconductor substrate is dipped, and the third nanomaterial region may be removed together when the photoresist pattern layer is removed. have.

In the nano-pattern layer forming step, the photoresist pattern may be removed by a wet etching method.

In the nano-pattern layer forming step, the nano-adsorption material may be carbon nanotubes or graphene.

In the forming of the nanopattern layer, the semiconductor substrate may be taken out of the solution and then the nanoadsorption material may be adsorbed onto the tunnel oxide material and the photoresist pattern layer by a heat treatment method.

In the forming of the nanopattern layer, the blocking oxide material may be deposited to contact the tunnel oxide material exposed to the spaced space between the first nanomaterial region and the second nanomaterial region.

The nonvolatile memory device according to the embodiment of the present invention has a first region and a second region spaced apart from each other, and has a charge trap layer formed of a nano adsorption material such as carbon nanotubes or graphene, thereby reducing the channel length. Even in this case, it is possible to facilitate the injection of charge into the first region and the second region, which are local regions, and to prevent side diffusion of the charge.

Accordingly, in the nonvolatile memory device according to the embodiment of the present invention, the storage space of the first region and the second region is minimized to reduce the error of the read operation due to the cross talk and to reduce the electron injection space and the hole. By reducing the occurrence of mismatch phenomena in which the injection spaces do not match, it is possible to realize high speed, low voltage, high performance, and high density multi-bit volatile memory devices.

In addition, a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention is formed by using a dipping method of dipping a semiconductor substrate in a solution in which a nano-adsorbing material is dispersed and a photolithography method using a photoresist pattern spaced apart from each other It is possible to easily form a charge trap layer having a region and a second region.

Therefore, the manufacturing method of the nonvolatile memory device according to the embodiment of the present invention can simplify the manufacturing process.

1 is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention.
FIG. 2 is a plan view of a tunnel oxide film and a charge trap layer of the nonvolatile memory device of FIG. 1.
3 is a flowchart illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.
4A through 4H are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device of FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention, and FIG. 2 is a plan view of a tunnel oxide layer and a charge trap layer of the nonvolatile memory device of FIG. 1.

1 and 2, a nonvolatile memory device 100 according to an exemplary embodiment of the present invention may include a semiconductor substrate 110, a tunnel oxide film 120, a charge trap layer 130, a blocking oxide film 140, and the like. The gate electrode 150 is included.

The semiconductor substrate 110 may be a p-type or n-type Si semiconductor substrate or a III-V group compound semiconductor substrate doped with impurities. The semiconductor substrate 110 may include a source region 111 and a drain region 112 formed to have a predetermined thickness from an upper surface and spaced apart from each other by a predetermined distance. A channel region is formed between the source region 111 and the drain region 112.

The tunnel oxide layer 120 is formed on the semiconductor substrate 110. In detail, the tunnel oxide layer 120 is formed on the channel region of the semiconductor substrate 110. The tunnel oxide layer 120 tunnels the charge from the semiconductor substrate 110 to flow into the charge trap layer 130, and the charge introduced into the charge trap layer 130 from the gate electrode 150 is transferred to the semiconductor substrate 110. To prevent it from leaking. The tunnel oxide film 120 may be formed through a thermal oxidation process or a known thin film deposition process. For example, the tunnel oxide film 120 may be formed of a silicon oxide film (SiO ₂ ) having a thickness of several nm.

The charge trap layer 130 has a first region 131 and a second region 132 spaced apart from each other on the tunnel oxide layer 120, and is formed of a nano adsorption material. The nano adsorption material may be carbon nanotubes or graphenes having excellent electrical conductivity and capture ability. The charge trap layer 130 traps or emits electrons according to a voltage application condition of the gate electrode 150 to store a memory state. The first and second regions 131 and 132 spaced apart from each other divide the area of the charge trap layer 130 so that the charge is localized even if the channel length of the volatile memory device 100 is shortened. Make it easy to inject. Each of the first region 131 and the second region 132 operates independently by one bit according to a voltage application condition of the gate electrode 150, so that the nonvolatile memory device 100 operates in one cell to two bits. can do. Here, the width of the separation space between the first region 131 and the second region 132 may be larger than the width of each of the first region 131 and the second region 132. This is because the side diffusion of the charge injected into the first region 131 and the charge injected into the second region 132 of the nonvolatile memory device 100 stores the first region 131 and the second region 132. This is to minimize the mixing of the space to reduce the error of the read operation due to the cross talk and to reduce the occurrence of mismatch phenomenon in which the electron injection space and the hole injection space do not match.

In FIG. 1, although the charge trap layer 130 is illustrated as having two regions, the first region 131 and the second region 132 spaced apart from each other, the charge trap layer 130 may be formed to have two or more regions. . In this case, the nonvolatile memory device 100 may operate at 1 cell-2 bits or more.

The blocking oxide layer 140 is formed on the charge trap layer 130, and specifically, a tunnel oxide layer exposed to a space between the first region 131 and the second region 132 of the charge trap layer 130. It is formed to contact 120. The blocking oxide layer 140 prevents the charge injected into the first region 131 and the second region 132 of the charge trap layer 130 from leaking to the gate electrode 150. The blocking oxide layer 140 may include at least one of an insulating metal oxide, for example, an aluminum oxide layer (AlO), a lanthanum hafnium oxide layer (LaHfO), a lanthanum aluminum oxide layer (LaAlO), or a dysprosium scandium oxide layer (DyScO). have.

The gate electrode 150 is formed on the blocking oxide layer 140. The gate electrode 150 may be formed of any conductive material typically used as a gate electrode, such as polysilicon, a metal-silicide formed on polysilicon, a metal, or polysilicon. On the other hand, when a positive voltage is applied to the gate electrode 150 during programming of the nonvolatile memory device 100, electrons tunnel from the semiconductor substrate 110 to the tunnel oxide layer 120 to charge the layer 130. Is injected into. When a negative voltage is applied to the gate electrode 150 when the nonvolatile memory device 100 is erased, electrons trapped in the charge trap layer 130 are emitted to the semiconductor substrate 110. By this operation, the nonvolatile memory device 100 stores the memory state.

As described above, the nonvolatile memory device 100 according to an embodiment of the present invention has a first region 131 and a second region 132 spaced apart from each other, and is formed of a nano adsorption material such as carbon nanotubes or graphene. By providing a charge trap layer 130, the injection of charges into the first region 131 and the second region 132, which are local regions, can be facilitated even when the channel length is shortened, and the side diffusion of the charges can be prevented. can do.

Accordingly, the nonvolatile memory device 100 according to an embodiment of the present invention minimizes mixing of storage spaces of the first region 131 and the second region 132 so that the read operation is caused by noise. It is possible to reduce the error of and reduce the occurrence of mis match phenomenon in which the electron injection space and the hole injection space do not match.

Accordingly, the nonvolatile memory device 100 according to an embodiment of the present invention can implement a high speed, low voltage, high performance, and highly integrated multi-bit volatile memory device.

Next, a method of manufacturing the nonvolatile memory device 100 according to an embodiment of the present invention will be described.

3 is a flowchart illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention, and FIGS. 4A to 4H are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device of FIG. 3.

Referring to FIG. 3, a method of manufacturing a nonvolatile memory device 100 according to an embodiment of the present invention may include preparing a semiconductor substrate (S10), forming a photoresist pattern layer (S20), and forming a nanopattern layer (S30). ), A blocking oxide film material and a gate electrode material deposition step (S40), and a tunnel oxide film, a charge trap layer, a blocking oxide film, and a gate electrode forming step (S40).

Referring to FIG. 4A, the preparing of the semiconductor substrate S10 may include preparing the semiconductor substrate 110 on which the tunnel oxide film 120a is deposited on the entire surface. Since the semiconductor substrate 110 has been described above, duplicated descriptions will be omitted. Here, the deposition of the tunnel oxide material 120a may be performed using a thermal oxidation process or a known thin film deposition process.

Referring to FIG. 4B, the photoresist pattern layer forming step (S20) is a step of forming the photoresist pattern layer 10 on the tunnel oxide layer material 120a. The photoresist pattern layer 10 is patterned to correspond to the spaced space between the first region 131 and the second region 132 of the completed charge trap layer 130 shown in FIG. 4H.

4C to 4F, the nano pattern layer forming step (S30) may be performed by dipping the semiconductor substrate 110 into a solution 30 in which the nano-adsorbing material 40 is dispersed. The first nanomaterial region 131a and the second nanomaterial region 132a are formed on both sides of the photoresist pattern layer 10 and the photoresist pattern layer 10 is removed.

Specifically, the nano-pattern layer forming step (S30) is a nano-adsorption material 40, for example carbon nanotubes (Carbone) on the semiconductor substrate 110, the photoresist pattern layer 10 is formed as shown in Figure 4c nanotubes) or dipping into graphene (Graphene) dispersed solution. Here, the solution 30 may be an aqueous solution and is filled in the container 20 in advance.

In addition, the nano-pattern layer forming step S30 may include adsorbing the nano-adsorbing material 40 on the tunnel oxide film material 120a. Here, the adsorption of the nano-adsorption material 40 may be performed by removing the semiconductor substrate 110 from the solution 30 and then performing heat treatment by a heat treatment method. By the adsorption of the nano-adsorption material 40, the first nanomaterial region 131a and the second nanomaterial on both sides of the tunnel oxide film 120a based on the photoresist pattern 10 as shown in FIG. 4D. Region 132a is formed. Of course, the third nanomaterial region 133a is also formed on the photoresist pattern 10.

The nano-pattern layer forming step (S40) may be performed by dipping the semiconductor substrate 110 in the etching solution 60 filled in the container 50 by using a wet etching method as illustrated in FIG. 4E. ) Process. In this case, when the photoresist pattern layer 10 is removed, the third nanomaterial region 133a is also removed. Accordingly, as illustrated in FIG. 4F, the nano pattern layer 130b may be formed on the tunnel oxide layer 120a so that the first nanomaterial region 131a and the second nanomaterial region 132a are spaced apart from each other.

Referring to FIG. 4G, the blocking oxide film material and the gate electrode material deposition step (S50) is a step of depositing the blocking oxide film material 140a and the gate electrode material 150a on the nano pattern layer 130b. Here, the deposition of the blocking oxide material 140a is deposited to contact the tunnel oxide material 120a exposed to the spaced space between the first nanomaterial region 131a and the second nanomaterial region 132a.

Referring to FIG. 4H, the tunnel oxide layer, the charge trap layer, the blocking oxide layer, and the gate electrode forming step (S60) may include the tunnel oxide layer 120a, the nano pattern layer 130b, the blocking oxide layer 140a, and the gate electrode material ( The etching process 150a may be performed to form the tunnel oxide layer 120, the charge trap layer 130, the blocking oxide layer 140, and the gate electrode 150. The etching of the tunnel oxide material 120a, the nano pattern layer 130b, the blocking oxide material 140a, and the gate electrode material 150a may be performed by the gate electrode 150 on the channel region of the semiconductor substrate 110. Correspondence is made.

On the other hand, after the tunnel oxide film, the charge trap layer, the blocking oxide film, and the gate electrode forming step S60, impurity ions are implanted into both sides of the channel region of the semiconductor substrate 110 to form the source region 111 and the drain region 112. Is formed.

As described above, the manufacturing method of the nonvolatile memory device 100 according to the embodiment of the present invention is a dipping method for dipping the semiconductor substrate 110 in a solution in which the nano-adsorbing material is dispersed, and photolithography using the photoresist pattern 10. Using the method, the charge trap layer 130 having the first region 131 and the second region 132 which are formed to be spaced apart from each other can be easily formed.

Therefore, the manufacturing method of the nonvolatile memory device 100 according to the embodiment of the present invention can simplify the manufacturing process.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation and that those skilled in the art will understand that various modifications and equivalent arrangements may be made therein It will be possible.

100: nonvolatile memory device 110: semiconductor substrate
120: tunnel oxide film 130: charge trap layer
131: first region 132: second region
140: blocking oxide film 150: gate electrode

Claims (10)

A semiconductor substrate;
A tunnel oxide film formed on the semiconductor substrate;
A charge trap layer having a first region and a second region spaced apart from each other on the tunnel oxide layer and formed of a nano adsorption material;
A blocking oxide film formed on the charge trap layer; And
And a gate electrode formed on the blocking oxide film. The method of claim 1,
The nano-adsorption material is a carbon nanotube or graphene (graphene), characterized in that the nonvolatile memory device. The method of claim 1,
The blocking oxide layer is in contact with the tunnel oxide layer exposed to the spaced space between the first region and the second region. The method of claim 1,
The width of the separation space between the first region and the second region is greater than the width of each of the first region and the second region. Preparing a substrate on which a tunnel oxide material is deposited;
A photoresist pattern layer forming step of forming a photoresist pattern layer on the tunnel oxide film material;
A first nanomaterial region and a second nanomaterial region are formed on both sides of the tunnel oxide layer based on the photoresist pattern layer by dipping the semiconductor substrate into a solution in which nano-adsorbent materials are dispersed. A nano pattern layer forming step of removing the pattern layer;
Depositing a blocking oxide material and a gate electrode material to deposit a blocking oxide material and a gate electrode material on the nanopattern layer; And
And etching the tunnel oxide material, the nano pattern layer, the blocking oxide material, and the gate electrode material to form the tunnel oxide film, the charge trap layer, the blocking oxide film, and the gate electrode. The method of claim 5, wherein
In the forming of the nanopattern layer, when the semiconductor substrate is dipped, a third nanomaterial region is formed together on the photoresist pattern layer, and when the photoresist pattern layer is removed, the third nanomaterial region is removed together. Non-volatile memory device manufacturing method characterized in that. The method of claim 5, wherein
In the nano-pattern layer forming step, the photoresist pattern is removed by a wet etching method. The method of claim 5, wherein
In the nano-pattern layer forming step, the nano-adsorption material is a carbon nanotube or graphene (graphene) characterized in that the manufacturing method of the nonvolatile memory device. The method of claim 5, wherein
In the forming of the nano-pattern layer, the semiconductor substrate is removed from the solution, and then the nano-adsorption material is adsorbed onto the tunnel oxide material and the photoresist pattern layer by a heat treatment method. . The method of claim 5, wherein
In the forming of the nanopattern layer, the blocking oxide material is deposited to contact the tunnel oxide material exposed to the spaced space between the first nanomaterial region and the second nanomaterial region. .

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