KR20060038129A - 2 bit nonvolatile memory device fabrication method using double gate structure with asymmetric work function and its structure - Google Patents

Abstract

The present invention relates to a method of fabricating a nonvolatile memory and a structure thereof, and more particularly, to a method of fabricating a 2-bit nonvolatile memory using an asymmetric double gate structure having a different work function and a nonvolatile memory fabricated by the fabricating method. will be.

A method of manufacturing a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function according to the present invention includes: (a) sequentially forming a silicon substrate, a lower insulating film, silicon, and a hard mask; (b) forming a photoresist pattern on the substrate to form a pattern of a silicon fin on which a channel is to be formed and a silicon region on which a source / drain is to be formed in the silicon and the hard mask; (c) sequentially growing and depositing a tunneling dielectric layer, a floating gate, and a control dielectric layer to capture electrons; (d) after depositing the gate material, injecting different types of impurities into each gate of each of the silicon fins by adjusting an impurity implantation angle to form an asymmetric double gate; (e) patterning the gate region with a gate mask; (f) impurity implantation to form source / drain regions; And (g) separating the double gates bonded by chemical, mechanical polishing or anisotropic etching.

Fin Field Effect Transistor (CinFET), Chemical and Mechanical Polishing (CMP), Anisotropic Etching, Double Gate, Double Bit Non-Volatile Memory Device, Asymmetrical Work Function, Nanocrystal Floating Gate Memory.

Description

Non-Volatile Memory Structure for two Bits Cell Operation with Asymmetrical Work Function Double Gate and its Manufacturing}

1A is a process perspective view sequentially illustrating a method of fabricating a fin field transistor according to the prior art.

FIG. 1B is a cross-sectional view in the a-a 'direction of the device fabricated by the fabrication method shown in FIG. 1A.

2A is a process perspective view sequentially illustrating a method of forming an asymmetric double gate nonvolatile memory device having different work functions formed by implanting different types of impurities according to the present invention.

FIG. 2B is a cross-sectional view of the device fabricated by the fabrication method shown in FIG. 2A.

3 is a process perspective view illustrating a method of forming an asymmetric double gate nonvolatile memory device using metal having different work functions according to another embodiment of the present invention.

FIG. 4 illustrates the operation of a 2-bit memory cell using metal double gates having different types of impurity implants or different work functions of the present invention.

5 is a graph for explaining voltage and current characteristics with respect to a logic value.

***** Description of the symbols for the main parts of the drawings *****

101, 201, 301: lower insulating film

102, 202, and 302: silicon

103, 203, 303: hard mask

104: photoresist pattern

305: metal gate material

105, 209: gate material

206, 306: tunneling dielectric film

207, 307: floating gate

208, 308: control dielectric film

210: gate photoresist pattern

311, 312: metal gate material

The present invention relates to a method of fabricating a nonvolatile memory and a structure thereof, and more particularly, to a method of fabricating a 2-bit nonvolatile memory using an asymmetric double gate structure having a different work function and a nonvolatile memory fabricated by the fabricating method. will be.

Flash memory, which is a nonvolatile memory device that can electrically erase and program data, is highly integrated like DRAM. In addition, since the data is non-volatile and excellent in data retention, it can be replaced as an auxiliary memory in a system and can be applied to a DRAM interface.

Current flash cell technologies include a NOR type using a thermal electronic program method and an FN tunneling erase method, and a NAND type using an FN tunneling program and an erase method.

Flash memory for code storage is developed in accordance with the demand for high speed and low voltage, like DRAM and SRAM. However, due to the limitations of the program and erase operations, it is difficult to rapidly reduce the cell size and increase efficiency and high integration of the cell array.

Flash memory for data storage will evolve to increase densities to lower costs, which requires a multi-bit technology that can store more than two bits of data per cell.

As a method of storing data, a charge trapping type of metal nitride oxide semiconductor (MNOS), poly-silicon oxide nitride oxide semiconductor (SONOS), and metal oxide nitride oxide semiconductor (MONOS) is used to replace the existing floating gate type. The structure of the trapping type is under study.

As CMOS devices shrink, flash memory also shrinks in size for high performance and high integration. In this case, in the case of using the device structure of the existing two-dimensional channel, the limit of integration is reached due to a short channel effect such as an increase in leakage current due to size reduction.

In order to reduce such a short channel effect, a transistor structure using two or more gates has been proposed. This transistor structure maximizes the potential control of the channel by the gate voltage by placing the gate on the top / bottom or both sides of the channel instead of the two-dimensional structure in which the potential of the silicon channel is controlled by one gate electrode on the channel. It is a three-dimensional structure using silicon fins.

A 30-nm triple gate nonvolatile memory cell using a conventional multi-gate pin field effect transistor structure and a poly-silicon oxide nitride oxide semiconductor (SONOS) structure was fabricated and 1-bit operation was announced.

In addition, the operation of two-dimensional type double gate field effect transistor using different work functions is verified through simulation.

Hereinafter, a fin field effect transistor forming method according to the related art will be described with reference to the accompanying drawings.

1A is a process perspective view sequentially illustrating a method of fabricating a fin field transistor according to the prior art.

First, an SOI substrate having a structure 100A of a substrate (not shown), lower insulating film 101, and silicon 102 is prepared. Instead of the SOI substrate, any one of a silicon bulk substrate, a silicon germanium substrate, a tensile silicon, or a tensile silicon germanium substrate may be used.

Next, an oxidation process and a nitride film are formed at a temperature of 900 to 1100 ° C. to form a hard mask 103 for protecting the fin during the etching process for keeping the upper end of the fin flat or for gate region patterning (100B). ). Here, the hard mask 103 refers to a mask obtained by combining an oxide film and a nitride film generated by an oxidation process.

Next, the photoresist pattern 104 for the active region pattern is formed on the silicon 102 and the hard mask 103 (100C).

Next, the photoresist pattern 104 is used to form a pattern of the fin and the region where the source / drain is to be formed in the silicon 102 and the hard mask layer 103 (100D).

Next, a fin field effect transistor is fabricated by forming a gate dielectric layer 106, depositing a gate material 105, and forming a gate region through patterning (100E).

FIG. 1B is a cross-sectional view in the a-a 'direction of the device fabricated by the fabrication method shown in FIG. 1A. As shown in FIG. 1B, a fin field effect transistor having the same work function is formed in a conventional method of manufacturing a fin field effect transistor.

An object of the present invention for solving the above problems is to use a double gate structure having an asymmetric work function through the injection of different types of impurities or deposition of metal having different work functions to have different work functions. The present invention provides a method of manufacturing a nonvolatile memory device having a bit operation.

Another object of the present invention is to provide a method of fabricating a 2-bit nonvolatile memory device using a double gate structure capable of high density integration and having an asymmetric work function compatible with existing silicon device fabrication processes.

A method of manufacturing a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function according to the present invention includes: (a) sequentially forming a silicon substrate, a lower insulating film, a silicon and a hard mask layer; (b) forming patterns of silicon fins on which channels are to be formed and regions on which sources / drains are to be formed in the silicon and hardmask layers using photoresist patterns; (c) sequentially growing and depositing a tunneling dielectric layer, a floating gate, and a control dielectric layer to capture electrons; (d) after depositing the gate material, injecting different types of impurities into each gate of each of the silicon fins by adjusting an impurity implantation angle to form an asymmetric double gate; (e) patterning the gate region with a gate mask; (f) impurity implantation to form source / drain regions; And (g) separating the double gates joined by a chemical, mechanical polishing process or an anisotropic etching process.

In addition, a method of manufacturing a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function according to the present invention includes: (a) sequentially forming a silicon substrate, a lower insulating film, silicon, and a hard mask; (b) forming patterns of silicon fins on which channels are to be formed and regions on which sources / drains are to be formed in the silicon and hardmask layers using photoresist patterns; (c) sequentially growing and depositing a tunneling dielectric layer, a floating gate, and a control dielectric layer to capture electrons; (d) depositing obliquely depositing metals having different work functions on both sides of the silicon fin; (e) patterning the gate region with a gate mask; (f) impurity implantation to form source / drain regions; And (h) separating the double gates joined by a chemical, mechanical polishing process or an anisotropic etching process.

According to the configuration according to the present invention, unlike the conventional structure using a double gate having the same work function, gates having different work functions are formed through the injection of different types of impurities or deposition of metal having different work functions. This allows a single device to have two threshold voltages, resulting in a nonvolatile memory structure that exhibits two-bit operating characteristics.

Hereinafter, a method of manufacturing a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function and a structure thereof according to the present invention will be described in detail with reference to the accompanying drawings.

2A is a process perspective view sequentially illustrating a method of forming an asymmetric double gate nonvolatile memory device having different work functions formed by implanting different types of impurities according to the present invention.

The process from 100A to 100D shown in FIG. 1 is the same. That is, the substrate (not shown), the lower insulating film 101 and the silicon 102 are sequentially formed.

Here, instead of using the substrate, the lower insulating film 101 and the silicon 102, any one of a silicon bulk substrate, a silicon germanium substrate, a tensile silicon substrate, or a tensile silicon germanium substrate may be formed and used.

Next, an oxidation process and a nitride film at a temperature of 900 to 1100 ° C. are formed to form a hard mask layer 103.

Next, a photoresist pattern 104 for the active region pattern is formed on the substrate.

Next, using the photoresist pattern 104, a pattern of a silicon fin on which a silicon channel is to be formed and a region on which a source / drain is to be formed is formed on the silicon 102 and the hard mask layer 103.

In this case, the silicon channel may be formed of a silicon thin film or a fin structure to increase the degree of integration of the device and to suppress a short channel effect.

Next, the tunneling dielectric film 206, the floating gate 207, and the control dielectric film 208 are sequentially grown and deposited to capture electrons, and then the gate material 209 is deposited (200A). A film structure for trapping the electrons is formed between the silicon fin and the gate to be formed in a later process.

Next, in order to form an asymmetric double gate, the impurity implantation angles of n-type and p-types are adjusted (> 45 °) to inject different types of impurities into the gates of each of the silicon fins (200B).

Here, after depositing the non-doped gate material 209, the step of implanting the n-type impurities to the selected gate without additional mask operation by adjusting the implantation angle and the n-type impurity by adjusting the implantation angle And injecting into the gate opposite to the type without additional masking.

In this case, the gate material uses polysilicon, and as an n-type impurity, for example, As or P is injected, and the p-type impurity is injected with B or BF2.

In addition, the injection angle is preferably to be 45 ° or more.

In addition, in order to remove the channeling effect of ions passing through the gate to the substrate during impurity implantation, a screen oxide is deposited on the gate, and then the impurity ions of the different types are implanted, and the blocking is performed again. The method may further include removing the oxide layer (not shown).

Next, the gate mask 210 is patterned to form a gate pattern (200C).

Next, the gate material 209, the control dielectric layer 208, the floating gate 207, and the tunneling dielectric layer 206 of the remaining portions except for the gate region are etched and impurities are implanted to form the source / drain regions. The gate mask 210 is removed (200D).

Next, the gate that was joined by removing the gate material 209, the control dielectric film 208, the floating gate 207, and the tunneling dielectric film 206 left at the upper end of the fin through a chemical, mechanical polishing method or an anisotropic etching method. Is separated (200E).

By this process, it becomes possible to fabricate a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function according to an embodiment of the present invention.

Furthermore, in one embodiment of the present invention, instead of a structure such as SONOS that traps electrons in the insulating film trap, silicon, silicon nanocrystals, germanium, germanium nanocrystals, and metal nanocrystals are used as floating gates, and the control dielectric film and tunneling are performed. As the dielectric film, a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function of a floating gate memory structure using a polymer material, an oxide film, a nitride film, and an oxide film / nitride film / oxide film can be manufactured.

FIG. 2B is a cross-sectional view of the device fabricated by the fabrication method shown in FIG. 2A.

As shown in FIG. 2B, a double gate structure, a tunneling dielectric layer 206, a floating gate 207, and a control dielectric layer 208 have an asymmetric work function in a cross-section in the bb ′ direction of FIG. 2A. can confirm.

3 is a process perspective view illustrating a method of forming an asymmetric double gate nonvolatile memory device using metal having different work functions according to another embodiment of the present invention.

First, since the processes 100A to 100D shown in FIG. 1 are the same, the description is omitted below.

Next, the tunneling dielectric layer 306, the floating gate 307, and the control dielectric layer 308 are sequentially grown and deposited to capture electrons. A film structure for trapping the electrons is formed between the silicon fin and the gate to be formed in a later process.

Next, metals 311 and 312 having different work functions on both surfaces of the silicon fin are deposited by oblique sputtering or evaporation.

In addition, after depositing the undoped polysilicon and the metal in turn, by adjusting the implant angle (Large Angle Tilted Implantation) and implanting different types of n-type or p-type impurities around both sides of the silicon fin After that, the method may further include performing a subsequent thermal process.

In addition, after depositing the non-doped polysilicon, the impurity implantation angle is first adjusted to inject different types of impurities into both sides of the polysilicon as the gate material based on the silicon fin, and then onto the polysilicon as the gate material. After depositing the metal, silicides having different work functions may be formed through subsequent thermal processes.

In addition, by depositing nickel on the doped polysilicon by adjusting the injection angle of the gate to n-type and p-type, and then forming NiSi in a subsequent thermal process, to form a metal electrode having a work function of 4 eV on one side On the other side, a silicide electrode having a work function of 5 eV may be formed.

At this time, one side is less than 4 eV, and the other side is to deposit a metal having a work function of more than 5 eV on both sides around the silicon fin.

That is, since the difference in the threshold voltage between two bits increases as the work function difference between two gates between metals or pins increases, the difference in the work function between metals is increased to increase the threshold voltage difference to prevent malfunction of the device.

Instead of sputtering the metal obliquely as a method for depositing the metal obliquely, a method of obliquely inserting the substrate into the metal deposition equipment or turning the chuck on which the substrate is mounted may be used.

Next, the gate mask region is patterned to form a gate pattern as shown in FIG. 2C and 200D, and the gate material, the control dielectric layer, the floating gate, and the tunneling dielectric layer in the remaining portions except the gate region are etched, and the source / Impurities are implanted to form the drain region.

Next, the bonding is performed by removing the gate materials 311 and 312, the control dielectric layer 308, the floating gate 307 and the tunneling dielectric layer 306 left at the upper end of the fin through a chemical, mechanical polishing method or an anisotropic etching method. The gate is disconnected (300B).

By this process, it becomes possible to manufacture a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function according to another embodiment of the present invention.

Further, in another embodiment of the present invention, silicon, silicon nanocrystals, nitrides, germanium, germanium nanocrystals, and metal nanocrystals are used as floating gates instead of a structure such as SONOS that traps electrons in an insulating film trap, and a control dielectric film. As the over-tuning dielectric film, a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function of a floating gate memory structure using a polymer material, an oxide film, a nitride film, and an oxide film / nitride film / oxide film can be manufactured. have.

4 and 5 illustrate a two-bit memory cell operation using a metal double gate having different types of impurity implants or different work functions of the present invention.

4 is a schematic cross-sectional view of a 2-bit nonvolatile memory device using a dual gate structure having an asymmetric work function, and FIG. 5 is a graph for explaining voltage and current characteristics with respect to a logic value.

Before looking at the voltage characteristics for the logic values, define the parameters as follows.

-The voltage corresponding to logic "1" is defined as Vp.

-The voltage corresponding to logic "0" is defined as Ve.

-The voltage applied to the forward gate (FG) is defined as Vfg.

-The voltage applied to the BG (Back Gate) is defined as Vbg.

The threshold voltage of FG is defined as Vtfg.

The threshold voltage of BG is defined as Vtbg.

Here, the case is when Vtfg < Vtbg.

The logic " 00 " is Vfg = Ve < Vtfg and Vbg = Ve < Vtbg, so that the electrons trapped in the floating gate are very few and show the device-wide threshold voltage similar to the erase situation.

Since logic "01" is Vfg = Ve <Vtfg, Vbg = Vp> Vtbg, very small amount of electron capture occurs in FG, but large amount of electron capture occurs in BG, compared to logic "00" at read time. An increased threshold voltage is shown.

Logic "10" is Vfg = Vp> Vtfg, Vbg = Ve <Vtbg and Vtfg <Vtbg, so in the case of logic “01”, more than the amount of electrons trapped in the BG is captured by the FG, so the logic at read The threshold voltage is increased from 01 ".

The logic " 11 " is Vfg = Vp > Vtfg and Vbg = Vp > Vtbg, so that both electrons are actively captured in FG and BG, resulting in the largest threshold voltage increase at the time of read.

The above describes the 2-bit memory operation of an asymmetric double gate pin field effect transistor.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

The above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the foregoing description, and the meaning and scope of the claims and their All changes or modifications derived from equivalent concepts should be construed as being included in the scope of the present invention.

The method of manufacturing a 2 bit nonvolatile memory device using a double gate structure having an asymmetric work function according to the present invention is simple and highly reproducible, and by using a FinFET structure, high density integration is possible and a conventional silicon device manufacturing process The ability to be compatible with is a major contributor to continually reducing the size of memory devices.

In addition, it is possible to continuously reduce the size of the memory device, it is possible to develop a tera-class memory, and the ripple effect is large throughout the semiconductor industry.

Claims (18)

(a) forming a substrate comprising silicon; (b) forming a photoresist pattern for the active region pattern on the hard mask layer; (c) forming a pattern of a silicon fin on which a silicon channel is to be formed and a region where a source / drain is to be formed in the silicon and hard mask layer using the photoresist pattern; (d) sequentially growing and depositing a tunneling dielectric layer, a floating gate, and a control dielectric layer to capture electrons; (e) after depositing a gate material, implanting different types of impurities into each gate of each of the silicon fins by adjusting an impurity implantation angle to form an asymmetric double gate; (f) patterning the gate region with a gate mask; (g) impurity implantation to form source / drain regions; and (h) separating the bonded double gate by removing the gate material, control dielectric layer, floating gate and tunneling dielectric layer left at the top of the fin through chemical, mechanical polishing or anisotropic etching; A method of manufacturing a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function including a. The method of claim 1, The silicon-containing substrate may be any one of an SOI substrate, a silicon bulk substrate, a silicon germanium substrate, a tensile silicon substrate, or a tensile silicon germanium substrate. Memory device manufacturing method. The method of claim 1, The floating gate of step (d) is any one of silicon, silicon nanocrystal (nanocrystal), nitride film, germanium, germanium nanocrystal or metal nanocrystal, The control dielectric film and the tunneling dielectric film of step (d) may use any one of a polymer material, an oxide film, a nitride film, and an oxide film / nitride film / oxide film. The 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function may be used. Manufacturing method. The method of claim 1, In the impurity implantation of step (e), an n-type impurity is implanted into one gate, and an p-type impurity is implanted into the gate opposite to the n-type. 2 bit non-volatile memory device manufacturing method using. The method of claim 4, wherein The gate material of step (e) is polysilicon, n-type impurity is As or P, and p-type impurity is B or BF2, 2-bit non-volatile memory using a double gate structure having an asymmetric work function Device manufacturing method. The method of claim 5, The impurity implantation angle of step (e) is 45 ° or more method of manufacturing a two-bit nonvolatile memory device using a double gate structure having an asymmetric work function. The method of claim 1, The impurity implantation of step (e) is implanted without an additional mask forming operation. A method of manufacturing a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function. The method of claim 1, In the impurity implantation of step (e), a screen oxide is deposited on the gate, and the ion is removed after the ion is injected to remove the channeling effect of the ions passing through the gate to the substrate. A method of manufacturing a 2 bit nonvolatile memory device using a double gate structure having an asymmetric work function further comprising. A 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function manufactured by a method of fabricating a nonvolatile memory device using a double gate structure having a different work function of any one of claims 1 to 8. . (a) sequentially forming a substrate including a silicon, a lower insulating film, silicon, and a hard mask; (b) forming a photoresist pattern on the hard mask layer for the active region pattern. (c) A pattern of a silicon fin on which a silicon channel is to be formed and a region on which a source / drain is to be formed is formed on the silicon and the hard mask using a photoresist pattern. (d) sequentially growing and depositing a tunneling dielectric layer, a floating gate, and a control dielectric layer to capture electrons; (e) obliquely depositing metals having different work functions on both sides of the silicon fin; (f) patterning the gate region with a gate mask; (g) impurity implantation to form source / drain regions; And (h) separating the bonded double gate by removing the gate material, control dielectric film, floating gate and tunneling dielectric film left at the upper end of the fin using chemical, mechanical polishing or anisotropic etching process; A method of manufacturing a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function including a. The method of claim 10, The silicon-containing substrate may be any one of a silicon bulk substrate, a silicon germanium substrate, a tensile silicon substrate, or a tensile silicon germanium substrate, and fabricate a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function. Way. The method of claim 10, The floating gate of step (d) is any one of silicon, silicon nanocrystal (nanocrystal), nitride film, germanium, germanium nanocrystal or metal nanocrystal, The control dielectric film and the tunneling dielectric film of step (d) may use any one of a polymer material, an oxide film, a nitride film, and an oxide film / nitride film / oxide film. The 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function may be used. Manufacturing method. The method of claim 10, Before depositing the metal of step (e), the undoped polysilicon and the metal film are sequentially deposited, and n-type on one side and p-type impurities on the opposite side of the silicon fin are inclined to be inclined. A method of manufacturing a 2-bit nonvolatile memory device using a structure. The method of claim 10, After depositing the undoped polysilicon before depositing the metal of the step (e), p-type impurities are implanted on one side of the n-type opposite to the silicon fin, and then deposited obliquely. A method of manufacturing a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function characterized by forming a gate having a silicide asymmetric work function using a process. The method of claim 14, Nickel is deposited on polysilicon implanted with other types of impurities based on the silicon fin, and NiSi is formed by a subsequent thermal process to form a silicide electrode having a work-function of 4 eV on one side and 5 eV on the other side. A method of manufacturing a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function, which forms a NiSi silicide electrode having a work function. The method according to claim 10, The work-function difference of the asymmetric dual control gate can be adjusted by increasing the threshold voltage between the two bits, the method of manufacturing a 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function. The method of claim 10, In the case of depositing the metal in the step (e) inclined, by inserting the substrate inclined to the metal deposition equipment or by rotating the chuck mounted on the substrate 2 using a double gate structure having an asymmetric work function Bit nonvolatile memory device manufacturing method. A 2-bit nonvolatile memory device using a double gate structure having an asymmetric work function fabricated by a method of fabricating a nonvolatile memory device using a double gate structure having a different work function according to any one of claims 10 to 17. .

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