KR20080068658A - SOI trench horizontal ITV - Google Patents

Abstract

In the IGBT, in a high voltage, and enabling the driving at a large current and a high latch-up immunity, and an object of the present invention to decrease the on-resistance per unit area, in order to achieve this purpose, n ⁺ emitter region ( A trench consisting of an upper trench 16a and a lower trench 16b is formed on the entire surface of the wafer between 6a) and the p ⁺ collector region 12a, and the inner pressure is filled by filling the trench with the trench filling insulating film 17. The drift region is bent in the depth direction of the wafer to lengthen the effective drift length. By embedding the emitter side field plate 15 in the trench buried insulating film 17 and shielding the transverse electric field generated on the emitter side of the trench buried insulating film 17, the n ⁻ drift region 3a and the p base region ( The electric field generated at the PN junction with 4a) is relaxed.

Description

SOI TRENCH LATERAL IGBT

The present invention is a horizontal IGBT (insulated gate bipolar) which is one of a power device having a low on-resistance per unit area and having a high short circuit resistance, which is a combination of a horizontal MOS (metal-oxide-semiconductor) transistor and a bipolar transistor. Transistor).

A device in which a MOS transistor and a bipolar transistor are combined has an advantage that the structure of the driving circuit is simple as in the MOS element, and that the on-resistance is low by the conductivity modulation of the breakdown portion like the bipolar transistor. Therefore, it is important in the field requiring high breakdown voltage and high power level.

The device has a planar gate type and a trench gate type. The planar gate type has a structure in which a gate electrode is provided on the substrate surface through a gate insulating film. The trench gate type has a structure in which a gate electrode is embedded in a trench formed in a substrate. The trench gate type device structure has excellent characteristics such as high density of the channel and poor parasitic thyristor operation.

Below, the structure of the conventional IGBT is demonstrated with reference to an accompanying drawing. In addition, in this specification and an accompanying drawing, n or p shown by the name of the layer and the area | region of a semiconductor means that the majority carrier of the layer or area | region is an electron or a hole, respectively. In addition, like n ⁺ and p ⁺ , ⁺ attached to n or p indicates that the impurity concentration is relatively higher than the impurity concentration of the layer or region of the semiconductor to which it is not attached. Also, like n ^- and p ^- , ^- attached to n or p indicates that the impurity concentration is relatively lower than that of the layer or region of the semiconductor to which it is not attached.

FIG. 49 is a diagram showing a cross-sectional structure of an IGBT fabricated using a conventional thick-film SOI substrate. As shown in FIG. 49, the SOI substrate has a structure in which a high resistivity n ⁻ drift region 103 serving as an active layer is laminated on the support substrate 101 through the insulating layer 102. The p base region 104 is provided in a part of the surface layer of the n ⁻ drift region 103.

A part of the surface layer of the p base region 104 is provided with an n ⁺ emitter region 106 and a p ⁺ low resistance region 105 in contact with the n ⁺ emitter region 106. A portion of this p ⁺ low resistance region 105 occupies the lower portion of the n ⁺ emitter region 106.

In addition, an n buffer region 111 is provided away from the p base region 104 in a part of the surface layer of the n ⁻ drift region 103. The resistivity of the n buffer region 111 is lower than the resistivity of the n ⁻ drift region 103. The p ⁺ collector region 112 is provided in part of the surface layer of the n buffer region 111.

The emitter electrode 107 is in contact with both the p ⁺ low resistance region 105 and the n ⁺ emitter region 106. On the surface of the p base region 104 sandwiched between the n ⁻ drift region 103 and the n ⁺ emitter region 106, a gate electrode 108 is provided through the insulating film 109. The collector electrode 110 is in contact with the p ⁺ collector region 112.

In the IGBT having the configuration shown in FIG. 49, the n region including the p ⁺ collector region 112, the n buffer region 111 and the n ⁻ drift region 103, the p base region 104 and the p ⁺ low resistance The p region consisting of the region 105 constitutes a PNP bipolar transistor. In addition, the NPN bipolar transistor is configured by the n ⁺ emitter region 106, the p base region 104, and the n ⁻ drift region 103.

Then, these PNP bipolar transistors and NPN bipolar transistors form a parasitic thyristor. In order to prevent latch-up by this parasitic thyristor, the upper limit of the on-current is set. In order to raise the upper limit of the on current, the NPN bipolar transistor may be disabled.

For this purpose, it is necessary to suppress the resistance of the current path passing from below the channel single side to below the n ⁺ emitter region 106 to the p ⁺ low resistance region 105. In this regard, a method of lowering the resistance of the current path by ion implantation is known. In addition, when forming the p ⁺ low resistance region 105, a method of removing the uncertainty by mask matching, minimizing the length of the current path, and forming a trench emitter electrode capable of self matching with the gate electrode is provided. Known.

In addition, when the device is in the on state, a portion of the carrier flowing into the n ⁻ drift region 103 from the p ⁺ collector region 112 reaches the p ⁺ low resistance region 105 without passing through the current path. Is known. In the IGBT having the configuration shown in FIG. 49, the electric field is an interface near the wafer surface of the n ⁻ drift region 103 and the p base region 104, and the n ⁻ drift region 103 and the n buffer region 111. Concentrate on the interface near the wafer surface.

In order to alleviate the concentration of this electric field, as the field plate, the emitter electrode 107 and the collector electrode 110 may be extended to cover the interface via the insulating film 109. As a structure in which a higher breakdown voltage is required or a wiring such as a power supply line is provided on the drift region, it is known that a capacitively coupled field plate is provided on the top surface of the drift region or inside the drift region. It is.

In a device in which a conventional MOS transistor and a bipolar transistor are combined as described above, since the voltage is carried in the direction along the wafer surface, the dimension of the unit device increases in proportion to the design breakdown voltage value. For this reason, there is a drawback that the chip area becomes large in a device having a high current at high breakdown voltage.

Therefore, in the lateral MOS transistor, in order to reduce the area of the drift region occupied on the wafer surface, a configuration is proposed in which a trench is formed in the drift region and the trench is filled with a silicon oxide film having a larger breakdown field than silicon (for example, See Patent Document 1.). According to this proposal, as shown in Fig. 50, the effective drift length L _eff is buried in the trench from the boundary between the p well region 204 where the channel is formed and the n well region 203 serving as the drift region. The distance L _P to the oxide film 217, the trench depth L _T , the trench width L _B , and the trench depth L _T are obtained.

On the other hand, the distance L _D from the boundary between the p well region 204 and the n well region 203 on the wafer surface to the drain region 212 is the length obtained by adding L _P and L _B. Therefore, since L _eff can be made longer than when the buried oxide film 217 is not provided, the on-resistance R _on A is reduced in comparison with a device having the same breakdown voltage. Where R _on is the on resistance per unit area and A is the surface area. In other words, it is possible to obtain a lateral device having a breakdown voltage and an on current equivalent to that of the conventional art and having a smaller device pitch than the conventional art.

In addition, in a horizontal IGBT having an SOI (silicon on insulator) structure, a structure is proposed in which a trench is formed in the n-type active layer and a partially high concentration n-type bypass layer is provided below the trench ( See, for example, Patent Document 2). According to this proposal, since the hole current flowing into the source electrode is reduced by the trench, and the electron current flows through the bypass layer, the accumulation of the electron current on the source side increases and the on-voltage decreases.

Patent Document 1: Japanese Patent Application Laid-Open No. 8-97411

Patent document 2: Unexamined-Japanese-Patent No. 8-88357 (FIGS. 1-8)

However, the IGBT of the structure disclosed by the said patent document 2 has the following various problems. In other words, in the case where the SOI structure is realized with a bonded wafer, for example, two wafers must be bonded with the alignment accuracy of a µm order so that the bypass layer is located directly under the trench, which is undesirable in manufacturing. In addition, in the layout shown in FIG. 2 or FIG. 3 of Patent Document 2, since the breakdown voltage is determined by the length of the n-type active layer on the wafer surface, the cell pitch of the device cannot be shortened. Therefore, the on resistance per unit area cannot be lowered.

In addition, in the layout shown in Fig. 4 of Patent Document 2 and having the cross-sectional configuration shown in Fig. 8, since a low resistance region exists around the trench, the breakdown voltage is equal to that of the n-type active layer on the wafer surface excluding the trench. Determined by length Therefore, the cell pitch of the device cannot be shortened, and the on resistance per unit area cannot be lowered.

Moreover, in the device shown in FIG. 4 of patent document 2 and having the cross-sectional structure shown in FIG. 6, since the channel | path of a hole is not formed below the trench 17, the conductivity side of the gate side is eliminated, and the advantage of IGBT is shown. This is damaged. In addition, in order to maintain the conductivity modulation on the gate side, the layout shown in Fig. 2 of this publication makes it impossible to shorten the pitch because the device pitch is determined by the length of the surface drift region 3.

In addition, in the cross-sectional structure shown in FIG. 5 of Patent Document 2, since the distance between the trench bottom and the bypass layer is determined by ion implantation energy, the portion cannot be thickened, and the tradeoff with internal pressure is limited. It becomes.

SUMMARY OF THE INVENTION The present invention aims at providing a horizontal IGBT with a high breakdown voltage, capable of driving at a large current, having a high latch up resistance, and having a low on-resistance per unit area, in order to solve the problems caused by the above-described prior art. do.

In order to solve the above problems and achieve the object, the SOI trench lateral IGBT according to the invention of claim 1 is a semiconductor layer of the first conductivity type provided on the support substrate via an insulating layer, and is provided on the semiconductor layer, A first semiconductor region of a first conductivity type having a higher resistivity than the semiconductor layer, a second semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region provided in a part of a surface layer of the first semiconductor region, A third conductive region of a second conductivity type provided in a part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region, and a gate insulating film on a surface of a portion of the third semiconductor region; A gate electrode provided, a first conductivity type emitter region provided in a part of the third semiconductor region, and a part of the third semiconductor region, and beneath the emitter region. A low-resistance region of the second conductivity type, a portion of the third semiconductor region, a high conductivity region of the second conductivity type provided adjacent to the emitter region, and a portion of the surface layer of the first semiconductor region. And a fourth semiconductor region of a first conductivity type having a resistivity lower than that of the first semiconductor region and spaced apart from the second semiconductor region and the third semiconductor region, and of a second conductivity type provided in a portion of the fourth semiconductor region. A top trench provided between the collector region, the second semiconductor region, the third semiconductor region and the fourth semiconductor region, a bottom trench narrower than the top trench, which is provided from a bottom of the top trench to a deeper position; And a trench filling insulating film embedded in the upper trench and the lower trench, and a trench filling insulating film in the upper trench. The emitter side conductive region of the floating potential buried in the vicinity of the third semiconductor region, the collector side conductive region buried in the vicinity of the fourth semiconductor region in the trench filling insulating film in the upper trench, and the emitter region And a collector electrode in contact with the high conductivity region, and a collector electrode in contact with the collector region and electrically connected to the collector-side conductive region.

SOI trench lateral IGBT according to the invention of claim 2 is a first conductive semiconductor layer provided on the support substrate via an insulating layer, and the first conductive semiconductor material having a higher resistivity than the semiconductor layer provided on the semiconductor layer. A first semiconductor region, a second conductive region of a first conductivity type lower in resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, and in contact with the first semiconductor region and the second semiconductor region; A third semiconductor region of a second conductivity type provided on a part of the surface layer of the first semiconductor region, a gate electrode provided on a surface of the part of the third semiconductor region via a gate insulating film, and a part of the third semiconductor region. An emitter region of the first conductivity type provided, a low resistance region of the second conductivity type provided in a part of the third semiconductor region and provided below the emitter region, and the third half. A second conductivity type high conductivity region provided adjacent to the emitter region, and a part of the surface layer of the first semiconductor region, separated from the second semiconductor region and the third semiconductor region. And a fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, a collector region of a second conductivity type provided in a portion of the fourth semiconductor region, the second semiconductor region and the third semiconductor region. A trench provided between the semiconductor region and the fourth semiconductor region, a trench filling insulating film embedded in the trench, an emitter side conductive region having a floating potential buried near the third semiconductor region in the upper half of the trench filling insulating film, The collector-side conductive region buried near the fourth semiconductor region in the upper half of the trench filling insulating film, the emitter region and the high conductivity The emitter electrode in contact with the station, and in contact with the collector region, characterized by comprising a collector electrode electrically connected to the collector side conductive regions.

The SOI trench lateral IGBT according to the invention of claim 3 is a first conductive type semiconductor layer provided on the support substrate via an insulating layer and a first conductive type having a higher resistivity than the semiconductor layer provided on the semiconductor layer. A first semiconductor region, a third conductive region of a second conductivity type provided in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region, and penetrating the third semiconductor region to the first semiconductor region; A gate electrode provided through a gate insulating film inside the reaching gate trench, a part of the third semiconductor region, an emitter region of a first conductivity type provided in contact with the gate trench, and a part of the third semiconductor region, A low resistance region of the second conductivity type provided adjacent to the emitter region and a part of the surface layer of the first semiconductor region, provided away from the third semiconductor region, A fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, a collector region of a second conductivity type provided in a portion of the fourth semiconductor region, and between the third semiconductor region and the fourth semiconductor region. A top trench provided in the trench, a bottom trench narrower than the top trench provided in a deeper position from the bottom of the top trench, a trench buried insulating film embedded in the top trench and the bottom trench, and in the top trench. Emitter-side conductive region of floating potential buried in the trench buried insulating film near the third semiconductor region, and collector-side conductive buried near the fourth semiconductor region in the trench buried insulating film in the upper trench. A region, an emitter electrode in contact with the emitter region and the low resistance region, and the collector And a collector electrode in contact with the region and electrically connected to the collector-side conductive region.

The SOI trench lateral IGBT according to the invention of claim 4 is a first conductive type semiconductor layer provided on the support substrate via an insulating layer and a first conductive type higher resistivity than the semiconductor layer provided on the semiconductor layer. A first semiconductor region, a third conductive region of a second conductivity type provided in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region, and penetrating the third semiconductor region to the first semiconductor region; A gate electrode provided through a gate insulating film inside the reaching gate trench, a part of the third semiconductor region, an emitter region of a first conductivity type provided in contact with the gate trench, and a part of the third semiconductor region, A low resistance region of the second conductivity type provided adjacent to the emitter region and a part of the surface layer of the first semiconductor region, provided away from the third semiconductor region, A fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, a collector region of a second conductivity type provided in a portion of the fourth semiconductor region, and between the third semiconductor region and the fourth semiconductor region. A trench provided in the trench, a trench filling insulating film embedded in the trench, an upper conductive portion of the trench filling insulating film, an emitter side conductive region having a floating potential buried near the third semiconductor region, and an upper half of the trench filling insulating film, A collector-side conductive region buried near the fourth semiconductor region, an emitter electrode in contact with the emitter region and the low resistance region, a collector electrode in contact with the collector region and electrically connected to the collector-side conductive region Characterized in that it comprises a.

SOI trench lateral IGBT according to the invention of claim 5 is a first conductive type semiconductor layer provided on the support substrate via an insulating layer and a first conductivity type higher resistivity than the semiconductor layer provided on the semiconductor layer. A first semiconductor region, a second conductive region of a first conductivity type lower in resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, and in contact with the first semiconductor region and the second semiconductor region; A third semiconductor region of a second conductivity type provided on a part of the surface layer of the first semiconductor region, a gate electrode provided on a surface of the part of the third semiconductor region via a gate insulating film, and a part of the third semiconductor region. An emitter region of the first conductivity type provided, a low resistance region of the second conductivity type provided in a part of the third semiconductor region and provided below the emitter region, and the third half. A second conductivity type high conductivity region provided adjacent to the emitter region, and a part of the surface layer of the first semiconductor region, separated from the second semiconductor region and the third semiconductor region. And a fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, a collector region of a second conductivity type provided in a portion of the fourth semiconductor region, the second semiconductor region and the third semiconductor region. An upper trench disposed away from the fourth semiconductor region, a lower trench narrower than the upper trench disposed between the fourth semiconductor region and a position deeper from the bottom of the upper trench, the upper trench and the lower end; The third peninsula in the trench-filling insulating film embedded in the trench and the trench-filling insulating film in the upper trench Already teocheuk conductive region of the buried floating potential in the vicinity of the region, and the emitter electrode and the emitter region in contact with the classical nor the region, it characterized in that it comprises a collector electrode in contact with the collector region.

The SOI trench lateral IGBT according to the invention of claim 6 includes a first conductive semiconductor layer provided on a support substrate via an insulating layer and a first conductive semiconductor material having a higher resistivity than the semiconductor layer provided on the semiconductor layer. A first semiconductor region, a second conductive region of a first conductivity type lower in resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, and in contact with the first semiconductor region and the second semiconductor region; A third semiconductor region of a second conductivity type provided on a part of the surface layer of the first semiconductor region, a gate electrode provided on a surface of the part of the third semiconductor region via a gate insulating film, and a part of the third semiconductor region. An emitter region of the first conductivity type provided, a low resistance region of the second conductivity type provided in a part of the third semiconductor region and provided below the emitter region, and the third half. A second conductivity type high conductivity region provided adjacent to the emitter region, and a part of the surface layer of the first semiconductor region, separated from the second semiconductor region and the third semiconductor region. And a fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, a collector region of a second conductivity type provided in a portion of the fourth semiconductor region, the second semiconductor region and the third semiconductor region. A floating potential buried in the vicinity of the third semiconductor region between the trench and the fourth semiconductor region, a trench disposed away from the fourth semiconductor region, a trench filling insulating film embedded in the trench, and an upper half of the trench filling insulating film. Emitter side conductive region, an emitter electrode in contact with the emitter region and the high conductivity region, and a collector in contact with the collector region It characterized in that it comprises an electrode.

SOI trench lateral IGBT according to the invention of claim 7 is a first conductive type semiconductor layer provided on the support substrate via an insulating layer, and the first conductive type of higher resistivity than the semiconductor layer provided on the semiconductor layer A first semiconductor region, a third conductive region of a second conductivity type provided in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region, and penetrating the third semiconductor region to the first semiconductor region; A gate electrode provided through a gate insulating film inside the reaching gate trench, a part of the third semiconductor region, an emitter region of a first conductivity type provided in contact with the gate trench, and a part of the third semiconductor region, A low resistance region of the second conductivity type provided adjacent to the emitter region and a part of the surface layer of the first semiconductor region, provided away from the third semiconductor region, A fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, a collector region of a second conductivity type provided in a portion of the fourth semiconductor region, and between the third semiconductor region and the fourth semiconductor region. An upper trench disposed away from the fourth semiconductor region, a lower trench narrower than the upper trench disposed deeper from a bottom of the upper trench, and a trench buried insulating layer embedded in the upper trench and the lower trench. And an emitter side conductive region of a floating potential buried in the vicinity of the third semiconductor region in the trench buried insulating film in the upper trench, an emitter electrode in contact with the emitter region and the low resistance region, And a collector electrode in contact with the collector region.

The SOI trench lateral IGBT according to the invention of claim 8 includes a first conductive semiconductor layer provided on the support substrate via an insulating layer and a first conductive semiconductor material having a higher resistivity than the semiconductor layer provided on the semiconductor layer. A first semiconductor region, a third conductive region of a second conductivity type provided in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region, and penetrating the third semiconductor region to the first semiconductor region; A gate electrode provided through a gate insulating film inside the reaching gate trench, a part of the third semiconductor region, an emitter region of a first conductivity type provided in contact with the gate trench, and a part of the third semiconductor region, A low resistance region of the second conductivity type provided adjacent to the emitter region and a part of the surface layer of the first semiconductor region, provided away from the third semiconductor region, A fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, a collector region of a second conductivity type provided in a portion of the fourth semiconductor region, and between the third semiconductor region and the fourth semiconductor region. A trench provided away from the fourth semiconductor region, a trench fill insulating film buried in the trench, an emitter side conductive region of a floating potential buried near the third semiconductor region in an upper half of the trench buried insulating film, And an emitter electrode in contact with the emitter region and the low resistance region, and a collector electrode in contact with the collector region.

The SOI trench lateral IGBT according to the invention of claim 9 is a first conductive type semiconductor layer provided on the support substrate via an insulating layer and a first conductive type resistivity higher than the semiconductor layer provided on the semiconductor layer. A first semiconductor region, a second conductive region of a first conductivity type lower in resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, and in contact with the first semiconductor region and the second semiconductor region; A third semiconductor region of a second conductivity type provided on a part of the surface layer of the first semiconductor region, a gate electrode provided on a surface of the part of the third semiconductor region via a gate insulating film, and a part of the third semiconductor region. An emitter region of the first conductivity type provided, a low resistance region of the second conductivity type provided in a part of the third semiconductor region and provided below the emitter region, and the third half. A second conductivity type high conductivity region provided adjacent to the emitter region, and a part of the surface layer of the first semiconductor region, separated from the second semiconductor region and the third semiconductor region. And a fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, a collector region of a second conductivity type provided in a portion of the fourth semiconductor region, the second semiconductor region and the third semiconductor region. An upper trench disposed away from the third semiconductor region, a lower trench narrower than the upper trench disposed between the fourth semiconductor region and a position deeper from a bottom of the upper trench, the upper trench and the lower trench; The fourth peninsula in the trench-filling insulating film embedded in the trench and the trench-filling insulating film in the upper trench A collector-side conductive region embedded near the region, an emitter electrode in contact with the emitter region and the high conductivity region, and a collector electrode in contact with the collector region and electrically connected to the collector-side conductive region. It is characterized by.

SOI trench lateral IGBT according to the invention of claim 10 is a first conductive type semiconductor layer provided on the support substrate through an insulating layer, and the first conductive type of higher resistivity than the semiconductor layer provided on the semiconductor layer A first semiconductor region, a second conductive region of a first conductivity type lower in resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, and in contact with the first semiconductor region and the second semiconductor region; A third semiconductor region of a second conductivity type provided on a part of the surface layer of the first semiconductor region, a gate electrode provided on a surface of the part of the third semiconductor region via a gate insulating film, and a part of the third semiconductor region. An emitter region of a first conductivity type provided, a low resistance region of a second conductivity type provided in a part of the third semiconductor region and provided below the emitter region, and the third A second conductivity type high conductivity region provided adjacent to the emitter region, and a part of the surface layer of the first semiconductor region, separated from the second semiconductor region and the third semiconductor region. And a fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, a collector region of a second conductivity type provided in a portion of the fourth semiconductor region, the second semiconductor region and the third semiconductor region. A trench disposed between the fourth semiconductor region and a trench provided away from the third semiconductor region, a trench filling insulating film buried in the trench, and an upper portion of the trench filling insulating film, the collector side buried near the fourth semiconductor region. A conductive region, an emitter electrode in contact with the emitter region and the high conductivity region, and the collector region; It characterized in that it comprises a collector electrode electrically connected to the station.

The SOI trench lateral IGBT according to the invention of claim 11 is a first conductive type semiconductor layer provided on the support substrate via an insulating layer and a first conductive type resistivity higher than the semiconductor layer provided on the semiconductor layer. A first semiconductor region, a second conductive region of a first conductivity type lower in resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, and in contact with the first semiconductor region and the second semiconductor region; A third semiconductor region of a second conductivity type provided on a part of the surface layer of the first semiconductor region, a gate electrode provided on a surface of the part of the third semiconductor region via a gate insulating film, and a part of the third semiconductor region. An emitter region of a first conductivity type provided, a low resistance region of a second conductivity type provided in a part of the third semiconductor region and provided below the emitter region, and the third A second conductivity type high conductivity region provided adjacent to the emitter region, and a part of the surface layer of the first semiconductor region, separated from the second semiconductor region and the third semiconductor region. And a fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, a collector region of a second conductivity type provided in a portion of the fourth semiconductor region, the second semiconductor region and the third semiconductor region. A trench disposed away from the third semiconductor region and the fourth semiconductor region, a trench filling insulating film embedded in the trench, and an emitter contacting the emitter region and the high conductivity region And a collector electrode in contact with the collector region.

The SOI trench lateral IGBT according to the invention of claim 12 is the gate insulating film, the gate electrode, or the third semiconductor region according to any one of claims 1, 2, 5, 6, 9, 10 and 11. The low resistance region, the emitter region and the high conductivity region are provided in plural on the same side with respect to the trench filling insulating film, and the emitter region and the high conductivity region adjacent to each other are the emitter. It is characterized by being electrically connected with each other by an electrode.

The SOI trench lateral IGBT according to the invention of claim 13 is the gate trench, the gate insulating film, the gate electrode, the third semiconductor region, or the invention according to any one of claims 3, 4, 7, and 8. The low resistance region and the emitter region are provided in plural on the same side with respect to the trench filling insulating film, and the adjacent emitter region and the low resistance region are electrically connected to each other by the emitter electrode. It is characterized by.

The SOI trench lateral IGBT according to the invention of claim 14 is the invention according to any one of claims 1 to 13, wherein the semiconductor layer between the insulating layer and the first semiconductor region on the support substrate is free of metal contamination. Characterized by including a gettering effect for.

SOI trench lateral IGBT according to the invention of claim 15 is a first conductive type semiconductor layer provided on the support substrate via an insulating layer and a first conductivity type higher resistivity than the semiconductor layer provided on the semiconductor layer. A first semiconductor region, a second conductive region of a first conductivity type lower in resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, and in contact with the first semiconductor region and the second semiconductor region; A third semiconductor region of the second conductivity type provided in part of the surface layer of the first semiconductor region, an emitter region of the first conductivity type provided in part of the third semiconductor region, the second semiconductor region and the emitter A gate electrode provided through a gate insulating film on a surface of the third semiconductor region between regions, and a portion of the surface layer of the first semiconductor region, the second semiconductor region and the third semiconductor; A fourth semiconductor region of a first conductivity type lower in resistivity than the first semiconductor region, a second conductivity type collector region provided in a part of the fourth semiconductor region, the second semiconductor region and the Between the third semiconductor region and the first semiconductor region in the trench provided between the third semiconductor region and the fourth semiconductor region, the trench filling insulating film embedded in the trench, and the trench filling insulating film in the trench. The emitter side conductive region of the floating potential buried near the pn junction and the collector side conductive region embedded near the interface between the fourth semiconductor region and the first semiconductor region in the trench filling insulating film in the trench. And an emitter electrode in contact with the emitter region, the collector region in contact with the collector region, and an electrical It is characterized by including a collector electrode which connects normally.

SOI trench lateral IGBT according to the invention of claim 16 is a first conductive type semiconductor layer provided on the support substrate through an insulating layer, and the first conductive type of higher resistivity than the semiconductor layer provided on the semiconductor layer A first semiconductor region, a third conductive region of a second conductivity type provided in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region, and penetrating the third semiconductor region to the first semiconductor region; A gate electrode provided through a gate insulating film inside the reaching gate trench, a first conductive type emitter region provided in contact with the gate trench in a part of the third semiconductor region, and a part of a surface layer of the first semiconductor region And a fourth conductive region of a first conductivity type having a resistivity lower than that of the first semiconductor region, which is provided away from the third semiconductor region, and the fourth semiconductor region. In a collector region of a second conductivity type provided in a part, a trench provided between the third semiconductor region and the fourth semiconductor region, a trench filling insulating film embedded in the trench, and a trench filling insulating film in the trench, The fourth semiconductor region and the first semiconductor in an emitter side conductive region having a floating potential buried near a pn junction between the third semiconductor region and the first semiconductor region, and the trench filling insulating film in the trench; A collector-side conductive region buried near the interface with the region, an emitter electrode in contact with the emitter region, and a collector electrode in contact with the collector region and electrically connected to the collector-side conductive region do.

SOI trench lateral IGBT according to the invention of claim 17 is a first conductive semiconductor layer provided on the support substrate through an insulating layer, and the first conductive type of the first conductive type having a higher resistivity than the semiconductor layer provided on the semiconductor layer A first semiconductor region, a second conductive region of a first conductivity type lower in resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, and in contact with the first semiconductor region and the second semiconductor region; A third semiconductor region of the second conductivity type provided in part of the surface layer of the first semiconductor region, an emitter region of the first conductivity type provided in part of the third semiconductor region, the second semiconductor region and the emitter A gate electrode provided through a gate insulating film on a surface of the third semiconductor region between regions, and a portion of the surface layer of the first semiconductor region, the second semiconductor region and the third semiconductor; A fourth semiconductor region of a first conductivity type lower in resistivity than the first semiconductor region, a second conductivity type collector region provided in a part of the fourth semiconductor region, the second semiconductor region and the A third trench between the third semiconductor region and the fourth semiconductor region, a trench provided away from the fourth semiconductor region, a trench filling insulating film embedded in the trench, and the trench filling insulating film in the trench And an emitter side conductive region having a floating potential buried near the pn junction with the first semiconductor region, an emitter electrode in contact with the emitter region, and a collector electrode in contact with the collector region.

SOI trench lateral IGBT according to the invention of claim 18 is a first conductive type semiconductor layer provided on the support substrate via an insulating layer, and the first conductive type first resistivity is higher than the semiconductor layer provided on the semiconductor layer A first semiconductor region, a third conductive region of a second conductivity type provided in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region, and penetrating the third semiconductor region to the first semiconductor region; A gate electrode provided through a gate insulating film inside the reaching gate trench, a first conductive type emitter region provided in contact with the gate trench in a part of the third semiconductor region, and a part of a surface layer of the first semiconductor region And a fourth conductive region of a first conductivity type having a resistivity lower than that of the first semiconductor region, which is provided away from the third semiconductor region, and the fourth semiconductor region. A collector region of a second conductivity type provided in a part, a trench disposed away from the fourth semiconductor region between the third semiconductor region and the fourth semiconductor region, a trench filling insulating film embedded in the trench, and the trench In the trench-filling insulating film in the trench-filling insulating film, the emitter side conductive region having a floating potential buried near a pn junction between the third semiconductor region and the first semiconductor region, and the trench-filling insulating film in the trench. And a collector-side conductive region buried near the interface between the four semiconductor regions and the first semiconductor region, an emitter electrode in contact with the emitter region, and a collector electrode in contact with the collector region.

SOI trench lateral IGBT according to the invention of claim 19 is a first conductive semiconductor layer provided on the support substrate via an insulating layer and a first conductive type of higher resistivity than the semiconductor layer provided on the semiconductor layer A first semiconductor region, a second conductive region of a first conductivity type lower in resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, and in contact with the first semiconductor region and the second semiconductor region; A third semiconductor region of the second conductivity type provided in part of the surface layer of the first semiconductor region, an emitter region of the first conductivity type provided in part of the third semiconductor region, the second semiconductor region and the emitter A gate electrode provided through a gate insulating film on a surface of the third semiconductor region between regions, and a portion of the surface layer of the first semiconductor region, the second semiconductor region and the third semiconductor; A fourth semiconductor region of a first conductivity type lower in resistivity than the first semiconductor region, a second conductivity type collector region provided in a part of the fourth semiconductor region, the second semiconductor region and the A fourth trench region between the third semiconductor region and the fourth semiconductor region, a trench provided away from the third semiconductor region, a trench filling insulating film embedded in the trench, and the trench filling insulating film in the trench And a collector side conductive region embedded near an interface between the first semiconductor region, an emitter electrode in contact with the emitter region, and a collector electrode in contact with the collector region and electrically connected to the collector side conductive region. It is characterized by including.

SOI trench lateral IGBT according to the invention of claim 20 is a first conductive semiconductor layer provided on the support substrate via an insulating layer, and the first conductive type of the first conductive type having a higher resistivity than the semiconductor layer provided on the semiconductor layer. A first semiconductor region, a second conductive region of a first conductivity type lower in resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, and in contact with the first semiconductor region and the second semiconductor region; A third semiconductor region of the second conductivity type provided in part of the surface layer of the first semiconductor region, an emitter region of the first conductivity type provided in part of the third semiconductor region, the second semiconductor region and the emitter A gate electrode provided through a gate insulating film on a surface of the third semiconductor region between regions, and a portion of the surface layer of the first semiconductor region, the second semiconductor region and the third semiconductor; A fourth semiconductor region of a first conductivity type lower in resistivity than the first semiconductor region, a second conductivity type collector region provided in a part of the fourth semiconductor region, the second semiconductor region and the A trench disposed away from the third semiconductor region and the fourth semiconductor region, between the third semiconductor region and the fourth semiconductor region, a trench filling insulating film buried in the trench, and an emitter electrode in contact with the emitter region; And a collector electrode in contact with the collector region.

According to the above-mentioned invention of Claims 1 to 20, by forming the trench, a portion for maintaining the internal pressure is provided in the direction perpendicular to the wafer surface. As a result, since the drift region is bent in the depth direction of the wafer and drawn out on the wafer surface, the effective drift length increases. For this reason, even if the effective drift length is the length equivalent to the conventional one, the required surface area of the device is greatly reduced. Therefore, the on resistance per unit area is reduced.

Further, according to the invention of claim 1, 2, 3, 4, 9, 10, 15, 16, and 19, the collector-side conductive region is in contact with the collector electrode and the coin phase, so that the fourth semiconductor region, that is, the trench buried insulating film Since the interface of the drift region on the collector side becomes less depleted, the role of voltage carrying can be fulfilled.

In addition, according to the invention of claim 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, 17, and 18, the emitter side conductive region and the trench filling insulating film are formed on the emitter side of the trench filling insulating film. The generated transverse electric field is shielded, and the electric field generated by the PN junction formed by the first semiconductor region and the third semiconductor region is alleviated, so that electrical breakdown is less likely to occur. In addition, since the potential of the emitter side conductive region becomes the floating potential, the switching speed of the device is faster than when the potential of the emitter side conductive region is the emitter potential. This is because the capacitor formed between the emitter side conductive region and the first semiconductor region does not become a capacitor connected in parallel with the capacitor formed between the collector-emitter of the IGBT, thereby increasing the collector-emitter capacity of the IGBT. Because it does not.

Here, the potential difference between the emitter side conductive region and the first semiconductor region is determined by the electrostatic coupling of the capacitance between the collector side conductive region and the emitter side conductive region and the capacitance between the emitter side conductive region and the first semiconductor region. The thickness of the insulating film between the emitter side conductive region and the first semiconductor region (see FIG. 1, D1 in FIG. 1) is the thickness of the insulating film between the collector side conductive region and the emitter side conductive region (see FIG. 1, 2D2 + in FIG. 1). In the case of much smaller than 2D3), the potential of the emitter side conductive region is close to the ground potential.

Further, according to the inventions of Claims 12 and 13, since a plurality of channels are provided in the drift region composed of one first semiconductor region, high current capability can be obtained.

Further, according to the invention of claim 14, since the semiconductor layer is formed by ion implantation and thermal diffusion on the supporting substrate through the insulating layer, the semiconductor layer becomes a getter layer against metal contamination, so that metal contamination Get gettering effect on. Thus, the reliability of the gate insulating film is improved.

In addition, according to the invention of Claims 1 to 20, the semiconductor layer provided on the support substrate via the insulating layer has a defect in each of the interface with the first semiconductor region thereon and the interface with the insulating layer thereunder. Is suppressed and the depletion effect from the support substrate is suppressed. Thus, the first semiconductor region functions to be a bulk layer.

Moreover, since the dopant concentration of the semiconductor layer on this insulating layer is high, the carrier lifetime is short. For this reason, the life of the carrier injected from the collector is controlled according to the distance between the bottom of the trench filling insulating film and the semiconductor layer on the insulating layer, thereby maintaining a balance between the reverse recovery time of the element and the on resistance.

(Effects of the Invention)

According to the present invention, an IGBT having the same breakdown voltage and current drive capability as that of a horizontal semiconductor device using a conventional SOI substrate, high latch-up resistance, and low on-resistance per unit area can be obtained. In addition, the use of the SOI substrate brings about the effect of being easily integrated with the CM0S device.

1 is a cross sectional view showing a configuration of an IGBT according to the first embodiment.

FIG. 2 is a cross-sectional view showing a state in which a screen oxide film is formed on the surface of a semiconductor wafer serving as a drift region and arsenic ions are implanted during the manufacture of a device wafer of an SOI wafer used for manufacturing the IGBT of Embodiment 1. FIG. .

3 is a cross-sectional view showing a state in which a minority carrier cancellation layer is formed by implanting arsenic ions on the surface of a semiconductor wafer subsequent to the state shown in FIG. 2.

4 is a cross-sectional view showing a state in which the screen oxide film is removed and the formation of a device wafer composed of a drift region and a minority carrier cancellation layer is completed following the state shown in FIG. 3.

FIG. 5 is a cross-sectional view showing a state in which a support substrate for a handle wafer is prepared during manufacture of a handle wafer of an SOI wafer used for manufacturing an IGBT of Embodiment 1. FIG.

6 is a cross-sectional view showing a state in which an insulating layer is formed on the support substrate surface of the handle wafer and the formation of the handle wafer is completed following the state shown in FIG. 5.

7 is a cross-sectional view showing a state in which the device wafer and the handle wafer are integrated into an SOI wafer following the states shown in FIGS. 4 and 6.

FIG. 8 is a cross-sectional view showing a state in which the drift region of the integrated SOI wafer is polished to a predetermined thickness following the state shown in FIG. 7 to complete formation of the SOI wafer used in the manufacture of the IGBT of Embodiment 1. FIG. to be.

9 is a characteristic diagram showing an example of a relationship between the breakdown voltage which is the off breakdown voltage of the IGBT of the first embodiment, and the doping concentration in the drift region.

FIG. 10 is a potential distribution diagram showing an example of the electrostatic potential distribution at the time of breakdown of the IGBT of the first embodiment. FIG.

FIG. 11 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 1.

12 is a cross sectional view showing a configuration of an IGBT according to the second embodiment.

FIG. 13 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 12.

14 is a cross-sectional view showing a configuration of the IGBT of Embodiment 3. FIG.

FIG. 15 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 14.

16 is a cross-sectional view showing a configuration of the IGBT of the fourth embodiment.

17 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 16.

18 is a sectional view showing a configuration of an IGBT according to the fifth embodiment.

19 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 18.

20 is a cross sectional view showing a configuration of an IGBT according to the sixth embodiment;

21 is a cross-sectional view showing a configuration of an IGBT inverted in polarity of the configuration shown in FIG. 20.

FIG. 22 is a cross-sectional view showing a configuration of the IGBT of Embodiment 7. FIG.

FIG. 23 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 22.

24 is a cross-sectional view showing a configuration of the IGBT of Embodiment 8. FIG.

25 is a cross-sectional view showing a configuration of an IGBT inverted in polarity of the configuration shown in FIG. 24.

FIG. 26 is a cross-sectional view showing a configuration of the IGBT of Embodiment 9. FIG.

FIG. 27 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 26.

FIG. 28 is a sectional view showing a configuration of an IGBT of Embodiment 10; FIG.

29 is a cross-sectional view showing a configuration of an IGBT inverted in polarity of the configuration shown in FIG. 28.

30 is a cross sectional view showing a configuration of an IGBT according to the eleventh embodiment.

FIG. 31 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 30.

32 is a cross sectional view showing a configuration of an IGBT according to the twelfth embodiment;

33 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 32.

34 is a cross-sectional view showing a configuration of the IGBT of Embodiment 13. FIG.

35 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 34.

36 is a cross sectional view showing a configuration of an IGBT according to the fourteenth embodiment;

37 is a cross-sectional view showing a configuration of an IGBT inverted in polarity of the configuration shown in FIG. 36.

38 is a cross sectional view showing a configuration of an IGBT according to the fifteenth embodiment;

FIG. 39 is a cross-sectional view showing a configuration of an IGBT in which the polarity of the configuration shown in FIG. 38 is inverted. FIG.

40 is a cross sectional view showing a configuration of an IGBT according to the sixteenth embodiment;

41 is a cross-sectional view showing a configuration of an IGBT inverted in polarity of the configuration shown in FIG. 40.

42 is a sectional view showing a configuration of an IGBT of Embodiment 17. FIG.

FIG. 43 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 42.

44 is a cross-sectional view showing a configuration of an IGBT of Embodiment 18. FIG.

45 is a cross-sectional view illustrating a configuration of an IGBT inverting the polarity of the configuration illustrated in FIG. 44.

46 is a cross sectional view showing a configuration of an IGBT according to the nineteenth embodiment;

FIG. 47 is a cross-sectional view showing a configuration of an IGBT inverting the polarity of the configuration shown in FIG. 46.

FIG. 48 is a plan layout diagram showing main parts of an IGBT having the configuration shown in FIG. 46.

FIG. 49 shows a cross-sectional structure of an IGBT fabricated using a conventional thick film SOI substrate.

50 is a diagram showing a cross-sectional structure of a conventional horizontal MOS transistor.

Explanation of the sign

1a, 1b: support substrate

2: insulation layer

3a, 3c: first semiconductor region (drift region)

3b, 3d: second semiconductor region (well region)

4a, 4b: third semiconductor region (base region)

5a, 5c: low resistance region

5b, 5d: High Conductivity Region (Base Contact Region)

6a, 6b: emitter area

7: emitter electrode

8a, 8b: gate electrode

9a and 9b: gate insulating film

9c: insulating film

10: collector electrode

11a and 11b: fourth semiconductor region (buffer region)

12a, 12b: collector area

13a and 13b: semiconductor layer (small carrier offset layer)

14: Collector side conductive region (collector side field plate)

15: emitter side conductive region (emitter side field plate)

16a: top trench

16b: bottom trench

16c: trench

17: trench filling insulating film

19: gate trench

(The best mode for carrying out the invention)

DESCRIPTION OF THE EMBODIMENTS Preferred embodiments of the IGBT according to the present invention will be described in detail below with reference to the accompanying drawings. In addition, in description of the following embodiment and all the accompanying drawings, the same code | symbol is attached | subjected to the same structure and the overlapping description is abbreviate | omitted.

Embodiment 1

1 is a cross-sectional view showing the IGBT of Embodiment 1. FIG. As shown in FIG. 1, in the first embodiment, an n-channel IGBT is manufactured using an SOI substrate. The SOI substrate has a structure in which an insulating layer 2 made of an oxide film or the like, an n ⁺ minority carrier canceling layer 13a and an n ⁻ drift region 3a are laminated in this order on the p support substrate 1a.

The resistivity of n ⁻ drift region 3a is higher than that of n ⁺ minority carrier cancellation layer 13a. For this reason, the n ⁺ minority carrier canceling layer 13a has a gettering effect against metal ion contamination, and also serves as a getter layer. The n ⁻ drift region 3a corresponds to the first semiconductor region, and the n ⁺ minority carrier canceling layer 13a corresponds to a semiconductor layer provided on the support substrate via an insulating layer.

The n well region 3b is provided in a part of the surface layer of n ⁻ drift region 3a. n-well region (3b) is n ^- and is heavily doped than the drift region (3a), n ^- have a lower resistivity than the drift region (3a). For this reason, the increase of the resistance of the n well region 3b by the JFET (junction type | mold FET) effect with the P base area | region 4a mentioned later is suppressed.

p base region (4a) is n ^- the part of the surface layer of the drift region (3a), n ^- are provided in contact with the drift region (3a) and the n-well region (3b). The n well region 3b and the p base region 4a correspond to the second semiconductor region and the third semiconductor region, respectively.

On a part of the p base region 4a and the surface of the n well region 3b, a gate electrode 8a is provided through the gate insulating film 9a. The gate electrode 8a is made of conductive polysilicon, for example. In the figure, a thick insulating film 9c is formed on the surface of the n well region 3b to reduce the capacitance, and a gate electrode 8a is provided thereon. In a part other than the p base region 4a, p ⁺ low resistance region 5a and p ⁺ base contact region 5b are provided. A part of p ⁺ low resistance region 5a is provided with n ⁺ emitter region 6a. The n ⁺ emitter region 6a is provided to match the p base region side end portion (the end on the n ⁺ emitter region 6a in FIG. 1) of the gate electrode 8a. The gate electrode 8a may be provided on the surface of the p base region 4a between the n well region 3b and the n ⁺ emitter region 6a and may not necessarily be provided on the n well region 3b.

When the gate voltage exceeds the threshold voltage, a channel is formed at the interface between the p base region 4a between the n ⁺ emitter region 6a and the n well region 3b and the gate insulating film 9a. In the p base region 4a, p ⁺ low resistance region 5a is formed to occupy the lower side of n ⁺ emitter region 6a, and P ⁺ base contact region 5b is n ⁺ emitter region 6a. It is installed adjacent to). The p ⁺ base contact region 5b corresponds to the high conductivity region. The p ⁺ low resistance region 5a is preferably formed so as to occupy the lower side of the n ⁺ emitter region 6a in a range that does not affect the threshold voltage as in the present embodiment, but the n ⁺ emitter region 6a It may be formed in the lower part of ().

On the outer side of the p base region side end portion of the gate electrode 8a, a gate sidewall spacer region 18 made of an oxide film or a nitride film is provided in contact with the end portion thereof. Using this gate sidewall spacer region 18, p ⁺ low resistance region 5a is formed so as not to enter the region where a channel is formed. As a result, the p ⁺ low resistance region 5a does not affect the threshold value of the gate voltage forming the channel.

In addition, an n buffer region 11a is provided in a part of the surface layer of the n ⁻ drift region 3a away from the n well region 3b and the p base region 4a. n buffer area (11a) is n ^- doped at a high concentration than the drift region (3a) and, n ^- have a lower resistivity than the drift region (3a).

The n buffer region 11a corresponds to the fourth semiconductor region, and becomes an drift region for maintaining the breakdown voltage of the device together with the n ⁻ drift region 3a and the n well region 3b. In this manner, the device is a punch-through type IGBT having n buffer regions 11a.

A p ⁺ collector region 12a is provided in a portion of the n buffer region 11a, and is separated from the n ⁻ drift region 3a by the n buffer region 11a. p ⁺ collector region 12a becomes a carrier injection region for conductivity modulation. The n buffer region 11a controls the amount of conductivity modulated carrier injected from the p ⁺ collector region 12a and is related to the trade-off between the element on resistance and the turn-off loss.

Between the n well region 3b and the p base region 4a and the n buffer region 11a, the upper trench 16a is deeper than the p base region 4a from the surface of the SOI substrate to the n ⁻ drift region 3a. It is formed to the position to reach. From the bottom of the upper trench 16a, the lower trench 16b, which is narrower than the upper trench 16a, is formed to a deeper position.

These upper trenches 16a and lower trenches 16b are filled with a trench filling insulating film 17 such as an oxide film. The trench buried insulating film 17 is in contact with the n ⁻ drift region 3a, the p base region 4a and the p ⁺ base contact region 5b on the emitter side sidewall of the upper trench 16a.

The emitter side field plate 15 made of conductive polysilicon or the like is electrically embedded in the trench filling insulating film 17 near the emitter side sidewall of the upper trench 16a. The emitter side field plate 15 may be provided over the top and bottom of the PN junction surface formed of the p base region 4a and the n ⁻ drift region 3a. The emitter side field plate 15 corresponds to the emitter side conductive region.

The trench buried insulating film 17 is in contact with the n ⁻ drift region 3a and the n buffer region 11a on the collector sidewall of the upper trench 16a. A collector side field plate 14 made of conductive polysilicon or the like is provided near the collector side sidewall of the upper trench 16a in the trench filling insulating film 17. The collector-side field plate 14 corresponds to the collector-side conductive region, is electrically connected to the collector electrode 10 provided in contact with the p ⁺ collector region 12a via an internal wiring or an external wiring, and the collector electrode 10 And coin will be.

The collector-side field plate 14 prevents depletion of the interface between the upper trench 16a and the n ⁻ drift region 3a and the n buffer region 11a, thereby contributing to the higher withstand voltage of the device. In other words, the collector-side field plate 14 is provided, so that the internal pressure of the device can be increased. The collector side field plate 14 may be provided over the top and bottom of the interface with the n ⁻ drift region 3a and the n buffer region 11a.

In contact with both n ⁺ emitter region 6a and p ⁺ base contact region 5b, the p ⁺ base contact region 5b and n ⁺ emitter region 6a are short-circuited to emitter electrode 7 Is installed. In Fig. 1, reference numeral 20 denotes an insulating film cover layer such as an oxide film provided to reduce plasma etching damage to the gate insulating film 9a at the time of manufacture, and 21 denotes an interlayer insulating film.

In the above configuration, a gate structure having a bypass structure for bypassing the conductivity modulated carrier is given. That is, a part of the carrier injected from the p ⁺ collector region 12a passes through the interface between the p base region 4a and the n ⁻ drift region 3a, the p base region 4a and the p ⁺ base contact region 5b. The emitter electrode 7 is reached.

The other carriers injected from the p ⁺ collector region 12a are the n well region 3b, the surface channel at the interface between the p base region 4a and the gate insulating film 9a, p ⁺ low resistance region 5a and p ^+. Through the base contact region 5b, the emitter electrode 7 is reached. This bypass structure prevents the device from latching up well, thereby improving latchup resistance.

Next, the manufacturing process of the device of the structure shown in FIG. 1 is demonstrated, referring FIGS. First, as shown in FIG. 2, the screen oxide film 31 is formed on the surface of the wafer of n <^-> semiconductor used as n <^-> drift area | region 3a. As a result, thermal diffusion is performed by ion implantation of As (arsenic) as an n-type impurity, and as shown in Fig. 3, an n ⁺ minority carrier canceling layer 13a is formed on the wafer surface. 4, the screen oxide film 31 is removed. Up to this point, the device wafer is completed.

On the other hand, as shown in FIG. 5, the p support substrate 1a is prepared. 6, the insulating layer 2, such as an oxide film, is formed in the surface of p support substrate 1a, and it is set as a handle wafer. Subsequently, as shown in FIG. 7, the surface of the insulating layer 2 of the handle wafer and the surface of the n ⁺ minority carrier canceling layer 13a of the device wafer are bonded. At that time, the device wafer and the handle wafer are combined and integrated through a natural oxide film on the surface of the device wafer. As shown in FIG. 8, the n ⁻ drift region 3a of the integrated SOI wafer is polished to a predetermined thickness. Up to this point, the SOI wafer is completed.

Although not particularly shown in the subsequent manufacturing process, the n well region 3b and the n buffer region (on the surface of the SOI wafer, i.e., the polished surface of the n ⁻ drift region 3a) are continuously formed by ion implantation such as phosphorus. An n diffusion layer to be 11a) is formed. Subsequently, ion implantation such as boron is performed, and thermal diffusion is performed to form the p base region 4a.

Subsequently, a hard mask for trench etching is formed, and the bottom trench 16b is formed by trench etching. After the damage of the trench etching is removed by sacrificial oxidation or the like, an insulating film such as an oxide film is deposited on the entire surface of the wafer.

After the deposited insulating film surface is planarized by CMP, a hard mask for trench etching is formed, and the upper trench 16a is formed by etching the upper portions of both side walls of the lower trench 16b. After the damage of the trench etching is removed by sacrificial oxidation or the like, an insulating film such as an oxide film or the like is deposited on the sidewall and the bottom surface of the upper trench 16a. Next, a conductive polysilicon film is deposited on the upper trench 16a.

After the deposited conductive polysilicon film is etched back, an insulating film such as an oxide film is deposited on the entire surface of the wafer and planarized by CMP. After that, an insulating film on the trench 16a and the trench 16b is left to expose the wafer surface. Using the nitride film as a mask, the LOCOS oxide film serving as the insulating film 9c is formed on the exposed wafer surface.

Next, an oxide film to be the gate insulating film 9a is grown thereon. On the gate insulating film 9a and the insulating film 9c, doped polysilicon to be the gate electrode 8a is deposited to a thickness of 300 nm to 400 nm.

Further, an oxide film or the like serving as the insulating film cover layer 20 is deposited to a thickness of 300 nm to 500 nm. Since the insulating film cover layer 20 is present, in this embodiment, the thickness of the doped polysilicon to be the gate electrode 8a can be reduced to 300 nm to 400 nm, so that the gate polysilicon of the LV (low voltage) CMOS device can be made thin. Common with is easy.

Subsequently, a gate stack structure made of the insulating film cover layer 20, the gate electrode 8a, and the gate insulating film 9a is formed by RIE (reactive ion etching). In that case, the plasma etching damage to the gate insulating film 9a is reduced by providing the oxide film etc. used as the insulating film cover layer 20.

After shadow oxidation is performed, ion implantation of arsenic or the like is performed by self-alignment (self-alignment technique) to form n ⁺ emitter regions 6a. Subsequently, a gate sidewall spacer region 18 is formed on the side of the gate stack structure. At this time, the thickness of the gate sidewall spacer region 18 needs to be about 150 nm to 200 nm. This is because in the following boron ion implantation step, the lateral range of boron ions is offset to suppress the influence of the threshold value of the gate voltage forming the channel. to be.

Thereafter, for example, boron is implanted at a high energy of 70 keV to 90 keV and a dose of 1 × 10 ¹⁵ cm ^-2 to 3 × 10 ¹⁵ cm ^-2 to form the bottom of the n ⁺ emitter region 6a. P ⁺ low resistance region 5a is formed in the substrate. At that time, implantation of boron ions into the channel region is prevented by the insulating film cover layer 20 and the gate electrode 8a, thereby protecting the channel region.

Subsequently, p ⁺ base contact regions 5b and p ⁺ collector regions 12a are formed by ion implantation of boron. Subsequently, an interlayer insulating film 21 is deposited on the entire wafer surface, and the upper surface is planarized by CMP (chemical mechanical polishing). Then, a contact hole is opened in the planarized interlayer insulating film 21, the metal is sputtered to form the emitter electrode 7 and the collector electrode 10, and the front end process is completed.

By the way, regarding the manufacture of the above-mentioned SOI wafer, the following report is reported.

First, it is a report about suppression of generation of OSF (oxidation introduction lamination defect) and BMD (bulk fine defect). The balance between the air holes and the lattice atoms formed in the wafer withdrawal process by the Czochralski method is broken by, for example, ion implantation of boron at a high dose amount. For this reason, when the first annealing treatment after ion implantation is performed at a temperature of 900 ° C. or lower, many OSFs and BMDs are generated.

As a countermeasure, Jeong-Min Kim et al., `` Behavior of Thermally Induced Defects in Heavily Boron-Doped Silicon Crystals '' ( In the Japanese Journal of Applied Physics, March 2001, Volume 40, Part 1, 3A, p. 1370-1374, the first annealing treatment was conducted at high temperature (1050 ° C.). It is reported that the generation of OSF and BMD can be suppressed.

In addition, the following has been reported regarding the bonding of wafers.

When fabricating a bonded SOI wafer, the surface of the bonded wafer becomes a mirror quality surface necessary for bonding the wafers together. As a mechanism for bonding silicon wafers together, it is known that wafers are integrated through H ₂ O adsorbed to “Si—OH—” on the surfaces of each other.

In this regard, R. Stengl et al., `` A Model for the Silicon Wafer Bonding Process '' (Japanese Journal of Applied Physics, October 1989) , Vol. 28, No. 10, p. 1735-1741), when heated to 200 ° C. or higher, the water molecules become tetramer clusters, and when heated to 700 ° C. or higher, the water clusters evaporate. Si-0-Si ”is reported to bond wafers together. Moreover, when heated to 1100 degreeC, it is reported that the insulating layer (embedded oxide film layer) of an SOI wafer reflows, and the bond strength of wafers becomes further higher.

In addition, bonding of wafers can be carried out if there is a hydroxyl group ("-OH") on the wafer surface of mirror quality before the bonding. Hiroaki Himi et al., `` Silicon Wafer Direct Bonding without Hydrophilic Native Oxides '' (Japanese Journal of Applied Physics, 1994 In January, Vol. 33, No. 1, No. 1A, p. 6-10), the surface density adhered to the surface of the device wafer by immersion in deionized water immediately after treating the device wafer with high concentration hydrofluoric acid After replacing high "-F" with "-OH", the method of joining a device wafer with the handle wafer in which the insulating layer was formed is reported.

In the present embodiment, the three reports described above can be applied to fabricating an SOI wafer.

According to the structure of Embodiment 1 mentioned above, when ensuring the withstand voltage of 200 V class, the device pitch of the structure shown in FIG. 1 is 12 micrometers or less, and the thickness of n ^- drift area | region 3a is 20 micrometers or less Since it can suppress, the device pitch of the structure shown in FIG. 1 becomes less than half the cell pitch (25 micrometers) of the conventional device shown in FIG. In addition, the current driving capability of the unit cell device having the configuration shown in FIG. 1 is about the same as that of the conventional horizontal device by the optimization of the device structure and the manufacturing process. Therefore, in the device having the configuration shown in FIG. 1, the on resistance per unit area is 250 mΩ · mm ² , which is half of the on resistance (500 mΩ · mm ² ) of the conventional device. It is about.

As an example, in the configuration shown in Fig. 1, D1 is 0.5 µm, D2 is 0.6 µm, 2D3 is 1.8 µm, and the thickness of n ^- drift region 3a is 12. 9 shows the relationship between the off breakdown voltage (breakdown voltage) of the device and the doping concentration of the n ⁻ drift region 3a when the µm or 16 µm is set. In addition, in the structure shown in FIG. 1, D1 is 0.5 micrometer, D2 is 0.6 micrometer, 2D3 is 1.8 micrometer, and the thickness of n ^- drift area | region 3a is 16 micrometer. FIG. 10 shows the electrostatic potential distribution at the time of breakdown when the doping concentration of the n ⁻ drift region 3a is 3 × 10 ¹⁴ cm ⁻³ . In FIG. 10, X represents the dimension of the device in the transverse direction, and Y represents the dimension of the device in the longitudinal direction.

FIG. 11 is a p-channel IGBT inverting the polarity of the n-channel IGBT having the configuration shown in FIG. 1. As for the p-channel IGBT, in the description of Embodiment 1 described above, p support substrate 1a, n ⁺ minority carrier cancellation layer 13a, n ^- drift region 3a, n well region 3b, and p base It is assumed that the region 4a is replaced with the n support substrate 1b, the p ⁺ minority carrier cancellation layer 13b, the p ⁻ drift region 3c, the p well region 3d and the n base region 4b, respectively. .

In addition, p ⁺ low resistance region 5a, p ⁺ base contact region 5b, n ⁺ emitter region 6a, n buffer region 11a and p ⁺ collector region 12a, respectively, n ⁺ low resistance region (5c), n ⁺ base contact region 5d, p ⁺ emitter region 6b, p buffer region 11b and n ⁺ collector region 12b. In addition, with respect to the implanted ion species in the manufacturing process, n-type impurities and p-type impurities are replaced.

Embodiment 2

12 and 13 are cross-sectional views showing the n-channel IGBT and the p-channel IGBT of Embodiment 2, respectively. As shown in FIG. 12 and FIG. 13, the IGBT of Embodiment 2 has a plurality (two in the example) of channels for each of the single drift regions 3a and 3c in the IGBT of Embodiment 1. The configuration has a high current capability.

Specifically, in the n-channel IGBT shown in FIG. 12, a plurality of, for example, two p-base regions 4a are provided on the emitter side of the trench filling insulating film 17 with the n well region 3b interposed therebetween. have. In each p base region 4a, p ⁺ low resistance region 5a, p ⁺ base contact region 5b and n ⁺ emitter region 6a are provided. On the p base region 4a between each n ⁺ emitter region 6a and the n well region 3b, a planar gate structure composed of a gate insulating film 9a and a gate electrode 8a is provided. A channel is formed at the interface between each p base region 4a and the gate insulating film 9a thereon.

In addition, adjacent n ⁺ emitter regions 6a and p ⁺ base contact regions 5b are electrically connected to each other by the emitter electrode 7. Since the other structure is the same as that of the IGBT of Embodiment 1, description is abbreviate | omitted.

In the case of the p-channel IGBT shown in FIG. 13, the polarity is replaced in the same manner as in the first embodiment.

Embodiment 3

14 and 15 are cross-sectional views illustrating the n-channel IGBT and the p-channel IGBT of Embodiment 3, respectively. As shown in FIGS. 14 and 15, each of the IGBTs of Embodiment 3, in each of the IGBTs of Embodiment 1, instead of the top trench 16a and the bottom trench 16b, until it reaches the trench bottom from the wafer surface. A trench 16c having a constant width is provided, and a trench filling insulating film 17 is embedded therein. Since the other structure is the same as that of the IGBT of Embodiment 1, description is abbreviate | omitted.

Embodiment 4

16 and 17 are cross-sectional views illustrating the n-channel IGBT and the p-channel IGBT of Embodiment 4, respectively. As shown in FIG. 16 and FIG. 17, each IGBT of Embodiment 4 combines the IGBTs of the corresponding polarity of Embodiment 2 and Embodiment 3, respectively. That is, each of the single drift regions 3a and 3c has a plurality of channels (two in the illustrated example), and a trench 16c having a constant width is provided from the wafer surface to the trench bottom, and the trench therein. The buried insulating film 17 is embedded. Since the other structure is the same as that of the IGBT of Embodiment 2 and the structure of the IGBT of Embodiment 3, description is abbreviate | omitted.

Embodiment 5

18 and 19 are sectional views showing the n-channel IGBT and the p-channel IGBT of Embodiment 5, respectively. As shown in FIG. 18 and FIG. 19, each IGBT of Embodiment 5 has a trench gate structure instead of the planar gate structure of each IGBT of Embodiment 1, and has the advantage that latchup does not work well.

Specifically, in the case of the n-channel IGBT shown in FIG. 18, the gate trench 19 that penetrates the p base region 4a from the wafer surface and reaches the n ⁻ drift region 3a is formed from the trench filling insulating film 17. Falling, and is formed in contact with the p base region 4a. The gate electrode 8b is buried inside the gate trench 19 through the gate insulating film 9b. In part of the p base region 4a, n ⁺ emitter region 6a is provided in contact with the gate trench 19.

Further, p ⁺ low resistance region 5a is provided adjacent to n ⁺ emitter region 6a in a part of p base region 4a. In contact with both n ⁺ emitter region 6a and p ⁺ low resistance region 5a, emitter electrode 7 shorts p ⁺ low resistance region 5a and n ⁺ emitter region 6a and have. In the IGBT of Embodiment 5, the n well region 3b in contact with the p base region 4a is not provided. Since the other structure is the same as that of the IGBT of Embodiment 1, description is abbreviate | omitted.

In the case of the p-channel IGBT shown in FIG. 19, the polarity is replaced in the same manner as in the first embodiment.

Embodiment 6

20 and 21 are cross-sectional views showing the n-channel IGBT and the p-channel IGBT of Embodiment 6, respectively. 20 and 21, the IGBT of the sixth embodiment has a plurality of channels (three in the illustrated example) for each of the single drift regions 3a and 3c in the IGBT of the fifth embodiment. The configuration has a high current capability. Since the other structure is the same as that of the IGBT of Embodiment 5, description is abbreviate | omitted.

Embodiment 7

22 and 23 are cross-sectional views illustrating n-channel IGBTs and p-channel IGBTs according to the seventh embodiment, respectively. As shown in FIGS. 22 and 23, each of the IGBTs of the seventh embodiment, in each of the IGBTs of the fifth embodiment, instead of the top trench 16a and the bottom trench 16b, until it reaches the trench bottom from the wafer surface. A trench 16c having a constant width is provided, and a trench filling insulating film 17 is embedded therein. Since the other structure is the same as that of the IGBT of Embodiment 5, description is abbreviate | omitted.

Embodiment 8

24 and 25 are cross-sectional views illustrating the n-channel IGBT and the p-channel IGBT of the eighth embodiment, respectively. As shown in FIG. 24 and FIG. 25, each IGBT of Embodiment 8 combines the IGBTs of the corresponding polarity of Embodiment 6 and Embodiment 7, respectively. That is, each of the single drift regions 3a and 3c has a plurality of channels (three in the illustrated example), and a trench 16c of constant width is provided from the wafer surface to the trench bottom, and the trench therein. The buried insulating film 17 is embedded. Since other configurations are the same as the configuration of the IGBT of Embodiment 6 and the configuration of the IGBT of Embodiment 7, description thereof is omitted.

Embodiment 9

26 and 27 are cross-sectional views illustrating the n-channel IGBT and the p-channel IGBT of Embodiment 9, respectively. As shown in FIG. 26 and FIG. 27, each IGBT of Embodiment 9 does not provide the collector side field plate 14 in each IGBT of Embodiment 1. As shown in FIG. In the n-channel IGBT, the upper trench 16a and the n buffer region 11a are separated, and the n ^- drift region 3a is sandwiched between the upper trench 16a and the n buffer region 11a, thereby providing an n buffer region. The influence on the breakdown voltage of the device due to the depletion of the interface between (11a) and the n ⁻ drift region 3a is suppressed.

Similarly, in the p-channel IGBT, the upper trench 16a and the p buffer region 11b are separated, and the p ^- drift region 3c is sandwiched therebetween, whereby the p buffer region 11b and the p ^- drift region 3c. The influence on the internal pressure of the device due to the depletion of the interface with) is suppressed. Therefore, the device pitch of each IGBT of Embodiment 9 is slightly longer than the device pitch of each IGBT of Embodiment 1, but is shorter than the cell pitch of the conventional device shown in FIG.

In addition, since the current driving capability of the unit cell device of each IGBT of Embodiment 9 is about the same as the current driving capability of the conventional horizontal device by optimization of the device structure and manufacturing process, the unit of each IGBT of Embodiment 9 The on resistance per area is smaller than that of the conventional device, and the short circuit resistance is also improved. Since the other structure is the same as that of the IGBT of Embodiment 1, description is abbreviate | omitted.

Embodiment 10

28 and 29 are cross-sectional views illustrating the n-channel IGBT and the p-channel IGBT of the tenth embodiment, respectively. As shown in FIG. 28 and FIG. 29, the IGBT of the tenth embodiment has a plurality of channels (two in the illustrated example) for each of the single drift regions 3a and 3c in the IGBT of the ninth embodiment. The configuration has a high current capability. Since the other structure is the same as that of the IGBT of Embodiment 9, description is abbreviate | omitted.

Embodiment 11

30 and 31 are cross sectional views illustrating the n-channel IGBT and the p-channel IGBT of Embodiment 11, respectively. 30 and 31, each of the IGBTs of the eleventh embodiment, in each of the IGBTs of the ninth embodiment, instead of the upper trench 16a and the lower trench 16b, reaches the trench bottom from the wafer surface. A trench 16c having a constant width is provided, and a trench filling insulating film 17 is embedded therein. Since the other structure is the same as that of the IGBT of Embodiment 9, description is abbreviate | omitted.

Embodiment 12

32 and 33 are cross-sectional views illustrating the n-channel IGBT and the p-channel IGBT of the twelfth embodiment, respectively. 32 and 33, each IGBT of the twelfth embodiment is a combination of the IGBTs of the corresponding polarities of the tenth and eleventh embodiments, respectively. That is, each of the single drift regions 3a and 3c has a plurality of channels (two in the illustrated example), and a trench 16c having a constant width is provided from the wafer surface to the trench bottom, and the trench therein. The buried insulating film 17 is embedded. Since other configurations are the same as those of the IGBT of the tenth embodiment and the configurations of the IGBT of the eleventh embodiment, description thereof is omitted.

Embodiment 13

34 and 35 are cross-sectional views illustrating the n-channel IGBT and the p-channel IGBT of Embodiment 13, respectively. As shown in FIG. 34 and FIG. 35, each IGBT of Embodiment 13 does not provide the collector side field plate 14 in each IGBT of Embodiment 5. As shown in FIG. In the n-channel IGBT, the upper trench 16a and the n buffer region 11a are separated, and the n ^- drift region 3a is sandwiched between the upper trench 16a and the n buffer region 11a to thereby n buffer. The influence on the breakdown voltage of the device due to the depletion of the interface between the region 11a and the n ⁻ drift region 3a is suppressed.

Similarly, in the p-channel IGBT, the upper trench 16a and the p buffer region 11b are separated, and the p ^- drift region 3c is sandwiched therebetween, whereby the p buffer region 11b and the p ^- drift region 3c. The influence on the internal pressure of the device due to the depletion of the interface with) is suppressed. Therefore, although the device pitch of each IGBT of Embodiment 13 is slightly longer than the device pitch of each IGBT of Embodiment 5, it is shorter than the cell pitch of the conventional device shown in FIG.

Further, since the current driving capability of the unit cell device of each IGBT of the thirteenth embodiment is about the same as the current driving capability of the conventional horizontal device by optimization of the device structure and the manufacturing process, the unit area per each IGBT of the thirteenth embodiment The on resistance of becomes smaller than the on resistance of the conventional device. Since the other structure is the same as that of the IGBT of Embodiment 5, description is abbreviate | omitted.

Embodiment 14

36 and 37 are cross-sectional views illustrating the n-channel IGBT and the p-channel IGBT of Embodiment 14, respectively. 36 and 37, the IGBT of the fourteenth embodiment has a plurality of channels (three in the illustrated example) for each of the single drift regions 3a and 3c in the IGBT of the thirteenth embodiment. The configuration has a high current capability. Since the other structure is the same as that of the IGBT of Embodiment 13, description is abbreviate | omitted.

Embodiment 15

38 and 39 are cross-sectional views illustrating the n-channel IGBT and the p-channel IGBT of the fifteenth embodiment, respectively. 38 and 39, each of the IGBTs of the fifteenth embodiment, in each of the IGBTs of the thirteenth embodiment, instead of the top trench 16a and the bottom trench 16b, until it reaches the trench bottom from the wafer surface. A trench 16c having a constant width is provided, and a trench filling insulating film 17 is embedded therein. Since the other structure is the same as that of the IGBT of Embodiment 13, description is abbreviate | omitted.

Embodiment 16

40 and 41 are cross-sectional views illustrating the n-channel IGBT and the p-channel IGBT of the sixteenth embodiment, respectively. As shown in FIG. 40 and FIG. 41, each IGBT of Embodiment 16 combines the IGBT of the corresponding polarity of Embodiment 14 and Embodiment 15, respectively. That is, each of the single drift regions 3a and 3c has a plurality of channels (three in the illustrated example), and a trench 16c of constant width is provided from the wafer surface to the trench bottom, and the trench therein. The buried insulating film 17 is embedded. The other configuration is the same as the configuration of the IGBT of Embodiment 14 and the configuration of the IGBT of Embodiment 15, and thus description thereof is omitted.

Embodiment 17

42 and 43 are cross-sectional views illustrating the n-channel IGBT and the p-channel IGBT of Embodiment 17, respectively. As shown in Figs. 42 and 43, in the n-channel IGBT of Embodiment 17, in the n-channel IGBT of Embodiment 1, the trench filling insulating film 17 is n ^- drift region 3a, n well region 3b. And only the n buffer region 11a. That is, the trench filling insulating layer 17 does not contact the p base region 4a and the p ⁺ base contact region 5b.

For this reason, in the seventeenth embodiment, the emitter side field plate 15 is not necessary. Carriers injected from the p ⁺ collector region 12a are the surface channels of the interface between the n well region 3b, the p base region 4a and the gate insulating film 9a, the p ⁺ low resistance region 5a and the p ⁺ base. The emitter electrode 7 is reached through the contact region 5b.

Similarly, in the p-channel IGBT, the trench buried insulating film 17 contacts only the p ⁻ drift region 3c, the p well region 3d, and the p buffer region 11b, and the n base region 4b and the n ⁺ base contact. There is no contact with the region 5d. Therefore, the emitter side field plate 15 is not provided. The carrier injected from the n ⁺ collector region 12b is a surface channel of an interface between the p well region 3d, the n base region 4b and the gate insulating film 9a, the n ⁺ low resistance region 5c and the n ⁺ base. The emitter electrode 7 is reached through the contact region 5d.

The device pitch of each IGBT of Embodiment 17 is shorter than the cell pitch of the conventional device shown in FIG. In addition, since the current driving capability of the unit cell device of each IGBT of Embodiment 17 is about the same as the current driving capability of the conventional horizontal device by optimization of the device structure and manufacturing process, per unit area of each IGBT of Embodiment 17 The on resistance of becomes smaller than the on resistance of the conventional device. Since the other structure is the same as that of the IGBT of Embodiment 1, description is abbreviate | omitted.

Embodiment 18

44 and 45 are sectional views illustrating the n-channel IGBT and the p-channel IGBT of Embodiment 18, respectively. 44 and 45, each of the IGBTs of the eighteenth embodiment, in each of the IGBTs of the seventeenth embodiment, instead of the top trench 16a and the bottom trench 16b, until it reaches the trench bottom from the wafer surface. A trench 16c having a constant width is provided, and a trench filling insulating film 17 is embedded therein. Since other configurations are the same as those of the IGBT of the seventeenth embodiment, description thereof is omitted.

Embodiment 19

46 and 47 are sectional views illustrating the n-channel IGBT and the p-channel IGBT of Embodiment 19, respectively. 46 and 47, in the n-channel IGBT of Embodiment 19, in the n-channel IGBT of Embodiment 1, the trench buried insulating film 17 is n ⁻ drift region 3a and n well region 3b. Is in contact only, and is not in contact with the p base region 4a and the p ⁺ base contact region 5b. For this reason, the emitter side field plate 15 is not necessary.

Further, the trench 16c and the n buffer region 11a are separated without providing the collector side field plate 14, and the n ⁻ drift region 3a is sandwiched therebetween, thereby providing the n ⁻ buffer region 11a. ) And the influence on the breakdown voltage of the device due to the depletion of the interface between the n ⁻ drift region 3a are suppressed. Carriers injected from the p ⁺ collector region 12a are the surface channels of the interface between the n well region 3b, the p base region 4a and the gate insulating film 9a, the p ⁺ low resistance region 5a and the p ⁺ base. The emitter electrode 7 is reached through the contact region 5b.

Similarly, in the p-channel IGBT, the trench filling insulating film 17 is in contact only with the p ⁻ drift region 3c and the p well region 3d, and with the n base region 4b and n ⁺ base contact region 5d. I never do that. Therefore, the emitter side field plate 15 is not provided.

The p buffer region 11b is formed by separating the trench 16c and the p buffer region 11b without interposing the collector side field plate 14 and sandwiching the p ⁻ drift region 3c therebetween. The influence on the breakdown voltage of the device due to the depletion of the interface between the p ^- drift region 3c is suppressed. The carrier injected from the n ⁺ collector region 12b is a surface channel of an interface between the p well region 3d, the n base region 4b and the gate insulating film 9a, the n ⁺ low resistance region 5c and the n ⁺ base. The emitter electrode 7 is reached through the contact region 5d.

The device pitch of each IGBT of Embodiment 19 is slightly longer than the device pitch of each IGBT of Embodiment 17 or Embodiment 18, but is shorter than the cell pitch of the conventional device shown in FIG. In addition, since the current driving capability of the unit cell device of each IGBT of Embodiment 19 is about the same as the current driving capability of the conventional horizontal device by optimization of the device structure and manufacturing process, per unit area of each IGBT of Embodiment 19 The on resistance of becomes smaller than the on resistance of the conventional device. Since the other structure is the same as that of the IGBT of Embodiment 1, description is abbreviate | omitted.

Here, the difference between the device of Embodiment 19 and the device disclosed in Patent Document 2 will be described. In the device of Embodiment 19, since n ⁺ minority carrier canceling layer 13a (p ⁺ minority carrier canceling layer 13b) is in contact with the insulating layer 2 as a whole, the SOI is described by the bonding method described in Embodiment 1. Bonding accuracy is not required when fabricating a wafer. Therefore, it can manufacture easily. On the other hand, in the device disclosed in the patent document 2, since the bonding precision of the µm order is required, manufacturing is not preferable as described above.

48 is a figure which shows an example of the planar layout of the device of 19th embodiment. As shown in FIG. 48, in the device of Embodiment 19, the trench filling insulating film 17 is formed of n ⁺ emitter region 6a (p ⁺ emitter region 6b) and p ⁺ collector region 12a (n ⁺ ). Since the collector region 12b is disposed on the entire wafer surface, the effective drift length is long, and the cell pitch on the wafer surface is shortened. On the other hand, in the device disclosed in Patent Document 2, the cell pitch cannot be shortened as described above.

In the device of the nineteenth embodiment, the distance between the trench filling insulating film 17 and the n ⁺ minority carrier canceling layer 13a (p ⁺ minority carrier canceling layer 13b) is similar to the device disclosed in Patent Document 2. By this, the amount of minority carriers injected from p ⁺ collector region 12a (n ⁺ collector region 12b) is limited. On the other hand, since the conduction of the majority carriers flowing through the channel is not disturbed, the concentration of the majority carriers on the channel side is kept high, which has the effect of lowering the channel resistance. Further, since the n-well region 3b (p-well region 3d) is provided, the JFET effect is suppressed, so that the on resistance can be reduced and the cell pitch can be shortened. Moreover, since p ⁺ low resistance area | region 5a (n ⁺ low resistance area | region 5c) is provided, latch up tolerance further improves.

As described above, according to Embodiments 1 to 19, by forming the trench, a portion for maintaining the internal pressure is provided in the direction perpendicular to the wafer surface. As a result, since the drift region is bent in the depth direction of the wafer and drawn out on the wafer surface, the effective drift length increases. For this reason, even if the effective drift length is the length equivalent to the conventional one, the required surface area of the element is greatly reduced. Therefore, the on resistance per unit area is reduced.

Further, according to Embodiments 1 to 19, since the n ⁺ minority carrier offset layer 13a (p ⁺ minority carrier offset layer 13b) becomes a getter layer for metal contamination, a gettering effect on metal contamination can be obtained. Can be. Therefore, the reliability of the gate insulating films 9a and 9b is improved.

Further, according to Embodiments 1 to 19, n ⁺ minority carrier cancellation layer 13a (p ⁺ minority carrier cancellation layer 13b) has an interface with n ⁻ drift region 3a (p ⁻ drift region 3c). And the influence of defects in each of the interfaces with the insulating layer 2 are suppressed, and the depletion effect from the p support substrate 1a (n support substrate 1b) is suppressed. For this reason, n ^- drift region 3a (p ^- drift region 3c) behaves as if it is a bulk layer.

Furthermore, according to Embodiments 1 to 19, the dopant concentration of n ⁺ minority carrier canceling layer 13a (p ⁺ minority carrier canceling layer 13b) is high, and the life of the carrier is short. Therefore, p ⁺ collector region 12a depending on the bottom of the trench filling insulating film 17 and the distance between the insulating layer 2 and the n ⁺ minority carrier canceling layer 13a (p ⁺ minority carrier canceling layer 13b). The lifetime of the carrier injected from (n ⁺ collector region 12b) is controlled to maintain the balance between the reverse recovery time of the device and the on resistance.

Further, according to Embodiments 1 to 8, 17, and 18, the transverse electric field generated on the collector side of the trench filling insulating film 17 is shielded by the collector side field plate 14 and the trench filling insulating film 17, and n ⁻ drift. The electric field generated in the PN junction formed by the region 3a (p ^- drift region 3c) and the p base region 4a (n base region 4b) is relaxed. Therefore, electrical breakdown is less likely to occur. In addition, the collector side field plate 14 is coincident with the collector electrode 10, so that the n-buffer region 11a (p buffer region 11b), that is, the drift region on the collector side in contact with the trench-filling insulating film 17, is formed. Since the interface is not depleted well, it can play a role of supporting voltage.

Therefore, according to each embodiment, an IGBT having a withstand voltage and a current driving capability equal to or greater than that of a conventional horizontal semiconductor device using a SOI substrate, and having a higher latch-up resistance and a lower on-resistance per unit area than the conventional horizontal semiconductor device. You can get it. In addition, by using the SOI substrate, it is possible to easily integrate with the CM0S device.

In the above, this invention is not limited to each embodiment mentioned above, A various change is possible. In addition, the structure of the withstand voltage withstand according to the present invention can be applied to horizontal LDMOS transistors and the like requiring high breakdown voltage, and the on-resistance per unit area can be reduced.

As described above, the IGBT according to the present invention is useful for a high breakdown voltage switching element requiring a high latch-up tolerance, and is particularly suitable for a high breakdown voltage switching element used for an output terminal such as a driver IC or a vehicle IC of a flat panel display.

Claims (20)

A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A second conductive region of a first conductivity type provided in a part of the surface layer of the first semiconductor region, the resistivity of which is lower than that of the first semiconductor region; A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region; A gate electrode provided on a surface of a portion of the third semiconductor region via a gate insulating film; An emitter region of a first conductivity type provided in a portion of the third semiconductor region, A low resistance region of a second conductivity type provided in a part of the third semiconductor region, and provided below the emitter region; A high conductivity region of a second conductivity type provided in a part of the third semiconductor region adjacent to the emitter region, A fourth conductive region of a first conductivity type having a lower resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, away from the second semiconductor region and the third semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, An upper trench disposed between the second semiconductor region and the third semiconductor region and the fourth semiconductor region; A lower trench narrower than the upper trench, installed from a bottom of the upper trench to a deeper position, A trench buried insulating film buried in the upper trench and the lower trench; An emitter side conductive region of a floating potential buried in the vicinity of the third semiconductor region in the trench filling insulating film in the upper trench; A collector-side conductive region buried in the vicinity of the fourth semiconductor region in the trench filling insulating film in the upper trench; An emitter electrode in contact with the emitter region and the high conductivity region; A collector electrode in contact with the collector region and electrically connected to the collector side conductive region. SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A second conductive region of a first conductivity type provided in a part of the surface layer of the first semiconductor region, the resistivity of which is lower than that of the first semiconductor region; A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region; A gate electrode provided on a surface of a portion of the third semiconductor region via a gate insulating film; An emitter region of a first conductivity type provided in a portion of the third semiconductor region, A low resistance region of a second conductivity type provided in a part of the third semiconductor region, and provided below the emitter region; A high conductivity region of a second conductivity type provided in a part of the third semiconductor region adjacent to the emitter region, A fourth conductive region of a first conductivity type having a lower resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, away from the second semiconductor region and the third semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, A trench provided between the second semiconductor region and the third semiconductor region and the fourth semiconductor region; A trench buried insulating film embedded in the trench; An emitter side conductive region of a floating potential buried in the vicinity of the third semiconductor region in an upper half of the trench filling insulating film; A collector-side conductive region buried in the vicinity of the fourth semiconductor region in an upper half of the trench filling insulating film; An emitter electrode in contact with the emitter region and the high conductivity region; A collector electrode in contact with the collector region and electrically connected to the collector side conductive region. SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A third semiconductor region of a second conductivity type in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region; A gate electrode provided through the gate insulating layer inside the gate trench that passes through the third semiconductor region and reaches the first semiconductor region; An emitter region of a first conductivity type provided in a part of the third semiconductor region in contact with the gate trench; A low resistance region of a second conductivity type provided in a part of the third semiconductor region adjacent to the emitter region, A fourth semiconductor region of a first conductivity type having a resistivity lower than that of the first semiconductor region, provided in a part of the surface layer of the first semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, An upper trench disposed between the third semiconductor region and the fourth semiconductor region; A lower trench narrower than the upper trench, installed from a bottom of the upper trench to a deeper position, A trench buried insulating film buried in the upper trench and the lower trench; An emitter side conductive region of a floating potential buried in the vicinity of the third semiconductor region in the trench filling insulating film in the upper trench; A collector-side conductive region buried in the vicinity of the fourth semiconductor region in the trench filling insulating film in the upper trench; An emitter electrode in contact with the emitter region and the low resistance region; A collector electrode in contact with the collector region and electrically connected to the collector side conductive region. SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A third semiconductor region of a second conductivity type in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region; A gate electrode provided through a gate insulating film inside the gate trench penetrating the third semiconductor region and reaching the first semiconductor region, and a first conductive type provided in a part of the third semiconductor region in contact with the gate trench; Emitter area of, A low resistance region of a second conductivity type provided in a part of the third semiconductor region adjacent to the emitter region, A fourth semiconductor region of a first conductivity type having a resistivity lower than that of the first semiconductor region, provided in a part of the surface layer of the first semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, A trench provided between the third semiconductor region and the fourth semiconductor region; A trench buried insulating film embedded in the trench; An emitter side conductive region of a floating potential buried in the vicinity of the third semiconductor region in an upper half of the trench filling insulating film; A collector-side conductive region buried in the vicinity of the fourth semiconductor region in an upper half of the trench filling insulating film; An emitter electrode in contact with the emitter region and the low resistance region; A collector electrode in contact with the collector region and electrically connected to the collector side conductive region. SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A second conductive region of a first conductivity type provided in a part of the surface layer of the first semiconductor region, the resistivity of which is lower than that of the first semiconductor region; A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region; A gate electrode provided on a surface of a portion of the third semiconductor region via a gate insulating film; An emitter region of a first conductivity type provided in a portion of the third semiconductor region, A low resistance region of a second conductivity type provided in a part of the third semiconductor region, and provided below the emitter region; A high conductivity region of a second conductivity type provided in a part of the third semiconductor region adjacent to the emitter region, A fourth conductive region of a first conductivity type having a lower resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, away from the second semiconductor region and the third semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, An upper trench disposed away from the fourth semiconductor region between the second semiconductor region and the third semiconductor region and the fourth semiconductor region; A lower trench narrower than the upper trench, installed from a bottom of the upper trench to a deeper position, A trench buried insulating film buried in the upper trench and the lower trench; An emitter side conductive region of a floating potential buried in the vicinity of the third semiconductor region in the trench filling insulating film in the upper trench; An emitter electrode in contact with the emitter region and the high conductivity region; Collector electrode in contact with the collector region SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A second conductive region of a first conductivity type provided in a part of the surface layer of the first semiconductor region, the resistivity of which is lower than that of the first semiconductor region; A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region; A gate electrode provided on a surface of a portion of the third semiconductor region via a gate insulating film; An emitter region of a first conductivity type provided in a portion of the third semiconductor region, A low resistance region of a second conductivity type provided in a part of the third semiconductor region, and provided below the emitter region; A high conductivity region of a second conductivity type provided in a part of the third semiconductor region adjacent to the emitter region, A fourth conductive region of a first conductivity type having a lower resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, away from the second semiconductor region and the third semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, Trenches disposed away from the fourth semiconductor region between the second semiconductor region and the third semiconductor region and the fourth semiconductor region; A trench buried insulating film embedded in the trench; An emitter side conductive region of a floating potential buried in the vicinity of the third semiconductor region in an upper half of the trench filling insulating film; An emitter electrode in contact with the emitter region and the high conductivity region; Collector electrode in contact with the collector region SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A third semiconductor region of a second conductivity type in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region; A gate electrode provided through the gate insulating layer inside the gate trench that passes through the third semiconductor region and reaches the first semiconductor region; An emitter region of a first conductivity type provided in a part of the third semiconductor region in contact with the gate trench; A low resistance region of a second conductivity type provided in a part of the third semiconductor region adjacent to the emitter region, A fourth semiconductor region of a first conductivity type having a resistivity lower than that of the first semiconductor region, provided in a part of the surface layer of the first semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, An upper trench disposed away from the fourth semiconductor region between the third semiconductor region and the fourth semiconductor region, A lower trench narrower than the upper trench, installed from a bottom of the upper trench to a deeper position, A trench buried insulating film buried in the upper trench and the lower trench; An emitter side conductive region of a floating potential buried in the vicinity of the third semiconductor region in the trench filling insulating film in the upper trench; An emitter electrode in contact with the emitter region and the low resistance region; Collector electrode in contact with the collector region SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A third semiconductor region of a second conductivity type in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region; A gate electrode provided through the gate insulating layer inside the gate trench that passes through the third semiconductor region and reaches the first semiconductor region; An emitter region of a first conductivity type provided in a part of the third semiconductor region in contact with the gate trench; A low resistance region of a second conductivity type provided in a part of the third semiconductor region adjacent to the emitter region, A fourth semiconductor region of a first conductivity type having a resistivity lower than that of the first semiconductor region, provided in a part of the surface layer of the first semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, Trenches disposed away from the fourth semiconductor region between the third semiconductor region and the fourth semiconductor region, A trench buried insulating film embedded in the trench; An emitter side conductive region of a floating potential buried in the vicinity of the third semiconductor region in an upper half of the trench filling insulating film; An emitter electrode in contact with the emitter region and the low resistance region; Collector electrode in contact with the collector region SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A second conductive region of a first conductivity type provided in a part of the surface layer of the first semiconductor region, the resistivity of which is lower than that of the first semiconductor region; A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region; A gate electrode provided on a surface of a portion of the third semiconductor region via a gate insulating film; An emitter region of a first conductivity type provided in a portion of the third semiconductor region, A low resistance region of a second conductivity type provided in a part of the third semiconductor region, and provided below the emitter region; A high conductivity region of a second conductivity type provided in a part of the third semiconductor region adjacent to the emitter region, A fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, away from the second semiconductor region and the third semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, An upper trench disposed away from the third semiconductor region between the second semiconductor region and between the third semiconductor region and the fourth semiconductor region; A lower trench narrower than the upper trench, installed from a bottom of the upper trench to a deeper position, A trench buried insulating film buried in the upper trench and the lower trench; A collector-side conductive region buried in the vicinity of the fourth semiconductor region in the trench filling insulating film in the upper trench; An emitter electrode in contact with the emitter region and the high conductivity region; A collector electrode in contact with the collector region and electrically connected to the collector side conductive region. SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A second conductive region of a first conductivity type provided in a part of the surface layer of the first semiconductor region, the resistivity of which is lower than that of the first semiconductor region; A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region; A gate electrode provided on a surface of a portion of the third semiconductor region via a gate insulating film; An emitter region of a first conductivity type provided in a portion of the third semiconductor region, A low resistance region of a second conductivity type provided in a part of the third semiconductor region, and provided below the emitter region; A high conductivity region of a second conductivity type provided in a part of the third semiconductor region adjacent to the emitter region, A fourth conductive region of a first conductivity type having a lower resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, away from the second semiconductor region and the third semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, Trenches disposed away from the third semiconductor region between the second semiconductor region and the third semiconductor region and the fourth semiconductor region; A trench buried insulating film embedded in the trench; A collector-side conductive region buried in the vicinity of the fourth semiconductor region in an upper half of the trench filling insulating film; An emitter electrode in contact with the emitter region and the high conductivity region; A collector electrode in contact with the collector region and electrically connected to the collector side conductive region. SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A second conductive region of a first conductivity type provided in a part of the surface layer of the first semiconductor region, the resistivity of which is lower than that of the first semiconductor region; A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region; A gate electrode provided on a surface of a portion of the third semiconductor region via a gate insulating film; An emitter region of a first conductivity type provided in a portion of the third semiconductor region, A low resistance region of a second conductivity type provided in a part of the third semiconductor region, and provided below the emitter region; A high conductivity region of a second conductivity type provided in a part of the third semiconductor region adjacent to the emitter region, A fourth conductive region of a first conductivity type having a lower resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, away from the second semiconductor region and the third semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, Trenches disposed away from the third semiconductor region and the fourth semiconductor region between the second semiconductor region and the third semiconductor region and the fourth semiconductor region; A trench buried insulating film embedded in the trench; An emitter electrode in contact with the emitter region and the high conductivity region; Collector electrode in contact with the collector region SOI trench horizontal IGBT comprising a. The method according to any one of claims 1, 2, 5, 6, 9, 10 and 11, The gate insulating film, the gate electrode, the third semiconductor region, the low resistance region, the emitter region, and the high conductivity region are provided in plural on one side with respect to the trench filling insulating film, and are adjacent to each other. The trench region and the high conductivity region are electrically connected to each other by the emitter electrode. The method according to any one of claims 3, 4, 7, and 8, The gate trench, the gate insulating film, the gate electrode, the third semiconductor region, the low resistance region, and the emitter region are provided in plural on one side with respect to the trench filling insulating film, and the emitter region adjacent to each other. And the low resistance region is electrically connected to each other by the emitter electrode. The SOI trench according to any one of claims 1 to 13, wherein the semiconductor layer between the insulating layer and the first semiconductor region on the support substrate includes a gettering effect on metal contamination. Horizontal IGBTs. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A second conductive region of a first conductivity type provided in a part of the surface layer of the first semiconductor region, the resistivity of which is lower than that of the first semiconductor region; A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region; An emitter region of a first conductivity type provided in a portion of the third semiconductor region, A gate electrode provided through a gate insulating film on a surface of the third semiconductor region between the second semiconductor region and the emitter region; A fourth conductive region of a first conductivity type having a lower resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, away from the second semiconductor region and the third semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, A trench provided between the second semiconductor region and the third semiconductor region and the fourth semiconductor region; A trench buried insulating film embedded in the trench; An emitter side conductive region having a floating potential buried in a vicinity of the pn junction between the third semiconductor region and the first semiconductor region in the trench buried insulating film in the trench; A collector-side conductive region buried near an interface between the fourth semiconductor region and the first semiconductor region in the trench buried insulating film in the trench; An emitter electrode in contact with the emitter region, A collector electrode in contact with the collector region and electrically connected to the collector side conductive region. SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A third semiconductor region of a second conductivity type in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region; A gate electrode provided through the gate insulating layer inside the gate trench that passes through the third semiconductor region and reaches the first semiconductor region; An emitter region of a first conductivity type provided in a part of the third semiconductor region in contact with the gate trench; A fourth semiconductor region of a first conductivity type having a resistivity lower than that of the first semiconductor region, provided in a part of the surface layer of the first semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, A trench provided between the third semiconductor region and the fourth semiconductor region; A trench buried insulating film embedded in the trench; An emitter side conductive region having a floating potential buried in a vicinity of the pn junction between the third semiconductor region and the first semiconductor region in the trench buried insulating film in the trench; A collector-side conductive region buried near an interface between the fourth semiconductor region and the first semiconductor region in the trench buried insulating film in the trench; An emitter electrode in contact with the emitter region, A collector electrode in contact with the collector region and electrically connected to the collector side conductive region. SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A second conductive region of a first conductivity type provided in a part of the surface layer of the first semiconductor region, the resistivity of which is lower than that of the first semiconductor region; A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region; An emitter region of a first conductivity type provided in a portion of the third semiconductor region, A gate electrode provided through a gate insulating film on a surface of the third semiconductor region between the second semiconductor region and the emitter region; A fourth conductive region of a first conductivity type having a lower resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, away from the second semiconductor region and the third semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, Trenches disposed away from the fourth semiconductor region between the second semiconductor region and the third semiconductor region and the fourth semiconductor region; A trench buried insulating film embedded in the trench; An emitter side conductive region having a floating potential buried in a vicinity of the pn junction between the third semiconductor region and the first semiconductor region in the trench buried insulating film in the trench; An emitter electrode in contact with the emitter region, Collector electrode in contact with the collector region SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A third semiconductor region of a second conductivity type in contact with the first semiconductor region and provided in a part of the surface layer of the first semiconductor region; A gate electrode provided through the gate insulating layer inside the gate trench that passes through the third semiconductor region and reaches the first semiconductor region; An emitter region of a first conductivity type provided in a part of the third semiconductor region in contact with the gate trench; A fourth semiconductor region of a first conductivity type having a resistivity lower than that of the first semiconductor region, provided in a part of the surface layer of the first semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, Trenches disposed away from the fourth semiconductor region between the third semiconductor region and the fourth semiconductor region, A trench buried insulating film embedded in the trench; An emitter side conductive region having a floating potential buried in a vicinity of the pn junction between the third semiconductor region and the first semiconductor region in the trench buried insulating film in the trench; A collector-side conductive region buried near an interface between the fourth semiconductor region and the first semiconductor region in the trench buried insulating film in the trench; An emitter electrode in contact with the emitter region, Collector electrode in contact with the collector region SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A second conductive region of a first conductivity type provided in a part of the surface layer of the first semiconductor region, the resistivity of which is lower than that of the first semiconductor region; A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region; An emitter region of a first conductivity type provided in a portion of the third semiconductor region, A gate electrode provided through a gate insulating film on a surface of the third semiconductor region between the second semiconductor region and the emitter region; A fourth semiconductor region of a first conductivity type having a lower resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, away from the second semiconductor region and the third semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, Trenches disposed away from the third semiconductor region between the second semiconductor region and the third semiconductor region and the fourth semiconductor region; A trench buried insulating film embedded in the trench; A collector-side conductive region buried near an interface between the fourth semiconductor region and the first semiconductor region in the trench buried insulating film in the trench; An emitter electrode in contact with the emitter region, A collector electrode in contact with the collector region and electrically connected to the collector side conductive region. SOI trench horizontal IGBT comprising a. A first conductive semiconductor layer provided on the support substrate via an insulating layer; A first semiconductor region of a first conductivity type provided on the semiconductor layer and having a higher resistivity than the semiconductor layer; A second conductive region of a first conductivity type provided in a part of the surface layer of the first semiconductor region, the resistivity of which is lower than that of the first semiconductor region; A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region; An emitter region of a first conductivity type provided in a portion of the third semiconductor region, A gate electrode provided through a gate insulating film on a surface of the third semiconductor region between the second semiconductor region and the emitter region; A fourth conductive region of a first conductivity type having a lower resistivity than the first semiconductor region, provided in a part of the surface layer of the first semiconductor region, away from the second semiconductor region and the third semiconductor region; A collector region of a second conductivity type provided in a part of the fourth semiconductor region, Trenches disposed away from the third semiconductor region and the fourth semiconductor region between the second semiconductor region and the third semiconductor region and the fourth semiconductor region; A trench buried insulating film embedded in the trench; An emitter electrode in contact with the emitter region, Collector electrode in contact with the collector region SOI trench horizontal IGBT comprising a.

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