JP4232645B2 - Trench lateral semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a power obtained by integrating a lateral MOS (metal-oxide-semiconductor) transistor and a bipolar transistor having a trench structure with low on-resistance per unit area and high short-circuit resistance. The present invention relates to a trench lateral semiconductor device constituting a device and a manufacturing method thereof.

  A device in which a MOS transistor and a bipolar transistor are integrated has an advantage that the configuration of a drive circuit is simple like a MOS element, and the on-resistance is low due to conductivity modulation of a withstand voltage portion like a bipolar transistor. Therefore, it is regarded as important in fields that require high breakdown voltage and high power level. Device structures include a planar gate type having a gate electrode on a substrate surface via a gate insulating film and a trench gate type having a gate electrode embedded in a trench formed in the substrate. The trench gate type device structure has excellent features such as high channel density and difficulty in operating a parasitic thyristor (see Non-Patent Document 1, for example).

The configuration of a conventional IGBT (insulated gate bipolar transistor) will be described below. Note that in this specification and the accompanying drawings, a layer or region with n or p is a sign that electrons or holes are carriers. Further, ⁺ or ⁻ attached to n or p represents a relatively high impurity concentration or a relatively low impurity concentration, respectively.

FIG. 53 is a cross-sectional view showing a configuration of a conventional trench gate IGBT. As shown in FIG. 53, a p ⁺ semiconductor layer 112 having high conductivity is provided on the collector electrode 110, and an n semiconductor layer 111 is further stacked thereon. On the n semiconductor layer 111, an n ⁻ semiconductor layer 103 having a lower conductivity than the n semiconductor layer 111 is stacked. A p semiconductor region 104 is provided on the surface layer of the n ⁻ semiconductor layer 103.

The trench penetrates the p semiconductor region 104 from the semiconductor surface and reaches the n ⁻ semiconductor layer 103. A gate electrode 108 is embedded in the trench through an insulating film 109. Further, an n ⁺ semiconductor region 106 is provided on the surface layer of the p semiconductor region 104 in contact with the insulating film 109 in the trench, and a p ⁺ semiconductor region 105 is provided in contact with the n ⁺ semiconductor region 106. ing. Emitter electrode 107 is in contact with both p ⁺ semiconductor region 105 and n ⁺ semiconductor region 106 and is insulated from gate electrode 108 by insulating film 109.

The IGBT having the configuration shown in FIG. 53 includes a p ⁺ semiconductor layer 112, an n region composed of n semiconductor layer 111 and n ⁻ semiconductor layer 103, and a p region composed of p semiconductor region 104 and p ⁺ semiconductor region 105. A parasitic thyristor is configured by the PNP bipolar transistor and the NPN bipolar transistor formed of the n ⁺ semiconductor region 106, the p semiconductor region 104, and the n ⁻ semiconductor layer 103. This parasitic thyristor does not operate unless the junction composed of the p semiconductor region 104, the p ⁺ semiconductor region 105, and the n ⁺ semiconductor region 106 is turned on.

The on-voltage value is proportional to the resistance of the p ⁺ semiconductor region 105. By adopting the trench gate structure, the p ⁺ semiconductor region 105 can be made thin and large in area, so that the resistance of the p ⁺ semiconductor region 105 is reduced and the current path from the p semiconductor region 104 to the emitter electrode 107 is reduced. The resistance becomes lower. As a result, the latch-up withstand capability of the trench gate IGBT is about four times as high as that of an IGBT having a gate having a normal DMOS (double diffused MOS) structure (see, for example, Non-Patent Document 1).

  In general, in a planar structure power IC in which a logic control circuit and a high voltage circuit are integrated, a drift region carrying a high voltage is provided in parallel to the wafer surface. In order to reduce the influence of noise on the low-voltage logic circuit caused by the high-voltage circuit, it is necessary to isolate the low-voltage logic circuit from the high-voltage circuit portion. The isolation structure includes a junction isolation structure and a dielectric isolation structure. Since the dielectric isolation structure using the bonded SOI wafer can make the chip smaller, it is widely used in driver ICs for flat display panels such as plasma display panels, switching ICs for automobiles, etc. (See Patent Document 2).

FIG. 54 is a diagram showing a cross-sectional configuration of an IGBT manufactured using a conventional thick film SOI substrate. As shown in FIG. 54, the SOI substrate has a structure in which an n ⁻ semiconductor layer 203 having a high resistivity serving as an active layer is laminated on a support substrate 201 with an insulating layer 202 interposed therebetween. A p semiconductor region 204 is provided in part of the surface layer of the n ⁻ semiconductor layer 203. A part of the surface layer of the p semiconductor region 204 is provided with an n ⁺ semiconductor region 206 and a first p ⁺ semiconductor region 205 in contact therewith. A portion of the first p ⁺ semiconductor region 205 occupies a portion below the n ⁺ semiconductor region 206.

Further, an n semiconductor region 211 is provided apart from the p semiconductor region 204 in a part of the surface layer of the n ⁻ semiconductor layer 203. The resistivity of the n semiconductor region 211 is lower than that of the n ⁻ semiconductor layer 203. A part of the surface layer of the n semiconductor region 211 is provided with a second p ⁺ semiconductor region 212. The emitter electrode 207 is in contact with both the first p ⁺ semiconductor region 205 and the n ⁺ semiconductor region 206. A gate electrode 208 is provided on the surface of the p semiconductor region 204 sandwiched between the n ⁻ semiconductor layer 203 and the n ⁺ semiconductor region 206 with an insulating film 209 interposed therebetween. In addition, the collector electrode 210 is in contact with the second p ⁺ semiconductor region 212.

In the IGBT having the configuration shown in FIG. 54, the second p ⁺ semiconductor region 212, the n region formed of the n semiconductor region 211 and the n ⁻ semiconductor layer 203, the p semiconductor region 204, and the first p ⁺ semiconductor region 205 are formed. A parasitic thyristor is configured by the PNP bipolar transistor configured by the p region and the NPN bipolar transistor configured by the n ⁺ semiconductor region 206, the p semiconductor region 204, and the n ⁻ semiconductor layer 203. In order to avoid latch-up by this parasitic thyristor, an upper limit is set for the on-current. In order to increase the upper limit value of the on-current, the NPN bipolar transistor may be prevented from operating. For this purpose, it is necessary to keep the resistance of the current path from the channel end side to the first p ⁺ semiconductor region 205 passing under the n ⁺ semiconductor region 206 low.

In this regard, a method for reducing the resistance of the current path by ion implantation has been reported (for example, see Non-Patent Document 3). In addition, a trench emitter electrode capable of removing uncertainty by mask matching when forming the first p ⁺ semiconductor region 205, minimizing the length of the current path, and self-aligning with the gate electrode is provided. A forming method has been reported (for example, see Non-Patent Document 4). Further, when the element is in the on state, a part of carriers flowing from the second p ⁺ semiconductor region 212 into the n ⁻ semiconductor layer 203 reaches the first p ⁺ semiconductor region 205 without passing through the current path. Structures have been reported (for example, see Non-Patent Document 5 and Non-Patent Document 6).

In the IGBT having the configuration shown in FIG. 54, the electric field is concentrated at the interface between the n ⁻ semiconductor layer 203 and the p semiconductor region 204 near the wafer surface and between the n ⁻ semiconductor layer 203 and the n semiconductor region 211 near the wafer surface. To do. In order to alleviate the concentration of the electric field, the emitter electrode 207 and the collector electrode 210 may be extended as field plates so as to overlap the interface via the insulating film 209. As a structure when a higher breakdown voltage is required or when there is a wiring such as a power supply line on the drift region, a capacitively coupled field plate is provided on the upper surface of the drift region on the wafer surface or inside the drift region. What is provided is known (for example, see Patent Document 1, Patent Document 2, and Patent Document 3).

  In HV (High Voltage) IC, as a countermeasure against the possibility of breakdown when a high-voltage metal wiring crosses a PN junction, an electrically floating conductive region serving as a field plate is provided on the HVIC wiring. It has been reported to be used (for example, see Non-Patent Document 7). In addition, a semiconductor including a lateral MOS element in which a pitch of a unit device is reduced by arranging a drift region that bears a breakdown voltage in a direction perpendicular to the wafer surface and having a drain region in contact with the drift region inside the substrate. The apparatus is known (for example, refer to Patent Document 4).

  Further, in manufacturing an SOI wafer, the balance between atomic vacancies and interstitial atoms formed in the wafer drawing process by the Czochralski method is destroyed by implanting boron at a high dose, for example. When the first annealing process is performed at a temperature of 900 ° C. or less, OSF (oxidation-introduced stacking fault) and BMD (bulk fine defects) are often generated. However, when the first annealing process is performed at a high temperature (1050 ° C.), There is a report that the occurrence of these defects can be suppressed (for example, see Non-Patent Document 8).

Further, when a bonded SOI wafer is manufactured, the surface of the bonded wafer becomes a mirror quality surface necessary for bonding the wafers. As a mechanism for bonding silicon wafers, it is known that the wafers are integrated with each other through H ₂ O adsorbed by “Si—OH—” on the surface of each other. When heated to 200 ° C. or higher, water molecules become tetramer clusters. When heated to 700 ° C. or higher, the water cluster evaporates and the wafers are bonded to each other through “Si—O—Si”. Furthermore, there is a report that when heated at 1100 ° C., the insulating layer (buried oxide film layer) of the SOI wafer is reflowed to further increase the bonding strength between the wafers (see, for example, Non-Patent Document 9). .

  Bonding between wafers is possible if there is a hydroxyl group (“—OH”) on the surface of the mirror-quality wafer before the bonding. A wafer used for forming a device (hereinafter referred to as a device wafer) is immersed in deionized water immediately after being treated with high-concentration hydrofluoric acid, thereby providing a high surface density “−F” attached to the surface of the device wafer. "Can be replaced with" -OH ". A method has been reported in which a device wafer is bonded to a wafer on which an insulating layer is formed (hereinafter referred to as a handle wafer) after this replacement (for example, see Non-Patent Document 10).

Further, by providing an n ⁺ semiconductor layer having a resistivity lower than that of the n ⁻ semiconductor layer between the insulating layer of the SOI substrate and the n ⁻ semiconductor layer serving as the active layer, a gettering effect against metal contamination can be obtained. . There is a report that the reliability of the gate is improved by this gettering effect (see, for example, Non-Patent Document 11).

Japanese Examined Patent Publication No. 63-50871 JP 5-190693 A Japanese Patent Laid-Open No. 2003-8006 Japanese Patent No. 3395603 B. Jayant Baliga, “Power Semiconductor Devices”, (USA), PWS Publishing Company, 1996, p. 496-498 H. Sumida, two others, “A High-Voltage Lateral IGBT with Significantly Improved IC” On-State Characteristics on SOI for an Advanced PDP Scan Driver IC "(USA), 2002 I Triple E International SOI Conference, 10/02 (2002 IEEE International SOI Conference, 10/02), 2002, p.64. -65 DR Disney, 1 other, "SOI LIGBT Devices with a Dual P-Well Implant for Improved Latching Characteristics", (USA) 5th International Symposium on Power Semiconductor Devices and ICs (1993), p. 254-258 Philip KT Mok, 2 others, “A Self-Aligned Trenched Cathode Lateral Insulated Gate Bipolar Transistor with High Latch-Up Resistance), (USA), I TRANSACTION ON ELECTRON DEVICES, December 1995, Vol. 42, No. 12, p. 2236-2239 H. Sumida, 2 others, “The Modified Structure of the Lateral IGBT on the SOI Wafer for Improving” the Dynamic Latch-up Characteristics), (USA), IEEE TRANSACTION ON ELECTRON DEVICES, 1995, Vol. 42, No. 2, p. 367-370 Jun Cai, 4 others, “A New Lateral Trench-Gate Conductivity Modulated Power Transistor” (USA), I Triple E Transaction On Electron Devices (IEEE TRANSACTION ON ELECTRON DEVICES), August 1999, Vol. 46, No. 8, p. 1788-1793 Philip KT Mok, 1 other, "Interconnect Induced Breakdown in HVIC's" (USA), Proceedings of the Symposium on High Voltage and Smart Power Ics (Proceedings of the Symposium on High Voltage and Smart Power Ics), 1989, p. 206-217 Jeong-Min Kim, 4 others, “Behavior of Thermally Induced Defects in Heavily Boron-Doped Silicon Crystals”, Japanese Journal Of Journal of Applied Physics, March 2001, Vol. 40, Part 1, Part 3A, p. 1370-1374 B. Stengl, two others, "A Model for the Silicon Wafer Bonding Process", Japanese Journal of Applied Physics, 1989 October, 28, 10, p. 1735-1741 Hiroaki Himi, 3 others, “Silicon Wafer Direct Bonding without Hydrophilic Native Oxides”, Japanese Journal of Applied Physics, 1994 January, Vol. 33, Part 1, No. 1A, p. 6-10 P. Papakonstaninou, 6 other authors, CE Hunt, 3 others, “The Electrochemical Society Proceedings Series” (PV99-35) In Semiconductor Wafer Bonding: Science, Technology and Applications V / 1999, (USA), Pennington, Nj, 2000

  However, in a device in which the drift region is provided along the surface direction of the wafer of the device, the drift region must be extended in the surface direction of the wafer in order to increase the breakdown voltage. For this reason, there is a problem that high integration is hindered. Further, when the drift region is extended in the wafer surface direction, the device pitch is increased, and the on-resistance per unit area is increased. On the other hand, in a device in which the drift region is arranged in a direction perpendicular to the wafer surface, the insulation region between the drift region and the drain region becomes thick as the breakdown voltage increases. Therefore, there is a problem that the device pitch increases and the on-resistance per unit area increases.

  The present invention is a device in which a lateral MOS transistor and a bipolar transistor are fused in order to eliminate the above-mentioned problems caused by the prior art, and can be driven with a high withstand voltage, a large current, and has a high latch-up withstand capability. An object of the present invention is to provide a device having a low on-resistance per unit area and a method for manufacturing the device.

  In order to solve the above-described problems and achieve the object, a trench lateral semiconductor device according to the invention of claim 1 is provided with a lower semiconductor layer of a first conductivity type provided on a support substrate via an insulating layer, and A second conductivity type upper semiconductor layer is provided on the lower semiconductor layer, and a second conductivity type first semiconductor region having a higher resistivity than the upper semiconductor layer is provided on the upper semiconductor layer. An SOI substrate; a second semiconductor region of a first conductivity type provided in a surface layer of the first semiconductor region; and the first semiconductor penetrating from the surface of the SOI substrate through the second semiconductor region. One or two or more trench gate portions having an insulating film on the inner surface of the trench reaching the region and having a first electrode inside the insulating film, and the trench gate in the surface layer of the second semiconductor region Second conductivity selectively provided in contact with the portion A third semiconductor region, a fourth semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor region, the third semiconductor region, and the fourth semiconductor region A second electrode that is in contact with and insulated from the first electrode; and the first semiconductor that penetrates the second semiconductor region from the surface of the SOI substrate at a position away from the trench gate portion. A third electrode provided in a trench reaching the region, and between the third electrode and the trench gate portion, straddling the first semiconductor region and the second semiconductor region, and the third electrode A conductive region provided up to a position shallower than the first electrode, a first insulating film that insulates the conductive region from surrounding semiconductors, and the third electrode for the conductive region and the first semiconductor region. A second insulating film for insulating from, A fifth semiconductor region of a first conductivity type connected to the lower end of the third electrode and the lower semiconductor layer of the SOI substrate, and the fifth semiconductor region are surrounded by the upper semiconductor layer of the SOI substrate. And a sixth semiconductor region of the second conductivity type to be connected.

  According to a second aspect of the present invention, a trench lateral semiconductor device includes a first conductive type semiconductor layer provided on a support substrate via an insulating layer, and a first layer having a higher resistivity than the semiconductor layer. An SOI substrate provided with a conductive first semiconductor region, a second conductive type second semiconductor region provided in a surface layer of the first semiconductor region, and the second surface from the surface of the SOI substrate. One or more trench gate portions having an insulating film on the inner surface of the trench that penetrates the semiconductor region and reaches the first semiconductor region, and has a first electrode inside the insulating film; A first semiconductor layer of a first conductivity type selectively provided in contact with the trench gate portion and a surface layer of the second semiconductor region; A fourth semiconductor region of the second conductivity type and the third semiconductor region; A second electrode that is in contact with the region and the fourth semiconductor region and is insulated from the first electrode, and at a position away from the trench gate portion, from the surface of the SOI substrate to the second semiconductor region. A third electrode provided in a trench that reaches the first semiconductor region through the first semiconductor region, and the first semiconductor region and the second electrode between the third electrode and the trench gate portion. A conductive region that extends over a semiconductor region and is shallower than the third electrode; a first insulating film that insulates the conductive region from surrounding semiconductor; and A second insulating film that is insulated from the conductive region and the first semiconductor region, and a fifth semiconductor region of a first conductivity type that is connected to a lower end of the third electrode and the semiconductor layer of the SOI substrate. It is characterized by having .

  According to a third aspect of the present invention, there is provided a lateral trench type semiconductor device in which a lower semiconductor layer of a first conductivity type is provided on a support substrate via an insulating layer, and an upper semiconductor of a second conductivity type is provided on the lower semiconductor layer. An SOI substrate in which a second conductivity type first semiconductor region having a higher resistivity than the upper semiconductor layer is provided on the upper semiconductor layer, and a surface layer of the first semiconductor region One or more planar gates having a first conductivity type second semiconductor region selectively provided on the first semiconductor electrode and a first electrode with an insulating film on a part of the surface of the second semiconductor region And a third semiconductor region of a second conductivity type selectively provided on the surface layer of the second semiconductor region in alignment with the end of the first electrode, and the second semiconductor region Provided on the surface layer in alignment with a terminal end of the first electrode, and the third semiconductor A fourth semiconductor region of a first conductivity type extending below the region; a second electrode in contact with the third semiconductor region and the fourth semiconductor region and insulated from the first electrode; A third electrode provided in a trench reaching the first semiconductor region from the surface of the SOI substrate through the second semiconductor region at a position away from the planar gate portion; A conductive region which extends between the first semiconductor region and the second semiconductor region and is shallower than the third electrode between the first electrode and the planar gate portion; A first insulating film that insulates the region from the surrounding semiconductor; a second insulating film that insulates the third electrode from the conductive region and the first semiconductor region; a lower end of the third electrode; The lower half of the SOI substrate A first conductive type fifth semiconductor region connected to the body layer, and a second conductive type sixth semiconductor region surrounding the fifth semiconductor region and connected to the upper semiconductor layer of the SOI substrate, It is characterized by providing.

  According to a fourth aspect of the present invention, there is provided a trench lateral type semiconductor device in which a first conductivity type semiconductor layer is provided on a support substrate via an insulating layer, and the first resistivity having a higher resistivity than the semiconductor layer is provided on the semiconductor layer. An SOI substrate provided with a first semiconductor region of conductivity type, a second semiconductor region of second conductivity type selectively provided on a surface layer of the first semiconductor region, and the second semiconductor region One or two or more planar gate portions having a first electrode through an insulating film on a part of the surface of the semiconductor device, and a surface layer of the second semiconductor region aligned with a terminal end of the first electrode A third semiconductor region of a first conductivity type selectively provided; and a surface layer of the second semiconductor region, provided in alignment with a terminal end of the first electrode, and the third semiconductor region A fourth semiconductor region of the second conductivity type extending downward, and the third semiconductor region and A second electrode that is in contact with the fourth semiconductor region and insulated from the first electrode, and penetrates the second semiconductor region from the surface of the SOI substrate at a position away from the planar gate portion. And a third electrode provided in a trench reaching the first semiconductor region, and the first semiconductor region and the second semiconductor region between the third electrode and the planar gate portion. A conductive region that extends to a position shallower than the third electrode, a first insulating film that insulates the conductive region from surrounding semiconductors, and a third electrode that connects the conductive region to the conductive region. And a second insulating film that insulates from the first semiconductor region, and a fifth semiconductor region of a first conductivity type that is connected to a lower end of the third electrode and the semiconductor layer of the SOI substrate. It is characterized by.

  According to the first to fourth aspects of the present invention, the portion for holding the withstand voltage is provided in the depth direction of the semiconductor device, and the third electrode has a trench reaching the first semiconductor region from the surface of the SOI substrate. By passing through the surface of the semiconductor device, the area occupied by the unit cell can be made smaller than that of a conventional lateral IGBT. Therefore, the on-resistance per unit area can be reduced. Here, one third electrode may be provided for each cell, or a plurality of cells may share one third electrode.

  According to the first to fourth aspects of the invention, the composite region has a configuration in which the conductive region is sandwiched between the first insulating film and the second insulating film on the side surface of the trench having the third electrode. Therefore, this conductive region is electrically floated to form a field plate. When the device is reverse-biased by this field plate, an electric field parallel to the substrate surface coming from the third electrode is shielded, so that it is formed at the interface between the first semiconductor region and the second semiconductor region. A high electric field parallel to the substrate surface generated on the side wall side of the trench having the third electrode of the PN junction (hereinafter referred to as PN junction A) can be relaxed. Therefore, the PN junction A is protected and the breakdown voltage is improved.

  Without the field plate, the high electric field parallel to the substrate surface is not relaxed, so that the PN junction A is likely to be destroyed when the device is reverse biased. Note that in the case where a lower withstand voltage may be used than when the composite region is provided, a thick insulating film may be provided instead of the composite region.

  The first semiconductor region, the second insulating film, and the third electrode constitute a MOS capacitor, and the first semiconductor region and the second insulation are increased as the voltage applied to the third electrode is increased. An accumulation layer is formed at the interface with the film, which causes electric field concentration in the drift region and lowers the breakdown voltage. On the other hand, according to the first to fourth aspects of the present invention, since the electrically floating conductive region is provided, the formation of the storage layer at a position where the storage layer is easily formed can be suppressed. Therefore, the breakdown voltage is improved.

  Here, the reason why the conductive region serving as the field plate is floated is as follows. That is, when the conductive region is grounded, the conductive region has the same potential as the second electrode that is set to the ground potential. Then, when the device is in the ON state, a relatively large capacitance formed by sandwiching the first insulating film between the conductive region and the first semiconductor region becomes a parasitic capacitance connected in parallel to the element. This will reduce the effective switching current capability of the device. In order to avoid this, it is desirable that the conductive region is floating.

  According to the invention of claim 1 or 3, the lower semiconductor layer of the SOI substrate serves as a getter layer against metal contamination, so that a gettering effect can be obtained. Similarly, according to the invention of claim 2 or 4, since the semiconductor layer of the SOI substrate becomes a getter layer against metal contamination, a gettering effect can be obtained. According to the first or second aspect of the invention, since the first electrode has a trench gate structure, the third semiconductor region, the second semiconductor region, and the first semiconductor serving as a trigger for the parasitic thyristor are provided. Since the transistor composed of the region becomes difficult to operate, the latch-up resistance and the short-circuit resistance of the device can be increased.

  According to a fifth aspect of the present invention, there is provided the trench lateral type semiconductor device according to any one of the first to fourth aspects, wherein the contact area between the third electrode and the fifth semiconductor region is the inside. When the trench formed in the SOI substrate for providing the third electrode is filled with an insulating film, the central portion of the insulating film is removed by self-aligned etching, and the second insulating film is formed. It is determined by the area of the semiconductor region exposed at the bottom of the trench.

  A trench lateral semiconductor device according to a sixth aspect of the invention is the invention according to any one of the first to fourth aspects, wherein the conductive region provided between the third electrode and the gate portion is It is characterized by being made of polysilicon.

  According to a seventh aspect of the present invention, there is provided a method for manufacturing a trench lateral semiconductor device, wherein the trench reaching the first semiconductor region from the surface of the SOI substrate is formed when the trench lateral semiconductor device according to the first aspect is manufactured. Then, an insulating film is deposited in the trench, a conductive film is deposited inside the insulating film, and the conductive film and the insulating film are placed until the upper end of the conductive film is lower than the surface of the SOI substrate. The first insulating film and the conductive region are formed by performing self-aligned etching by anisotropic etching.

  According to an eighth aspect of the present invention, there is provided a manufacturing method of a trench lateral semiconductor device according to the seventh aspect of the present invention, wherein after the first insulating film and the conductive region are formed, the same conductive region is formed inside the conductive region. An insulating film covering the conductive region is formed by self-aligned etching, and a deeper trench is formed at the bottom of the trench using the insulating film as a mask.

According to a ninth aspect of the present invention, there is provided a method for manufacturing a trench lateral semiconductor device, wherein the trench reaching the first semiconductor region from the surface of the SOI substrate is formed when the trench lateral semiconductor device according to the second aspect is manufactured. Then, an insulating film is deposited in the trench, a conductive film is deposited inside the insulating film, and the conductive film and the insulating film are placed until the upper end of the conductive film is lower than the surface of the SOI substrate. The first insulating film and the conductive region are formed by performing self-aligned etching by anisotropic etching.

  According to a tenth aspect of the present invention, there is provided a method for manufacturing a lateral trench type semiconductor device according to the ninth aspect, wherein the first insulating film and the conductive region are formed, and then the same conductive region is formed inside the conductive region. An insulating film covering the conductive region is formed by self-aligned etching, and a deeper trench is formed at the bottom of the trench using the insulating film as a mask.

According to a method for manufacturing a trench lateral semiconductor device according to an invention of claim 11, in manufacturing the trench lateral semiconductor device according to claim 3, a trench reaching the first semiconductor region from the surface of the SOI substrate is formed. Then, an insulating film is deposited in the trench, a conductive film is deposited inside the insulating film, and the conductive film and the insulating film are placed until the upper end of the conductive film is lower than the surface of the SOI substrate. The first insulating film and the conductive region are formed by performing self-aligned etching by anisotropic etching.

  According to a twelfth aspect of the present invention, there is provided a method for manufacturing a trench lateral semiconductor device according to the eleventh aspect of the present invention, wherein the first insulating film and the conductive region are formed, and then the same conductive region is formed inside the conductive region. An insulating film covering the conductive region is formed by self-aligned etching, and a deeper trench is formed at the bottom of the trench using the insulating film as a mask.

According to a thirteenth aspect of the present invention, there is provided a method of manufacturing a trench lateral semiconductor device, wherein the trench reaching the first semiconductor region from the surface of the SOI substrate is formed when the trench lateral semiconductor device according to the fourth aspect is manufactured. Then, an insulating film is deposited in the trench, a conductive film is deposited inside the insulating film, and the conductive film and the insulating film are placed until the upper end of the conductive film is lower than the surface of the SOI substrate. The first insulating film and the conductive region are formed by performing self-aligned etching by anisotropic etching.

  According to a fourteenth aspect of the present invention, there is provided a method for manufacturing a trench lateral semiconductor device according to the thirteenth aspect of the present invention, wherein after the first insulating film and the conductive region are formed, the same conductive region is formed inside the conductive region. An insulating film covering the conductive region is formed by self-aligned etching, and a deeper trench is formed at the bottom of the trench using the insulating film as a mask.

  According to a fifteenth aspect of the present invention, there is provided a method for manufacturing a lateral trench semiconductor device, comprising: implanting a second conductivity type impurity into a second conductivity type semiconductor wafer when manufacturing the trench lateral semiconductor device according to the first aspect; Then, after forming the second conductivity type upper semiconductor layer having a lower resistivity than the semiconductor wafer on the surface layer of the semiconductor wafer, an impurity of the first conductivity type is implanted into the upper semiconductor layer, Forming the first conductive type lower semiconductor layer on the surface layer of the semiconductor layer to fabricate the first wafer, and fabricating the second wafer by forming an insulating layer on the surface of the support wafer And a step of bonding the surface of the lower semiconductor layer of the first wafer to the surface of the insulating layer of the second wafer to integrate the first wafer and the second wafer. And the first Characterized in that it comprises a step of polishing the rear surface of the E c, the.

  According to a method of manufacturing a trench lateral semiconductor device according to a sixteenth aspect of the present invention, in manufacturing the trench lateral semiconductor device according to the second aspect, an impurity of the first conductivity type is implanted into the semiconductor wafer of the first conductivity type. Forming a first conductivity type semiconductor layer having a resistivity lower than that of the semiconductor wafer on the surface layer of the semiconductor wafer, and forming an insulating layer on the surface of the support wafer; Forming a second wafer by forming, and bonding the surface of the semiconductor layer of the first wafer to the surface of the insulating layer of the second wafer, and the first wafer and the first wafer And a step of polishing the back surface of the first wafer.

  A method for manufacturing a trench lateral semiconductor device according to a seventeenth aspect of the present invention is directed to implanting a second conductivity type impurity into a second conductivity type semiconductor wafer when manufacturing the trench lateral semiconductor device according to the third aspect. Then, after forming the second conductivity type upper semiconductor layer having a lower resistivity than the semiconductor wafer on the surface layer of the semiconductor wafer, an impurity of the first conductivity type is implanted into the upper semiconductor layer, Forming the first conductive type lower semiconductor layer on the surface layer of the semiconductor layer to fabricate the first wafer, and fabricating the second wafer by forming an insulating layer on the surface of the support wafer And a step of bonding the surface of the lower semiconductor layer of the first wafer to the surface of the insulating layer of the second wafer to integrate the first wafer and the second wafer. And the first Characterized in that it comprises a step of polishing the rear surface of the E c, the.

  According to a method of manufacturing a trench lateral semiconductor device according to an invention of claim 18, in manufacturing the trench lateral semiconductor device according to claim 4, an impurity of the first conductivity type is implanted into the semiconductor wafer of the first conductivity type. Forming a first conductivity type semiconductor layer having a resistivity lower than that of the semiconductor wafer on the surface layer of the semiconductor wafer, and forming an insulating layer on the surface of the support wafer; Forming a second wafer by forming, and bonding the surface of the semiconductor layer of the first wafer to the surface of the insulating layer of the second wafer, and the first wafer and the first wafer And a step of polishing the back surface of the first wafer.

  According to the present invention, a trench lateral semiconductor device having a breakdown voltage and a drive current equal to or higher than those of a lateral semiconductor device using a conventional SOI substrate, a high latch-up resistance, and a low on-resistance per unit area is obtained. There is an effect that is. Further, by using the SOI substrate, it is possible to easily integrate with the CMOS device.

Exemplary embodiments of a trench lateral semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the following description and the accompanying drawings, a semiconductor having n or p is a meaning that an electron or a hole is a carrier, respectively. Further, ⁺ or ⁻ attached to n or p represents a relatively higher impurity concentration or a relatively lower impurity concentration than those not attached thereto. Note that the same reference numerals are given to the same components in all the attached drawings, and redundant description is omitted.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the semiconductor device of the first embodiment. As shown in FIG. 1, the n-channel IGBT is manufactured using an SOI substrate. The SOI substrate has an insulating layer 2 made of an oxide film, a collector layer (lower semiconductor layer) 12 made of p ⁺ semiconductor, a buffer layer (upper semiconductor layer) 11 made of n semiconductor, n ⁻ on a support substrate 1. A drift region (first semiconductor region) 3 made of a semiconductor is stacked in this order. The resistivity of the drift region 3 is higher than the resistivity of the buffer layer 11. The collector layer 12 has a gettering effect against metal contamination, and also serves as a getter layer.

A base region (second semiconductor region) 4 made of a p semiconductor is provided in the surface layer of the drift region 3. An emitter region (third semiconductor region) 6 made of n ⁺ semiconductor is provided in a part of the surface layer of the base region 4. A low resistance region (fourth semiconductor region) 5 made of a p ⁺ semiconductor having higher conductivity than the base region 4 is provided in part of the surface layer of the base region 4 in contact with the emitter region 6.

  The surface layer of the SOI substrate is provided with one or more trench gate portions. The trench gate portion includes a first trench 17 that reaches the drift region 3 through the emitter region 6 and the base region 4 from the surface of the SOI substrate, and a gate electrode through a gate insulating film made of a part of the insulating film 9. (First electrode) 8 is embedded. The emitter region 6 is provided in contact with the trench gate portion. The emitter electrode (second electrode) 7 has a barrier metal 16 around it and is in contact with the emitter region 6 and the low resistance region 5. The emitter electrode 7 is insulated from the gate electrode 8 by an interlayer insulating film made of a part of the insulating film 9.

  A second trench 18 that extends from the surface of the SOI substrate to the shallow position of the drift region 3 through the base region 4 is provided at a position away from the trench gate portion. A first insulating film 20 made of an oxide film or the like is provided on the side surface of the second trench 18. Inside the first insulating film 20, the conductive region 15 made of polysilicon or other conductive material is provided to a position deeper than the PN junction surface formed by the base region 4 and the drift region 3. . The conductive region 15 is insulated from other semiconductor parts, electrodes, and the like by the first insulating film 20 and a second insulating film 14 described later, and is in an electrically floating state and functions as a field plate. .

  From the bottom surface of the second trench 18 excluding the conductive region 15, a third trench 19 that reaches a deeper position of the drift region 3 is formed. Inside the second trench 18 and the third trench 19, a second insulating film 14 made of an oxide film or the like is provided from the surface of the SOI substrate to the bottom surface of the third trench 19. In the second trench 18 and the third trench 19, the inner region of the second insulating film 14 is a collector electrode (third electrode) 10. The collector electrode 10 includes a first plug 10a and a second plug 10b, and a barrier metal 13 that covers the plugs 10a and 10b.

In the drift region 3, a buffer region (sixth semiconductor region) 11 a made of n semiconductor is provided below the third trench 19. The buffer area 11 a is connected to the buffer layer 11. In the drift region 3, a collector region (fifth semiconductor region) 12 a made of p ⁺ semiconductor is provided below the third trench 19. The collector region 12 a is in contact with the barrier metal 13 of the collector electrode 10 and is connected to the collector layer 12 through the buffer region 11 a.

  The buffer layer 11 and the buffer region 11 a have a higher impurity concentration than the drift region 3 and isolate the collector layer 12 and the collector region 12 a from the drift region 3. This device is a punch-through type IGBT having the buffer layer 11 and the buffer region 11a. The collector layer 12 and the collector region 12a serve as a carrier injection layer for conductivity modulation. The buffer layer 11 and the buffer region 11a control the amount of conductivity-modulated carriers injected from the collector layer 12 and the collector region 12a into the drift region 3, thereby creating a trade-off relationship between the on-resistance of the element and the turn-off loss. If the bottom of the third trench 19 reaches the buffer layer 11, the buffer region 11 a can be omitted. However, in order to increase manufacturing reliability, the buffer region 11 a is provided. Is desirable.

  In the above configuration, when the gate voltage applied to the gate electrode 8 exceeds the threshold voltage, a channel is formed along the gate insulating film at the interface between the side wall of the first trench 17 and the base region 4. Further, the device having the configuration shown in FIG. 1 includes a p region composed of the collector layer 12 and the collector region 12a, an n region composed of the buffer layer 11, the buffer region 11a and the drift region 3, and a p region of the base region 4. A parasitic thyristor is configured by the PNP bipolar transistor that is formed, the n region of the emitter region 6, the p region composed of the low resistance region 5 and the base region 4, and the n region of the drift region 3. The

  However, since the gate structure of the device is a trench gate structure, the NPN bipolar transistor that triggers the parasitic thyristor is difficult to operate. Therefore, the latch-up tolerance of the device is increased and the short-circuit tolerance is also increased. In addition, since the field plate potential of the conductive region 15 is floating, the capacitance between the emitter and the collector is reduced and the switching speed is improved as compared with the case where the field plate potential is fixed to the emitter potential.

Next, a description will be given of the results of investigation by the inventor of the characteristics of the device having the above-described configuration. In the following description, in the device having the configuration shown in FIG. The length from the PN junction at the interface between the drift region 3 and the base region 4 to the bottom surface of the third trench 19 (the contact surface between the barrier metal 13 and the collector region 12a) is defined as a drift region length L _D. The length from the PN junction at the interface between the drift region 3 and the base region 4 to the lower end of the conductive region 15 is defined as a field plate length _LFP . The thickness of the first insulating film 20 between the drift region 3 and the conductive region 15 is D1. The length between the conductive region 15 and the first plug 10a of the collector electrode 10 is D2.

Figure 2 is a characteristic diagram showing the results of examining the relationship between the off-state breakdown voltage (breakdown voltage) and L _D. Here, D1 is 1 μm, D2 is 0.8 μm, and L _FP is ½ of L _D. Also, the first insulating film 20 and SiO _2. As apparent from FIG 2, when it is a 5 × 10 ¹⁴ cm ^-3 when the doping concentration of the drift region is 1 × 10 ¹⁴ cm ^-3, the breakdown voltage increases as the length L _D of the drift region increases I understand that.

Specifically, when the doping concentration of the drift region is 1 × 10 ¹⁴ cm ⁻³ , the breakdown voltages are 172 V, 184 V and 205 V when L _D is 8 μm, 12 μm and 17 μm, respectively. When the doping concentration is 5 × 10 ¹⁴ cm ⁻³ , the breakdown voltages are 168V, 177V and 197V, respectively. If the doping concentration of the drift region is about 1 × 10 ¹⁴ cm ⁻³ and L _D is 12 μm or more, it can be seen that a breakdown voltage of 180 V or more can be secured. In general, since the withstand voltage in the off state required for the scan driver IC is 165 V, all the six devices plotted in FIG. 2 have no problem in practical use.

FIG. 3 is a simulation result showing the relationship between the off breakdown voltage (breakdown voltage) and _LFP . In this simulation, L _D was 12 μm, D 1 was 0.3 μm or 1 μm, and D 2 was 0.8 μm. In addition, the first insulating film 20 and SiO _2. As can be seen from FIG. 3, the breakdown voltage becomes maximum when L _FP is approximately half of L _D.

Specifically, when D1 is 1 μm and the doping concentration of the drift region is 1 × 10 ¹⁴ cm ⁻³ , the breakdown voltage is when L _FP is 2 μm, 5 μm, 6 μm, 7 μm, 8 μm, and 10 μm, respectively. Are 160V, 172V, 180V, 190V, 163V and 148V. When D1 is 0.3 μm and the doping concentration of the drift region is 3 × 10 ¹⁴ cm ⁻³ , the break occurs when the length L _FP of the field plate is 2 μm, 4 μm, 6 μm, 8 μm, and 10 μm. The down voltages are 93V, 97V, 108V, 95V and 90V.

FIG. 4 shows the results of examining the relationship between the off breakdown voltage (breakdown voltage) and the doping concentration in the drift region with and without the field plate. Here, L _D was 12 μm, and L _FP was 6 μm. In the case where there is a field plate, the conductive region 15 to be the field plate is made of n-type polysilicon. When there was no field plate, the region to be the conductive region 15 was also an oxide film.

As can be seen from FIG. 4, with the field plate, the breakdown voltage is higher by about 50 V than when there is no field plate. Further, under the conditions exemplified with reference to FIG. 4, it can be understood that a withstand voltage of 180 V or more can be secured if the doping concentration of the drift region is about 1 × 10 ¹⁴ cm ⁻³ .

FIG. 5 is a characteristic diagram showing the relationship between the off breakdown voltage (breakdown voltage) and D1. However, D2 was 0.8 μm, L _D was 12 μm, and L _FP was 6 μm. The first insulating film 20 and the second insulating film 14 are made of SiO ₂ . The field plate made of the conductive region 15 is electrostatically coupled to the drift region 3 by sandwiching the first insulating film 20 between the drift region 3 and is related to the breakdown voltage of the element. As is clear from FIG. 5, it can be seen that a higher breakdown voltage can be secured when the first insulating film 20 is thicker and the capacitance between the conductive region 15 and the drift region 3 is smaller. Specifically, when D1 is 0.3 μm, 0.5 μm, 0.8 μm, and 1 μm, the breakdown voltages are 109 V, 133 V, 164 V, and 180 V, respectively.

  When the conductive region 15 is made of n-type doped polysilicon, a storage layer is formed at the interface between the field plate and the surrounding insulating film. In the present embodiment, since the field plate potential is floating, extra electrons from the surface equilibrium state are not supplied from the external electrode to the field plate. Therefore, a space charge layer that balances with the surface non-equilibrium state layer is formed, and a dipole layer is formed. This increases the effective dielectric layer thickness between the drift region 3 and the conductive region 15.

  On the other hand, when the conductive region 15 is made of p-type doped polysilicon, a depletion layer is formed at the interface of the field plate. Holes excluded from the depletion layer at the interface of the conductive region 15 are deposited in the vicinity of the depletion layer and form a charge and a dipole of the depletion layer. Thereby, the effective dielectric layer thickness between the drift region 3 and the conductive region 15 becomes larger than the physical thickness of the first insulating film 20.

FIG. 6 is a characteristic diagram showing the relationship between the off breakdown voltage (breakdown voltage) and D2. However, D1 was 1 μm, L _D was 12 μm, and L _FP was 6 μm. The first insulating film 20 and the second insulating film 14 are made of SiO ₂ . FIG. 6 shows that the withstand voltage becomes 190 V or more when D2 is 1 μm or more. Specifically, when D2 is 0.8 μm, 1 μm, 1.3 μm, 1.5 μm, and 2 μm, the breakdown voltages are 180V, 191V, 198V, 203V, and 208V, respectively.

  Further, for the device having the configuration shown in FIG. 1, the current driving capability of the unit cell device is comparable to that of the conventional lateral device due to the optimization of the device structure and the manufacturing process. FIG. 7 shows the dimensions of each part when the collector electrode 10 is arranged for each trench gate portion and the design rule is 1 μm in the device having the configuration shown in FIG. In this case, as indicated by “0”, “0.5”, “2”, “4.5”, “7”, and “8” above the device of FIG. 7, the center of the gate electrode 8 is set as the starting point. “0”, the distance from the starting point to the interface between the gate insulating film which is a part of the insulating film 9 and the gate electrode 8 is 0.5 μm, the distance to the center of the emitter electrode 7 is 2 μm, The distance to the interface between the drift region 3 and the base region 4 and the first insulating film 20 is 4.5 μm, and the distance to the interface between the second plug 10 b of the collector electrode 10 and the barrier metal 13 is 7 μm. The distance to the center of the collector electrode 10 (first plug 10a and second plug 10b) is 8 μm. That is, the cell pitch is 8 μm.

On the other hand, in the conventional device shown in FIG. 54, the cell pitch is 25 μm. Therefore, in the device having the dimensions shown in FIG. 7, since the cell pitch is smaller than half of the conventional device, the on-resistance per unit area is about 250 mΩ · mm ² which is half of the on-resistance (500 mΩ · mm ² ) of the conventional device. Become.

On the other hand, in the device having the configuration shown in FIG. 1, when a plurality of gates share one collector electrode 10, it is necessary to consider the resistance of the collector layer 12. FIG. 8 is an explanatory diagram for deriving the effective resistance of the collector layer 12. As shown in FIG. 8, it is assumed that a current having a uniform current density j flows from the collector layer 12 to the buffer layer 11. The resistance R _{p +} of the collector layer 12 in this case is expressed by the following equation (1).

However, in the formula (1), W is a gate width in a direction perpendicular to the drawing of FIG. L is the distance from the center of the collector electrode 10 to the center of the gate electrode 8 farthest from the collector electrode 10 among the plurality of gate electrodes 8 sharing the collector electrode 10. ρ _sh is the sheet resistance of region 12. x is a distance from the center of the collector electrode 10. Therefore, the following equation (2) is obtained.

However, in Formula (2), A is a surface area of a device. N is the number of repetitions of the distance ΔL shown in FIG. L _p is a distance from the center of the collector electrode 10 to the center of the gate electrode 8 closest to the collector electrode 10 among the plurality of gate electrodes 8 sharing the collector electrode 10. ΔL is the distance between the centers of adjacent gate electrodes 8 sharing the collector electrode 10. The contact resistance R _c between the collector layer 12 and the barrier metal 13 is expressed by the following equation (3). The equation (4) is obtained from the equation (3).

In the equations (3) and (4), ρ _c is a specific contact resistance or a contact resistance per unit area, and W _c is a width of the collector electrode shown in FIG. When the barrier layer of the barrier metal 13 is Ti / TiN, its R _on A is expressed by the following equation (5).

However, in the formula (5), T _Ti and T _TiN are the thicknesses of Ti and TiN, respectively. ρ _Ti and ρ _TiN are the resistivity of Ti and TiN, respectively. If the metal of the first plug 10a and the second plug 10b is W (tungsten), its R _on A is expressed by the following equation (6).

However, in the equation (6), ρ _W is the resistivity of tungsten. D _c is the distance from the upper end of the second plug 10b to the lower end of the first plug 10a (see FIG. 1). W _C is the width of the collector electrode shown in FIG. Thus, the parasitic R _on A increases as N increases.

On the other hand, when the half cell pitch has two or more channels, the device channel can be formed at a distance shorter than the cell pitch when the number of channels shown in FIG. 7 is 1, so that the current can be increased. Therefore, the on-resistance R _on A of the device itself is reduced. Assume that the on-resistance R _on A or specific resistance R _on A per unit area is inversely proportional to the number of channels of the device. When the cell pitch of the device shown in FIG. 7 is L _p and its R _on A is (R _on A) ′, the following equation (7) is obtained.

However, in the equation (7), (2N + 1) is the number of channels included in the half cell pitch [(NΔL + L _p )] of the device. The total R _on A obtained by summing up the above is expressed by the following equation (8).

The value of N that minimizes (R _on A) _T is obtained by the following equation (9).

  Therefore, the following equation (10) is obtained.

However, in the equation (10), (2N + 1) _opt is the optimum number of channels included in the half cell pitch of the device. From the above, the optimum _cell pitch L _{cell opt} is expressed by the following equation (11). N _opt is the optimum number of repetitions of the distance ΔL shown in FIG.

Plotting the relationship between the above equation (8) and N gives the result shown in FIG. However, (R _on A) ′ = 150 mΩ · mm ² , L _p = 8 μm, ΔL = 5 μm, collector layer 12 thickness T (see FIG. 8) = 1 μm, ρ _Ti = 65 μΩ · cm, T _Ti = 0.1 μm T _TiN = 0.2 μm and D _c = 13 μm. Further, the combined width of the first plug 10a and the barrier metal 13 of the collector electrode 10 is W _c (see FIG. 1), and W _c = 1.4 μm.

Further, the resistivity ρ _Si of _silicon is 5 × 10 ⁻⁴ Ω · cm, ρ _c = 1 × 10 ⁻⁶ Ω · cm ² , ρ _TiN = 160 μΩ · cm, and ρ _W = 5.7 μΩ · cm. For ρ _Si , SM Sze's “Physics of Semiconductor Devices” (2nd ed., Wiley, 1982. P. 32.). ρ _c is from DK Schroder's “Semiconductor Material and Device Characterization” (2nd ed., Wiley, 1998. P. 141.). ρ _TiN = 160 μΩ · cm is according to “ULSI Technology” (McGraw Hill, 1996. P. 384.) by CY Chang et al. ρ _W is from SA Campbell's “The Science and Engineering of Microelectronic Fabrication” (Oxford University Press, 1996. P. 411).

In such a condition, N _opt is 5. Therefore, from the above equation (11), the optimum cell pitch is 136 μm, and it is expected that the influence on the element reliability is small from the etching of the trench for providing the collector electrode 10.

Next, a manufacturing process of the device having the configuration shown in FIG. 1 will be described with reference to FIGS. First, as shown in FIG. 10, a screen oxide film 31 is formed on the surface of a wafer made of an n ⁻ semiconductor to become the drift region 3, and n-type impurity As (arsenic) or antimony (Sb) is ion-implanted. Then, as shown in FIG. 11, a buffer layer 11 is formed on the wafer surface. Next, as shown in FIG. 12, B (boron), which is a p-type impurity, is ion-implanted into the wafer surface to form the collector layer 12 on the surface of the buffer layer 11 as shown in FIG. Then, as shown in FIG. 14, the screen oxide film 31 is removed. Thus far, a device wafer, which is the first wafer, is completed.

  On the other hand, as shown in FIG. 15, a support substrate 1 is prepared. Then, as shown in FIG. 16, an insulating layer 2 such as an oxide film is formed on the surface of the support substrate 1 to obtain a handle wafer as a second wafer. Next, as shown in FIG. 17, the surface of the insulating layer 2 of the handle wafer and the surface of the collector layer 12 of the device wafer are bonded together. At that time, the device wafer and the handle wafer are combined and integrated through a natural oxide film on the surface of the device wafer. Then, as shown in FIG. 18, the drift region 3 of the integrated SOI wafer is polished to a predetermined thickness. Thus, the SOI wafer is completed.

  Next, as shown in FIG. 19, a screen oxide film 32 is formed on the surface of the SOI wafer, that is, the surface of the drift region 3, and boron is ion-implanted into the surface of the drift region 3, and as shown in FIG. Region 4 is formed. Subsequently, As is ion-implanted into the wafer surface to form an emitter region 6 as shown in FIG. Thereafter, the screen oxide film 32 is removed. Next, as shown in FIG. 22, an oxide film 33 is deposited on the wafer surface, and a photoresist 34 is applied thereon. Then, an etching pattern is created in the photoresist 34 by photolithography, and the oxide film 33 is etched to form a trench etching mask.

  After the photoresist 34 is ashed, anisotropic etching is performed to form the first trench 17 as shown in FIG. The trench etching damage is removed by sacrificial oxidation or the like, a sacrificial oxide film (not shown) is removed, and then an insulating film 9 to be a gate insulating film is formed. Next, as shown in FIG. 24, doped polysilicon is deposited on the wafer surface, and this doped polysilicon is etched back until it becomes lower than the surface of the SOI wafer to form the gate electrode 8. Thereafter, the remaining polysilicon surface is oxidized.

  Next, as shown in FIG. 25, a photoresist 35 is applied to the wafer surface, and an ion implantation pattern is created by photolithography. Then, boron is ion-implanted to form the low resistance region 5 as shown in FIG. After the photoresist 35 is ashed, an oxide film 36 is deposited on the wafer surface, and a photoresist 37 is applied thereon. Then, an etching pattern is created in the photoresist 37 by photolithography, and the oxide film 36 is etched to form a trench etching mask.

  After the photoresist 37 is ashed, anisotropic etching is performed to form the second trench 18 as shown in FIG. Then, damage due to trench etching is removed by sacrificial oxidation or the like, and a sacrificial oxide film (not shown) is removed. Next, as shown in FIG. 28, an insulating film and a polysilicon film are deposited on the entire surface of the wafer, and the polysilicon film and the insulating film are sequentially etched by self-aligned etching to form the first trench on the side wall of the second trench 18. The conductive region 15 made of the insulating film 20 and the polysilicon film is left.

  Next, as shown in FIG. 29, an oxide film is deposited on the entire surface of the wafer, and this oxide film is etched by self-aligned etching to form an oxide film 21 that covers the upper and inner sides of the conductive region 15. Then, anisotropic etching is performed using the oxide film 21 as a mask for trench etching to form a third trench 19 at the bottom of the second trench 18. After etching damage is removed by sacrificial oxidation or the like, P (phosphorus) or As is ion-implanted to form a buffer region 11a at the bottom of the third trench 19 as shown in FIG.

  Thereafter, an insulating film is deposited, and this insulating film is etched by self-aligned etching to leave the second insulating film 14 inside the oxide film 21 in the second trench 18 and on the side wall of the third trench 19. . Then, boron is ion-implanted using the second insulating film 14 as a mask to form a collector region 12a at the bottom of the third trench 19 as shown in FIG. Subsequently, after forming a Ti / TiN layer to be the barrier metal 13, W (tungsten) is deposited, and the second trench 18 and the third trench 19 are filled with tungsten. Then, the Ti / TiN layer and tungsten are etched back, and the Ti / TiN layer and tungsten on the wafer surface are removed, so that the inside of the second insulating film 14 in the second trench 18 and the third trench 19 is removed. Is filled with the barrier metal 13 and the first plug 10a.

  Next, as shown in FIG. 32, an oxide film is deposited on the entire surface of the wafer, and the upper surface is flattened by CMP (Chemical Mechanical Polishing). A contact hole is opened in the planarized oxide film. Next, as shown in FIG. 33, the metal is sputtered to form the barrier metals 13 and 16, the emitter electrode 7 and the second plug 10b of the collector electrode 10, and the front end process. Complete.

Embodiment 2. FIG.
FIG. 34 is a cross-sectional view showing the semiconductor device of the second embodiment. As shown in FIG. 34, the second embodiment is a p-channel IGBT complementary to the first embodiment shown in FIG. 1, except that the semiconductor conductivity type is different from that of the first embodiment. 1 is the same configuration. Therefore, the same components as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The manufacturing method is the same as that in the first embodiment except that the conductivity type of the impurity at the time of ion implantation is different from that in the first embodiment, and thus the description thereof is omitted.

Embodiment 3 FIG.
FIG. 35 is a cross-sectional view showing the semiconductor device of the third embodiment. As shown in FIG. 35, the third embodiment is an n-channel MOS transistor. The difference from the first embodiment shown in FIG. 1 is that buffer layer 11 and buffer region 11a are not provided, and that the conductivity type of collector layer 12 and collector region 12a is the same n type as drift region 3. is there. Since other configurations are the same as those of the first embodiment, the same configurations as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. As for the manufacturing method, the ion implantation step for forming the buffer layer 11 and the buffer region 11a is omitted, and the conductivity type of the impurity to be ion-implanted to form the collector layer 12 and the collector region 12a is implemented. Since it is the same as that of Embodiment 1 except that it is different from Embodiment 1, description thereof is omitted.

Embodiment 4 FIG.
FIG. 36 is a cross-sectional view showing the semiconductor device of the fourth embodiment. As shown in FIG. 36, the fourth embodiment is a p-channel MOS transistor complementary to the third embodiment shown in FIG. 35, except that the semiconductor conductivity type is different from that of the third embodiment. The configuration is the same as in the third mode. Therefore, in the fourth embodiment, the buffer layer 11 and the buffer region 11a are not provided. The conductivity type of the collector layer 12 and the collector region 12 a is the same p type as that of the drift region 3. The same components as those in the first and third embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. As for the manufacturing method, the ion implantation step for forming the buffer layer 11 and the buffer region 11a is omitted, and the conductivity type of the impurity at the time of ion implantation is different from that of the first embodiment (the collector layer 12 and the collector region 12a). Except for the above, the description is omitted.

Embodiment 5 FIG.
FIG. 37 is a cross-sectional view showing the semiconductor device of the fifth embodiment. As shown in FIG. 37, in the fifth embodiment, the gate structure is changed to the DMOS structure in place of the trench gate structure in the first embodiment shown in FIG. Therefore, the first trench 17 is not provided in the fifth embodiment. The structure for drawing the collector electrode 10 to the substrate surface is the same as that of the first embodiment. In addition, an SOI substrate in which a field plate made of a conductive region 15 is provided and a p ⁺ collector layer 12, an n buffer layer 11 and an n ⁻ drift region 3 are stacked in this order on the insulating layer 2 is used. The n-channel IGBT is manufactured as in the first embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, detailed description thereof is omitted, and only differences from the first embodiment will be described below.

The DMOS type gate structure is configured as follows. A base region (second semiconductor region) 4 a made of p semiconductor is selectively provided in the surface layer of the drift region 3. The PN junction surface formed from the base region 4 a and the drift region 3 is shallower than the lower end of the conductive region 15. In the surface layer of the drift region 3, the region other than the base region 4 a is a surface drift region 3 a made of an n semiconductor having higher conductivity than the drift region 3. An emitter region (third semiconductor region) 6a made of n ⁺ semiconductor is provided in a part of the surface layer of the base region 4a. In the base region 4a, below the emitter region 6a, a low resistance region (fourth semiconductor region) 5a made of ap ⁺ semiconductor having higher conductivity than the base region 4a is provided.

The gate electrode (first electrode) 8a is provided on the surface of the base region 4a exposed between the surface drift region 3a and the emitter region 6a via a gate insulating film 9a. The emitter electrode (second electrode) 7a has a barrier metal 16a around the emitter electrode 7a, is in contact with the emitter region 6a, and has a low resistance region made of p ⁺ semiconductor having higher conductivity than the base region 4a. It is electrically connected to the low resistance region 5a via 5b. The emitter electrode 7a is insulated from the gate electrode 8a by the interlayer insulating film 9b.

  In the above configuration, when the gate voltage applied to the gate electrode 8a exceeds the threshold voltage, a channel is formed at the interface between the base region 4a and the gate insulating film 9a between the emitter region 6a and the surface drift region 3a. The In the device having the configuration shown in FIG. 37, a p region composed of the collector layer 12 and the collector region 12a, an n region composed of the buffer layer 11, the buffer region 11a and the drift region 3, a base region 4a and a low resistance region 5a, PNP bipolar transistor composed of a p region composed of 5b, an n region of emitter region 6a, a p region composed of low resistance regions 5a, 5b and base region 4a, and an n region of drift region 3 A parasitic thyristor is configured by the NPN bipolar transistor.

  However, since the holes flowing in from the channel side pass through the low resistance regions 5a and 5b having low resistivity, the voltage drop here becomes lower than the turn-on voltage of the PN junction, so that the NPN bipolar that triggers the parasitic thyristor The transistor becomes difficult to operate. Therefore, the latch-up tolerance of the device is increased and the short-circuit tolerance is also increased. Further, since the doping concentration of the surface drift region 3a is higher than that of the drift region 3, the JFET (junction FET) effect is hardly generated, and the on-resistance and the cell pitch can be reduced.

  Next, a manufacturing process of the device having the configuration shown in FIG. 37 will be described with reference to FIGS. First, an SOI wafer is manufactured in the same manner as in Embodiment Mode 1 (see FIGS. 10 to 18). Next, as shown in FIG. 38, a screen oxide film 32 is formed on the surface of the SOI wafer, that is, the surface of the drift region 3, and phosphorus is ion-implanted into the surface of the drift region 3. As shown in FIG. Drift region 3a is formed.

  After removing the screen oxide film 32, an oxide film, for example, which becomes the gate insulating film 9a is grown on the wafer surface. A doped polysilicon to be the gate electrode 8a is deposited on the oxide film, and an oxide film 41 is further deposited thereon. Then, the oxide film 41, the doped polysilicon, the oxide film that becomes the gate insulating film 9a, and the like are etched by photolithography and RIE (reactive ion etching) to form a gate stack structure. Subsequently, after performing polyshadow oxidation, oblique ion implantation of boron is performed on the gate stack structure.

  Then, thermal diffusion is performed to form a base region 4a as shown in FIG. Next, As ions are implanted by self-alignment (self-alignment technique) to form an emitter region 6a as shown in FIG. Next, an oxide film is deposited on the entire surface of the wafer, and a spacer oxide film 42 serving as a sidewall spacer is formed on the side surface of the gate stack structure by self-aligned etching. Thereafter, boron ions are implanted with high energy to form a low resistance region 5a below the emitter region 6a as shown in FIG.

  Next, a photoresist 43 is applied to the wafer surface, and an ion implantation pattern is created in the photoresist 43 by photolithography. Then, boron is ion-implanted to form the low resistance region 5b as shown in FIG. After the photoresist 43 is ashed, an oxide film 36 is deposited on the wafer surface, and a photoresist 37 is applied thereon. Then, an etching pattern is created in the photoresist 37 by photolithography, and the oxide film 36 is etched to form a trench etching mask.

  After ashing the photoresist 37, anisotropic etching is performed to form the second trench 18 as shown in FIG. Then, damage due to trench etching is removed by sacrificial oxidation or the like, and a sacrificial oxide film (not shown) is removed. Next, as shown in FIG. 45, an insulating film and a polysilicon film are deposited on the entire surface of the wafer, and the polysilicon film and the insulating film are sequentially etched by self-aligned etching to form the first trench 18 on the side wall of the second trench 18. The conductive region 15 made of the insulating film 20 and the polysilicon film is left.

  Next, as shown in FIG. 46, an oxide film is deposited on the entire surface of the wafer, and this oxide film is etched by self-aligned etching to form an oxide film 21 covering the upper and inner sides of the conductive region 15. Then, anisotropic etching is performed using the oxide film 21 as a mask for trench etching to form a third trench 19 at the bottom of the second trench 18. After removing the etching damage by sacrificial oxidation or the like, P (phosphorus) or As is ion-implanted to form a buffer region 11a at the bottom of the third trench 19 as shown in FIG.

  Thereafter, an insulating film is deposited, and this insulating film is etched by self-aligned etching to leave the second insulating film 14 inside the oxide film 21 in the second trench 18 and on the side wall of the third trench 19. . Then, boron is ion-implanted using the second insulating film 14 as a mask to form a collector region 12a at the bottom of the third trench 19 as shown in FIG. Subsequently, after forming a Ti / TiN layer to be the barrier metal 13, W (tungsten) is deposited, and the second trench 18 and the third trench 19 are filled with tungsten. Then, the Ti / TiN layer and tungsten are etched back, and the Ti / TiN layer and tungsten on the wafer surface are removed, so that the inside of the second insulating film 14 in the second trench 18 and the third trench 19 is removed. Is filled with the barrier metal 13 and the first plug 10a.

  Next, as shown in FIG. 49, an oxide film is deposited on the entire surface of the wafer, and the upper surface is planarized by CMP (Chemical Mechanical Polishing). A contact hole is opened in the planarized oxide film. Next, as shown in FIG. 37, the metal is sputtered to form the barrier metals 13 and 16a, the emitter electrode 7a, and the second plug 10b of the collector electrode 10 to form the front end process. Complete.

Embodiment 6 FIG.
FIG. 50 is a cross-sectional view showing the semiconductor device of the sixth embodiment. As shown in FIG. 50, the sixth embodiment is a p-channel IGBT complementary to the fifth embodiment shown in FIG. 37, except that the semiconductor conductivity type is different from that of the fifth embodiment. 5 is the same configuration. Therefore, the same components as those in the fifth embodiment and the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The manufacturing method is the same as that of the fifth embodiment except that the conductivity type of the impurity at the time of ion implantation is different from that of the fifth embodiment, and thus the description thereof is omitted.

Embodiment 7 FIG.
FIG. 51 is a cross-sectional view showing the semiconductor device of the seventh embodiment. As shown in FIG. 51, the seventh embodiment is an n-channel MOS transistor. The difference from the fifth embodiment shown in FIG. 37 is that buffer layer 11 and buffer region 11a are not provided, and that the conductivity type of collector layer 12 and collector region 12a is the same n type as drift region 3. is there. Since other configurations are the same as those of the fifth embodiment, the same reference numerals are given to the same configurations as those of the fifth embodiment and the first embodiment, and detailed description thereof is omitted. As for the manufacturing method, the ion implantation step for forming the buffer layer 11 and the buffer region 11a is omitted, and the conductivity type of the impurity to be ion-implanted to form the collector layer 12 and the collector region 12a is implemented. Since it is the same as that of Embodiment 5 except that it differs from Embodiment 5, description thereof is omitted.

Embodiment 8 FIG.
FIG. 52 is a sectional view showing a semiconductor device according to the eighth embodiment. As shown in FIG. 52, the eighth embodiment is a p-channel MOS transistor complementary to the seventh embodiment shown in FIG. 51, except that the semiconductor conductivity type is different from that of the seventh embodiment. The configuration is the same as in Form 7. Therefore, in the eighth embodiment, the buffer layer 11 and the buffer region 11a are not provided. The conductivity type of the collector layer 12 and the collector region 12 a is the same p type as that of the drift region 3. Configurations similar to those in the seventh embodiment, the fifth embodiment, and the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. As for the manufacturing method, in the manufacturing method described in the fifth embodiment, the ion implantation step for forming the buffer layer 11 and the buffer region 11a is omitted, and the conductivity type of the impurity at the time of ion implantation is the embodiment. Since it is the same as that of Embodiment 5 except that it is different from 5 (except for the collector layer 12 and the collector region 12a), the description thereof is omitted.

  As described above, the trench lateral semiconductor device according to the present invention is useful for a high breakdown voltage switching element that requires a high latch-up resistance, and in particular, is used for an output stage such as a driver IC of a flat panel display or an in-vehicle IC. Suitable for withstand voltage switching elements.

FIG. 3 is a cross-sectional view showing the configuration of the first embodiment. FIG. 2 is a characteristic diagram illustrating a relationship between an off breakdown voltage and a drift region length of the device having the configuration illustrated in FIG. 1. It is a characteristic view which shows the simulation result of the off pressure | voltage resistance with respect to the length of the field plate of the device of the structure shown in FIG. It is a characteristic view which shows the relationship between the off breakdown voltage of the device of the structure shown in FIG. 1, and the doping concentration of a drift region. It is a characteristic view which shows the relationship between the off-breakdown pressure | voltage of the device of a structure shown in FIG. 1, and the thickness of a 1st insulating film. It is a characteristic view which shows the relationship between the off-breakdown pressure | voltage of the device of a structure shown in FIG. 1, and the thickness of a 2nd insulating film. It is sectional drawing which shows the dimension of each part at the time of producing the device of the structure shown in FIG. 1 by 1 micrometer technology. It is explanatory drawing for derivation | leading-out the effective resistance of a collector layer in the device of a structure shown in FIG. 2 is a characteristic diagram showing a trade-off relationship between R _on A and the number of repetitions N of the distance ΔL shown in FIG. 1 in the device having the configuration shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of an SOI wafer. It is sectional drawing which shows the state in the middle of manufacture of an SOI wafer. It is sectional drawing which shows the state in the middle of manufacture of an SOI wafer. It is sectional drawing which shows the state in the middle of manufacture of an SOI wafer. It is sectional drawing which shows the state in the middle of manufacture of an SOI wafer. It is sectional drawing which shows the state in the middle of manufacture of an SOI wafer. It is sectional drawing which shows the state in the middle of manufacture of an SOI wafer. It is sectional drawing which shows the state in the middle of manufacture of an SOI wafer. It is sectional drawing which shows an SOI wafer. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of the device of the structure shown in FIG. It is sectional drawing which shows the state which the front end process of the device of the structure shown in FIG. 1 was completed. FIG. 6 is a cross-sectional view illustrating a configuration of a second embodiment. FIG. 6 is a cross-sectional view illustrating a configuration of a third embodiment. FIG. 6 is a cross-sectional view showing a configuration of a fourth embodiment. FIG. 10 is a cross-sectional view illustrating a configuration of a fifth embodiment. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 38 is a cross-sectional view showing a state in the middle of manufacturing the device having the configuration shown in FIG. 37. FIG. 10 is a cross-sectional view showing a configuration of a sixth embodiment. FIG. 10 is a cross-sectional view showing a configuration of a seventh embodiment. FIG. 10 is a cross-sectional view showing a configuration of an eighth embodiment. It is sectional drawing which shows the structure of the conventional trench gate IGBT. It is sectional drawing which shows the structure of the conventional SOI horizontal type IGBT.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support substrate 2 Insulating layer 3 1st semiconductor region (drift region)
4, 4a Second semiconductor region (base region)
5, 5a, 5b Fourth semiconductor region (low resistance region)
6, 6a Third semiconductor region (emitter region)
7, 7a Second electrode (emitter electrode)
8, 8a First electrode (gate electrode)
9, 9a Insulating film 10 Third electrode (collector electrode)
11 Upper semiconductor layer (buffer layer)
11a Sixth semiconductor region (buffer region)
12 Lower semiconductor layer (collector layer)
12a Fifth semiconductor region (collector region)
14 Second insulating film 15 Conductive region 17 First trench 18 Second trench 19 Third trench 20 First insulating film

Claims (18)

A lower semiconductor layer of the first conductivity type is provided on the support substrate via an insulating layer, and an upper semiconductor layer of the second conductivity type is provided on the lower semiconductor layer, and further on the upper semiconductor layer, An SOI substrate provided with a first semiconductor region of a second conductivity type having a higher resistivity than the upper semiconductor layer;
A second semiconductor region of a first conductivity type provided in a surface layer of the first semiconductor region;
1 or 2 having an insulating film on the inner surface of a trench that penetrates the second semiconductor region from the surface of the SOI substrate to the first semiconductor region, and has a first electrode inside the insulating film The above trench gate part,
A third semiconductor region of a second conductivity type selectively provided in contact with the trench gate portion on the surface layer of the second semiconductor region;
A fourth semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor region;
A second electrode in contact with the third semiconductor region and the fourth semiconductor region and insulated from the first electrode;
A third electrode provided in a trench that penetrates the second semiconductor region from the surface of the SOI substrate and reaches the first semiconductor region at a position away from the trench gate portion;
A conductive region provided between the third electrode and the trench gate portion, which extends over the first semiconductor region and the second semiconductor region and is shallower than the third electrode;
A first insulating film that insulates the conductive region from surrounding semiconductors;
A second insulating film that insulates the third electrode from the conductive region and the first semiconductor region;
A fifth semiconductor region of a first conductivity type connected to a lower end of the third electrode and the lower semiconductor layer of the SOI substrate;
A sixth semiconductor region of a second conductivity type surrounding the fifth semiconductor region and connected to the upper semiconductor layer of the SOI substrate;
A trench lateral semiconductor device comprising: An SOI in which a first conductive type semiconductor layer is provided on a supporting substrate via an insulating layer, and a first conductive type first semiconductor region having a higher resistivity than the semiconductor layer is provided on the semiconductor layer. A substrate,
A second semiconductor region of a second conductivity type provided in a surface layer of the first semiconductor region;
1 or 2 having an insulating film on the inner surface of a trench that penetrates the second semiconductor region from the surface of the SOI substrate to the first semiconductor region, and has a first electrode inside the insulating film The above trench gate part,
A third semiconductor region of a first conductivity type selectively provided on the surface layer of the second semiconductor region in contact with the trench gate portion;
A fourth semiconductor region of a second conductivity type selectively provided on a surface layer of the second semiconductor region;
A second electrode in contact with the third semiconductor region and the fourth semiconductor region and insulated from the first electrode;
A third electrode provided in a trench that penetrates the second semiconductor region from the surface of the SOI substrate and reaches the first semiconductor region at a position away from the trench gate portion;
A conductive region provided between the third electrode and the trench gate portion, which extends over the first semiconductor region and the second semiconductor region and is shallower than the third electrode;
A first insulating film that insulates the conductive region from surrounding semiconductors;
A second insulating film that insulates the third electrode from the conductive region and the first semiconductor region;
A fifth semiconductor region of a first conductivity type connected to a lower end of the third electrode and the semiconductor layer of the SOI substrate;
A trench lateral semiconductor device comprising: A lower semiconductor layer of the first conductivity type is provided on the support substrate via an insulating layer, and an upper semiconductor layer of the second conductivity type is provided on the lower semiconductor layer, and further on the upper semiconductor layer, An SOI substrate provided with a first semiconductor region of a second conductivity type having a higher resistivity than the upper semiconductor layer;
A second semiconductor region of a first conductivity type selectively provided on a surface layer of the first semiconductor region;
One or more planar gate portions having a first electrode on a part of the surface of the second semiconductor region with an insulating film interposed therebetween;
A third semiconductor region of a second conductivity type selectively provided on the surface layer of the second semiconductor region in alignment with the terminal end of the first electrode;
A fourth semiconductor region of a first conductivity type provided in a surface layer of the second semiconductor region in alignment with a terminal end of the first electrode and extending below the third semiconductor region;
A second electrode in contact with the third semiconductor region and the fourth semiconductor region and insulated from the first electrode;
A third electrode provided in a trench that penetrates the second semiconductor region from the surface of the SOI substrate and reaches the first semiconductor region at a position away from the planar gate portion;
A conductive region provided between the third electrode and the planar gate portion and extending over the first semiconductor region and the second semiconductor region to a position shallower than the third electrode;
A first insulating film that insulates the conductive region from surrounding semiconductors;
A second insulating film that insulates the third electrode from the conductive region and the first semiconductor region;
A fifth semiconductor region of a first conductivity type connected to a lower end of the third electrode and the lower semiconductor layer of the SOI substrate;
A sixth semiconductor region of a second conductivity type surrounding the fifth semiconductor region and connected to the upper semiconductor layer of the SOI substrate;
A trench lateral semiconductor device comprising: An SOI in which a first conductive type semiconductor layer is provided on a supporting substrate via an insulating layer, and a first conductive type first semiconductor region having a higher resistivity than the semiconductor layer is provided on the semiconductor layer. A substrate,
A second semiconductor region of a second conductivity type selectively provided on a surface layer of the first semiconductor region;
One or more planar gate portions having a first electrode on a part of the surface of the second semiconductor region with an insulating film interposed therebetween;
A third semiconductor region of a first conductivity type selectively provided on the surface layer of the second semiconductor region in alignment with the terminal end of the first electrode;
A fourth semiconductor region of a second conductivity type provided on the surface layer of the second semiconductor region in alignment with the terminal end of the first electrode and extending below the third semiconductor region;
A second electrode in contact with the third semiconductor region and the fourth semiconductor region and insulated from the first electrode;
A third electrode provided in a trench that penetrates the second semiconductor region from the surface of the SOI substrate and reaches the first semiconductor region at a position away from the planar gate portion;
A conductive region provided between the third electrode and the planar gate portion and extending over the first semiconductor region and the second semiconductor region to a position shallower than the third electrode;
A first insulating film that insulates the conductive region from surrounding semiconductors;
A second insulating film that insulates the third electrode from the conductive region and the first semiconductor region;
A fifth semiconductor region of a first conductivity type connected to a lower end of the third electrode and the semiconductor layer of the SOI substrate;
A trench lateral semiconductor device comprising:   The contact area between the third electrode and the fifth semiconductor region is such that a trench formed in the SOI substrate is filled with an insulating film in order to provide the third electrode therein, and a central portion of the insulating film is formed. 5 is determined by the area of the semiconductor region exposed at the bottom of the trench when the second insulating film is formed by removing the film by self-aligned etching. Trench lateral semiconductor device.   The trench lateral semiconductor device according to claim 1, wherein the conductive region provided between the third electrode and the gate portion is made of polysilicon. . In manufacturing the trench lateral semiconductor device according to claim 1,
After forming a trench reaching the first semiconductor region from the surface of the SOI substrate, an insulating film is deposited in the trench, a conductive film is deposited inside the insulating film, and the conductive film and the insulating film are formed. The trench lateral type is characterized in that the first insulating film and the conductive region are formed by performing self-aligned etching by anisotropic etching until the upper end of the conductive film is lower than the surface of the SOI substrate. A method for manufacturing a semiconductor device.   After forming the first insulating film and the conductive region, an insulating film covering the conductive region is formed by self-aligned etching inside the conductive region, and further on the trench bottom using the insulating film as a mask. 8. The method of manufacturing a trench lateral semiconductor device according to claim 7, wherein a deep trench is formed. In manufacturing the trench lateral semiconductor device according to claim 2,
After forming a trench reaching the first semiconductor region from the surface of the SOI substrate, an insulating film is deposited in the trench, a conductive film is deposited inside the insulating film, and the conductive film and the insulating film are formed. The trench lateral type is characterized in that the first insulating film and the conductive region are formed by performing self-aligned etching by anisotropic etching until the upper end of the conductive film is lower than the surface of the SOI substrate. A method for manufacturing a semiconductor device.   After forming the first insulating film and the conductive region, an insulating film covering the conductive region is formed by self-aligned etching inside the conductive region, and further on the trench bottom using the insulating film as a mask. 10. The method of manufacturing a trench lateral semiconductor device according to claim 9, wherein a deep trench is formed. In manufacturing the trench lateral semiconductor device according to claim 3,
After forming a trench reaching the first semiconductor region from the surface of the SOI substrate, an insulating film is deposited in the trench, a conductive film is deposited inside the insulating film, and the conductive film and the insulating film are formed. The trench lateral type is characterized in that the first insulating film and the conductive region are formed by performing self-aligned etching by anisotropic etching until the upper end of the conductive film is lower than the surface of the SOI substrate. A method for manufacturing a semiconductor device.   After forming the first insulating film and the conductive region, an insulating film covering the conductive region is formed by self-aligned etching inside the conductive region, and further on the trench bottom using the insulating film as a mask. 12. The method of manufacturing a trench lateral semiconductor device according to claim 11, wherein a deep trench is formed. In manufacturing the trench lateral semiconductor device according to claim 4,
After forming a trench reaching the first semiconductor region from the surface of the SOI substrate, an insulating film is deposited in the trench, a conductive film is deposited inside the insulating film, and the conductive film and the insulating film are formed. The trench lateral type is characterized in that the first insulating film and the conductive region are formed by performing self-aligned etching by anisotropic etching until the upper end of the conductive film is lower than the surface of the SOI substrate. A method for manufacturing a semiconductor device.   After forming the first insulating film and the conductive region, an insulating film covering the conductive region is formed by self-aligned etching inside the conductive region, and further on the trench bottom using the insulating film as a mask. 14. The method of manufacturing a trench lateral semiconductor device according to claim 13, wherein a deep trench is formed. In manufacturing the trench lateral semiconductor device according to claim 1,
After implanting a second conductivity type impurity into a second conductivity type semiconductor wafer and forming the upper semiconductor layer of the second conductivity type having a lower resistivity than the semiconductor wafer on the surface layer of the semiconductor wafer, Implanting a first conductivity type impurity into the upper semiconductor layer and forming the first conductivity type lower semiconductor layer on a surface layer of the upper semiconductor layer, thereby producing a first wafer;
Producing a second wafer by forming an insulating layer on the surface of the support wafer;
Bonding the surface of the lower semiconductor layer of the first wafer to the surface of the insulating layer of the second wafer and integrating the first wafer and the second wafer;
Polishing the back surface of the first wafer;
A method for manufacturing a trench lateral semiconductor device, comprising: In manufacturing the trench lateral semiconductor device according to claim 2,
A first conductivity type impurity is implanted into a first conductivity type semiconductor wafer, and a first conductivity type semiconductor layer having a resistivity lower than that of the semiconductor wafer is formed on a surface layer of the semiconductor wafer. Producing a wafer of 1;
Producing a second wafer by forming an insulating layer on the surface of the support wafer;
Bonding the surface of the semiconductor layer of the first wafer to the surface of the insulating layer of the second wafer and integrating the first wafer and the second wafer;
Polishing the back surface of the first wafer;
A method for manufacturing a trench lateral semiconductor device, comprising: In manufacturing the trench lateral semiconductor device according to claim 3,
After implanting a second conductivity type impurity into a second conductivity type semiconductor wafer and forming the upper semiconductor layer of the second conductivity type having a lower resistivity than the semiconductor wafer on the surface layer of the semiconductor wafer, Implanting a first conductivity type impurity into the upper semiconductor layer and forming the first conductivity type lower semiconductor layer on a surface layer of the upper semiconductor layer, thereby producing a first wafer;
Producing a second wafer by forming an insulating layer on the surface of the support wafer;
Bonding the surface of the lower semiconductor layer of the first wafer to the surface of the insulating layer of the second wafer and integrating the first wafer and the second wafer;
Polishing the back surface of the first wafer;
A method for manufacturing a trench lateral semiconductor device, comprising: In manufacturing the trench lateral semiconductor device according to claim 4,
A first conductivity type impurity is implanted into a first conductivity type semiconductor wafer, and a first conductivity type semiconductor layer having a resistivity lower than that of the semiconductor wafer is formed on a surface layer of the semiconductor wafer. Producing a wafer of 1;
Producing a second wafer by forming an insulating layer on the surface of the support wafer;
Bonding the surface of the semiconductor layer of the first wafer to the surface of the insulating layer of the second wafer and integrating the first wafer and the second wafer;
Polishing the back surface of the first wafer;
A method for manufacturing a trench lateral semiconductor device, comprising:

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