KR20060081914A - Output pin short circuit test method of semiconductor device - Google Patents

Abstract

The present invention discloses an output pin short test method of a semiconductor device.

The output pin short-circuit test method of the semiconductor device of the present invention includes a first step of applying a first test signal and a second test signal having different sizes to the first input pin and the second input pin of the semiconductor device; The output pins of the semiconductor device are divided into a first group and a second group, and the first test signal and the second test signal are switched at regular intervals to output the output pins of the first group and the output pins of the second group. Alternately outputting the second step; And a third step of determining whether the output pin is shorted by comparing the waveform of the signal output from the respective output pins with the waveform of the signal supplied to the input pin. Etch touch failure can be detected efficiently.

Description

Method for testing of output pin short in semiconductor device

1 is a view showing a metal lifting phenomenon by the wafer cutting process.

2 shows modeling for edge touch failures.

3 is a view showing the concept of a semiconductor device output pin short test method according to the present invention.

Figure 4 is a waveform diagram showing a comparison of the normal waveform and the distorted waveform.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method of a semiconductor device, and more particularly to edge touch defects due to high resistive short between output pins and between output pins and a substrate in semiconductor devices. An output pin short circuit test method of a semiconductor device that can be detected.

As the size of liquid crystal display (LCD) panels grows larger, the number of output pins of LCD driver ICs (LDIs) that process and control image data of LCD panels increases, resulting in products that currently have more than 500 pins. It is becoming. In order to implement such a large number of output pins in one IC, pad pitch has been gradually decreased to develop fine pitch products of 45 μm or less, and P4 for testing fine pitch products has been developed. (Photolithographic Pattern Plating Process) A probe card has been proposed. Therefore, securing the quality of many output pins has become an essential challenge these days, and researches on efficient test techniques for quality assurance have been actively conducted.

Recently, edge touch defects caused by resistive short-circuits between adjacent output pins or between output pins and wafer substrates are emerging in LDI, and edge touch defects cause line defects in LCD displays. It is linked to poor reliability of IC and is a major cause of deterioration of LCD panel quality. As a result of analyzing the electrical characteristics of LCD panel with line defects, the output voltage of LDI specific output pin at the position where the defect occurs is about 400 kHz lower than that of other adjacent normal pins. Analysis In the analysis, a hot spot appears as a leakage current occurs between the lead of the output pin and the IC edge.

Edge touch failures can also be caused by metal patterns or KLA keys on the scribe line of the wafer. As the wafer cutting process, which is one of the LDI assembly processes, the edge step of the IC is generated by the metal pattern in the scribe line or the metal lift of the KLA key, as shown in FIG. It lowers the edge gap margin, causing edge touch failure. The fine particles of the metal pattern or the KLA key remain on the output pin as a conductive material, and this material acts as a parasitic resistance on the output pin, causing a decrease in the output voltage.

FIG. 2 illustrates modeling of edge touch failure. In the case of a normal IC, since parasitic resistance Re does not exist between adjacent output pins or between the output pin and the substrate, the output voltage Vout is

Vout ≒ V1 or V2 or V3 or V4 or VSS

In the case of an output pin having an edge touch failure, as shown in FIG. Output to output pin. For example, the output voltage Vout for V4 is

Vout = V4 × [Re / (R1 + Re)]

It is defined as, and the dropped output voltage cannot normally control the pixels of the LCD panel.

Most conventional semiconductor IC tests begin with open / short tests using electrostatic discharge (ESD) devices designed for pads, which detect short circuit pins with a resistance of less than about 100 kΩ. (VSIM: 0.1V / 1 :).

However, when conventional short test techniques are used to detect hundreds of kΩ to several kΩ high resistive short pins that can result from edge touch failures, a typical ATE (Automatic Test Equipment) is the current measurement range (10 mA: 10㎁) and measurement resolution is limited, so it is impossible to screen edge touch defects.

Accordingly, an object of the present invention for solving the above-described problem is to efficiently detect etch touch defects due to high resistive short circuits in a short time by using a new output pin-to-short test method.

The output pin short circuit test method of the semiconductor device according to the present invention for achieving the above object is applied to the first test signal and the second test signal having a different size to each of the first input pin and the second input pin of the semiconductor device. A first step of making; The output pins of the semiconductor device are divided into a first group and a second group, and the first test signal and the second test signal are switched at regular intervals to output the output pins of the first group and the output pins of the second group. Alternately outputting the second step; And a third step of determining whether a short circuit of the output pin compares the waveform of the signal output from the respective output pins with the waveform of the signal supplied to the input pin.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a view showing the concept of a semiconductor device output pin short test method according to the present invention.

The test method according to the present invention divides the output pins of the LDI (LCD Driver IC) into odd-numbered output pins (hereinafter referred to as odd output pins) and even-numbered output pins (hereinafter referred to as even output pins), and multiple lines. By using the MLS (Multi Line Selection) method, the test signals applied through the two input pads V1 and V4 are alternately switched between the odd output pins and the even output pins, respectively. At this time, in the ATE, a voltage of 5V is applied to the V1 channel and a voltage of 10V to the V4 channel to output pulse signals having different magnitudes between adjacent output pins as shown in FIG.

Referring to the test method of the present invention in more detail as follows.

First, the packaged semiconductor device is loaded on the ATE, which is an automatic test equipment, so that the test signals V1 to V5 from the ATE can be applied to the input pads of the LDI.

Among the test signals applied through the input pad of the LDI, the signals applied through specific channels V1 and V4 are alternately switched to odd and even output pins at regular intervals through the logic circuit of the LDI. That is, the logic circuit of the LDI has an output driver having a switching circuit as shown in FIG. 2 so that the test signal applied through the V4 channel of the ATE is simultaneously output to the odd output pins and the test signal applied to the V1 channel is even. Output to the output pins at the same time. Next, the logic circuit of the LDI switches the path of the test signal to output the test signal applied through the V4 channel to even output pins and the test signal applied to the V1 channel to odd output pins. By repeating this switching operation in a certain period, the signals output to each output pin of the LDI is in the form of a pulse signal in which the high level (M1) and the low level (M2) are repeated at a constant period, as shown in Figure 3, in particular between adjacent pins Signals out of phase with each other are output.

As a switching method for the output signals, after the 4-bit data '1111b' is written in the odd-output pin data area and the 4-bit data '0000b' is written in the even-output pin data area in the memory embedded in the logic circuit, All data is synchronized to the system clock to be converted into 5-bit data through a decoder (not shown) defined as a function of MLS (Multi Line Selection). By using the decoded signal as a logic control signal of the output driver as shown in FIG. 2, the on / off of the MOS transistors is controlled so that the signal of V1 is output to the even output pad and the signal of V4 is output to the odd output pad. have.

Next, the signal waveforms measured in the test signal supply channels V1 and V4 of the ATE are compared with the waveforms of the signals output from the respective output pins of the LDI. In this case, when a specific output pin is shorted by the parasitic resistance Re, the waveform of the signal output through the corresponding output pin is output as a distortion waveform (Bad waveform) as compared with the normal waveform as shown in FIG. You can immediately see if a short circuit has occurred on the output pins, and at the same time test all the output pins. In particular, because two adjacent output pins output signals of different phases, if a short circuit occurs between adjacent output pins, the signal output from the corresponding output pin is more distorted to half the level of the applied signal. The position can be easily determined.

In the above-described embodiment, when the test signal of fixed magnitude is applied to the two channels V1 and V4 in the ATE, the signals applied through the two channels V1 and V4 are switched in the logic circuit of the LDI. It is not limited to this. That is, without configuring a separate circuit for signal switching in the logic circuit of the LDI, only the path connecting the channel V4 and the odd output pins and the path connecting the channel V1 and the even output pins are set in advance. The same pulse signal as the output signal may be applied to the two channels V1 and V4.

As described above, the output pin short test method of the semiconductor device according to the present invention can detect the etch touch defect due to the high resistive short circuit in a short time by a simple method.

Claims (3)

A first step of applying a first test signal and a second test signal having different sizes to the first input pin and the second input pin of the semiconductor device; The output pins of the semiconductor device are divided into a first group and a second group, and the first test signal and the second test signal are switched at regular intervals to output the output pins of the first group and the output pins of the second group. Alternately outputting the second step; And And comparing a waveform of a signal output from each of the output pins with a waveform of a signal supplied to the input pin to determine whether the output pin is short-circuited. The method of claim 1, And the output pins of the first group are odd-numbered output pins, and the output pins of the second group are even-numbered output pins. The method of claim 2, wherein the second step Storing predetermined bits of data in a data area corresponding to the odd-numbered output pin and a data area corresponding to the even-numbered output pin; Generating a logic control signal by decoding data stored in each data area in synchronization with a system clock using a multi-line simultaneous selection (MLS) function; And And controlling the operation of the output driver of the semiconductor device according to the logic control signal to switch the test signals.

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