KR20040043548A - Method of forming gate for semiconductor devices - Google Patents

Abstract

Forming a mold film on the substrate, etching the mold film to form a gate trench, forming a spacer having an etching selectivity with the mold film on the sidewalls of the gate trench, exposing the substrate to the bottom of the gate trench on which the spacer is formed, Forming a gate insulating film on the substrate exposed to the bottom of the trench, stacking and etching a lower gate electrode layer having an etch selectivity with the mold layer and the spacer to expose the upper portion of the mold layer and the spacer, and forming a lower electrode defined in the trench; Removing the spacer from the substrate on which the lower electrode is formed, forming an upper electrode filling the space where the spacer is removed and the gate trench space above the lower electrode, and removing the remaining mold layer to leave a gate electrode composed of the upper electrode and the lower electrode. Half equipped with steps A method of forming a conductor device gate is disclosed.

According to the present invention, a gate having a fine line width can be formed by arbitrarily adjusting the gate length, and a region where the source / drain region overlaps with the gate electrode is reduced to prevent the transistor operation speed from being reduced by the parasitic capacitor. It is possible to reduce the interface resistance between the lower electrode and the upper electrode at the gate.

Description

Method of forming gate for semiconductor devices

The present invention relates to a method for forming a semiconductor device gate, and more particularly, to a method for forming a semiconductor device gate using a damascene process.

As device integration of semiconductor devices is achieved, the size of semiconductor devices is gradually reduced. In order to exhibit the function of each device in a fine pattern without abnormality, fine defects also need to be removed. When forming a gate of a MOS transistor, it is common to use a method of forming a gate insulating film on a substrate and stacking and patterning a gate conductive film. However, the gate formed by the conductive film patterning has a problem such that the etched sidewall portion is damaged during etching, so that the flow of charge from the channel to the peripheral portion of the gate becomes uneven and leakage of current occurs.

In order to solve the problem of damage caused by gate patterning, a damascene process using a dummy gate may be used to form the gate. The gate forming method using the damascene process can be briefly described with reference to FIGS. 1 to 3.

Referring to FIG. 1, a buffer film 2 is formed on a substrate 1 and a dummy gate film is stacked. Through the patterning, a dummy gate 11 made of a dummy gate film is formed.

Referring to FIG. 2, a mold film 13 having an etch selectivity with a dummy gate layer is stacked on a substrate on which a dummy gate is formed. The dummy gate upper surface is exposed through the CMP for the mold film 13. The dummy gate and the buffer layer below the dummy gate are etched and removed. Thus, a gate mold made of the mold film 13 is formed.

Referring to FIG. 3, as shown in FIG. 2, a gate insulating layer 15 is formed on a surface of the substrate 1 exposed through thermal oxidation while the substrate is exposed in a region where the dummy gate is removed. The space where the dummy gate is removed is filled through the gate conductive film stack on the substrate. The gate line 17 is formed by performing planarization etching on the gate conductive layer until the upper surface of the mold layer 13 is exposed.

Although not shown, the mold film may be removed over the entire surface of the substrate, and then the buffer film under the mold film may be removed. Accordingly, the gate line 17 including the gate insulating layer 15 and the gate conductive layer is formed on the substrate without patterning the gate conductive layer, and no damage portion due to etching is present on the sidewall of the gate line.

However, if the line width of the gate pattern is narrowed as the device is highly integrated, the gate forming method using the dummy gate also has a problem in that the desired line width cannot be realized due to the limitation of the exposure process. When a source / drain region is formed by ion implantation, a parasitic capacitor is formed between the gate electrode and the source / drain region as the source / drain region partially overlaps with the gate electrode when viewed from above by impurity diffusion. Parasitic capacitors interfere with the fast operation of transistors and degrade the performance of semiconductor devices. On the other hand, when the gate forms a multilayer structure in which two or more material layers overlap, when the line width is narrowed, the interface area between the lower conductive film and the upper conductive film is also reduced, thereby increasing the interface resistance.

The present invention can achieve a narrow gate pattern line width not achieved through the conventional gate formation method using a dummy gate, and can reduce the overlapping area between the gate electrode and the source / drain to suppress parasitic capacitor formation. It is an object to provide a method for forming a device gate.

1 to 3 are cross-sectional views illustrating the main steps of a conventional method of forming a gate electrode using a dummy gate;

4 to 10 are process cross-sectional views showing main steps of a method of forming a gate electrode according to an embodiment of the present invention;

11 and 12 are partial cross-sectional views showing a cross section of a gate electrode made by another embodiment of the present invention.

In the gate forming method of the present invention for achieving the above object, forming a mold film on the substrate, etching the mold film to form a gate trench, forming a spacer having an etching selectivity with the mold film on the gate trench side wall Exposing the substrate to the bottom of the gate trench on which the spacer is formed; forming a gate insulating film on the substrate exposed by the trench bottom; stacking and etching the mold layer and the lower gate electrode layer having the etching selectivity with the mold layer and the spacer; Forming an upper electrode that exposes an upper portion and is confined to a trench, removing a spacer from the substrate on which the lower electrode is formed, forming an upper electrode that fills the space where the spacer is removed and the gate trench space above the lower electrode, and the remaining mold Remove the membrane to remove the upper electrode and lower electrode It is achieved by having the step, leaving a gate electrode made of.

In the present invention, it is common to form a thin buffer film on the substrate to buffer the stress between the substrate and the mold film before forming the mold film. The buffer film is removed together at the end of exposing the substrate by removing the mold film.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4 through 10 are process cross-sectional views illustrating important steps in forming a method of forming a semiconductor device gate in accordance with an embodiment of the present invention.

Referring to FIG. 4, a thin thermal oxide film is formed on the separated silicon substrate 1 with the buffer film 2, and a mold film 3 is formed on the buffer film 2 with the silicon nitride film. Subsequently, the gate trench 4 is formed in the region where the gate line is to be formed by patterning the mold layer 3. In the etching process of forming the gate trench 4, the etching may be performed until the buffer film 2 or the substrate 1 is exposed on the bottom surface of the trench. In this embodiment, the etching process is performed so that the mold layer 3 remains a certain thickness.

Referring to FIG. 5, a silicon oxide layer is deposited on the entire surface of the substrate on which the gate trench is formed, and the spacers 7 remain only on the gate trench sidewalls through the front etch back. Therefore, the silicon oxide film for the spacer 7 should be formed to a thickness less than half the width of the gate trench. By controlling the thickness of the silicon oxide layer, the width of the gate trench remaining in the space after the spacer 7 is formed may be adjusted, thereby forming a gate line having a fine line width exceeding an exposure limit.

Referring to FIG. 6, the substrate 1 is exposed by etching the bottom surface of the remaining trench formed of the remaining space of the trench using the spacer 7 as an etching mask. When the trench bottom reaches the substrate 1 when the gate trench 4 is formed in the step of FIG. 4, since the substrate 1 is already exposed on the bottom of the remaining trench in the step of FIG. 5, the substrate may be exposed through separate etching. There is no need.

In this case, in order to expose the substrate 1, etching of the buffer layer 2 under the mold layer 3 is performed in the remaining trenches. Impurity ion implantation is conventionally performed by using the spacer 7 and the mold layer 3 as an ion implantation mask to control voltage and prevent punch through to the exposed substrate 1 in the gate region.

Referring to FIG. 7, the substrate is thermally oxidized while the substrate is exposed on the bottom of the remaining trench to form a gate insulating film 9 in the gate region. Subsequently, the first conductive film 11 to form the lower electrode is stacked over the entire substrate to fill the remaining trenches. The lower electrode is usually formed of doped polysilicon. The CMP process removes the first conductive layer stacked on the upper surface of the mold layer 3 so that the first conductive layer 11 is present only in the remaining trenches.

Referring to FIG. 8, the planarized surface is further etched back to the first conductive film 11 in a state where the top surface has the same level as the top surface of the mold film 3 so that the top surface reaches a predetermined level in the remaining trench. As a result, the lower electrode 111 is formed. If the etch back is made in place of CMP processing in the description of Fig. 7, Figs. 7 and 8 can be made continuously.

Referring to FIG. 9, the silicon oxide film is etched to remove the spacers 7 of FIG. 8 from the gate trench sidewalls. The spacer 7 may be removed entirely or leave a residual spacer 71 of a constant thickness below. Next, planarization processing is performed on the second conductive film stack and the second conductive film. The second conductive film is preferably made of a metal such as tungsten or a material having good conductivity such as metal silicide in order to increase the conductivity of the gate electrode. The planarization processing for the second conductive film may be usually made of CMP and is performed until the top surface of the mold film 3 is exposed. Prior to metal lamination, barrier films such as tungsten nitride film and titanium / titanium nitride film may be laminated thinly. As a result, the gate upper electrode 13 is formed. Since the lower electrode 111 made of the first conductive film and the upper electrode 13 made of the second conductive film are contacted through three sides in the cross-sectional view, the interface resistance is increased by increasing the interface between the lower electrode 111 and the upper electrode 13. Can have the effect of reducing In addition, while reducing the channel length, the gate upper electrode may be formed wider than the lower electrode, thereby reducing the overall gate line resistance.

Referring to FIG. 10, in the state of FIG. 9, an isotropic etching such as wet etching including nitric acid is performed on the mold film 3 of silicon nitride film quality. Therefore, the remaining mold film 3 of the substrate is all removed. When the buffer film 2 and the remaining spacers 71 made of silicon oxide are present, isotropic etching is performed on the buffer film 2 and the remaining spacers 71. Accordingly, a mold-type gate line including the upper electrode 13 and the lower electrode 111 is formed on the sidewall without being damaged by patterning.

In the gate structure shown in FIG. 10 formed through this embodiment, the gate width of the lower electrode is reduced. That is, in the MOS transistor, the width of the gate electrode contacted through the substrate 1 and the gate insulating film 9 is reduced, thereby reducing the length of the channel. On the other hand, the upper electrode 13 is formed so as to surround the upper portion of the lower electrode 111 in at least two directions. That is, at least two side surfaces of the upper part of the lower electrode 111 are covered by the upper electrode 13. The width from one side of the upper electrode 13 to the other side is larger than the width of the lower electrode 111.

According to the present invention, since the gate length can be reduced by using the spacer, a gate having a fine line width can be formed. In addition, the region where the source / drain regions overlapped with the gate electrode formed by the source / drain ion implantation and diffusion are substantially eliminated, thereby preventing the transistor operating speed from being reduced by the parasitic capacitor.

11 is a partial cross-sectional view showing another embodiment of the present invention. In this form, the first conductive film is recessed until the upper surface of the lower electrode 111 reaches the lower surface of the spacer 7 while forming the state of FIG. 8 or the etching of the spacer 7 while the state of FIG. 9 is formed. The spacer 7 may be removed only to the upper surface of the lower electrode 111, and the remaining spacers 71 may be left.

12 is a partial cross-sectional view showing yet another embodiment of the present invention. In this state, as shown in FIG. 7, the spacer 7 is removed by wet etching without the first conductive layer 11 recessed immediately, and the tungsten and poly are thermally treated by filling the space where the spacer 7 is present through tungsten deposition. It can be formed by the method of carrying out the oxidization in the part 15 which silicon contact | connects, and performing a board | substrate tungsten CMP. In this case, in order to remove the spacers 7, the top surface of the spacers 7 must be exposed in wet etching, so that the edges of the edges are adjusted in the forming process of the spacers 7 and the degree of planarization is controlled to stack and planarize the first conductive layer. When closed, a portion of the upper surface of the spacer 7 should not be covered by the first conductive film 11.

In this type of gate line, the upper electrode is formed on both side surfaces of the upper lower electrode, the upper width of the lower electrode is wider than the lower width, and the upper surface is silicided.

According to the present invention, a gate having a fine line width can be formed by arbitrarily adjusting the gate length, and a region where the source / drain region overlaps with the gate electrode is reduced to prevent the transistor operation speed from being reduced by the parasitic capacitor. Can be. In addition, the contact area between the lower electrode and the upper electrode may be increased to reduce the interface resistance.

Claims (4)

Forming a mold film on the substrate, Etching the mold layer to form a gate trench; Forming a spacer having an etch selectivity with a mold layer on sidewalls of the gate trench; Exposing a substrate to a bottom of the gate trench in which the spacer is formed; Forming a gate insulating film on the substrate exposed through the trench bottom surface; Stacking and etching the mold layer and the lower gate electrode layer having an etch selectivity with the spacer to expose the mold layer and the upper portion of the spacer, and to form a lower electrode having an upper surface below the upper surface of the mold layer; Removing the spacer from the substrate on which the lower electrode is formed; Forming an upper electrode filling the space where the spacer is removed and the gate trench space above the lower electrode; Removing the remaining portion of the mold film to leave a gate electrode consisting of the upper electrode and the lower electrode. The method of claim 1, And forming a buffer film on the substrate before forming the mold film. The method of claim 1, And wherein the mold film is a silicon nitride film, the spacer is a silicon oxide film, and the lower electrode is made of polysilicon. The method of claim 1, And the upper electrode is made of tungsten.