KR20120003422A - Buried gate electrode of transistor and method of forming same - Google Patents

Abstract

A buried gate electrode of a transistor and a method of forming the same are provided. The gate electrode includes a trench formed in the substrate and a silicon pattern conformally covering the inner wall of the trench and having a gap region at the center thereof. A tungsten pattern is filled in the gap region of the silicon pattern, and an adhesive layer pattern is interposed between the silicon pattern and the tungsten pattern. A capping layer covers an upper portion of the silicon pattern and the tungsten pattern. Thus, ends of the silicon pattern and the tungsten pattern interface may be covered by the capping layer. The silicon pattern may have sidewalls extending vertically from the substrate surface. Sidewalls of the silicon pattern are aligned with sidewalls of the capping layer. A gate poly oxide layer may be formed on the stretched sidewall of the silicon pattern.

Description

Buried gate electrode of transistor and method of forming the same {BURIED GATE ELECTRODE OF TRANSISTOR AND METHOD OF FORMING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a gate electrode of a transistor and a method of forming the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a gate electrode of a transistor and a method of forming the same.

As the gate line width of the transistor decreases, a low resistance metal is introduced as a material for forming the gate electrode to improve the operation speed. Among the low-resistance metals, tungsten has the advantage that deformation does not occur in subsequent thermal processes and that the diffusion of the metal through the insulating film is not concerned, and thus is suitable for adoption in next-generation low-resistance gates.

Compared to polyside gate electrodes currently used, tungsten-based polymetal gates have low specific resistance and less dependence on line width, and thus are expected to be applied to general polyside gate electrode forming processes.

1 to 3 are cross-sectional views illustrating a conventional transistor and a manufacturing method.

Referring to FIG. 1, an isolation region 12 is formed on a semiconductor substrate 10 to define an active region. Using a conventional DRAM device as an example, the device isolation layer 12 defines a plurality of isolated active regions, and the active regions are vertically and horizontally arranged in a cell array. The gate electrode 28 intersects with the gate insulating layer 16 on the active region. The gate electrode 28 includes a lower silicon film 18 and an upper tungsten film 22. An adhesive layer 22 made of a metal nitride film is formed between the silicon film 18 and the tungsten film 22. May be interposed. The silicon film 18 may be polysilicon or amorphous silicon. The adhesive layer 22 may increase adhesion between silicon and tungsten and may have a function of an ohmic layer. A capping layer 24 is formed on the tungsten film 22.

Referring to FIG. 2, the gate electrode 28 is formed by patterning a silicon film, an adhesive layer 22, a tungsten film 22, and a capping layer 24 sequentially stacked on a substrate. Therefore, the surface of the silicon layer 18 may be damaged during etching. Therefore, in the conventional transistor forming step, a thermal oxidation step is performed to cure the surface defect of the silicon film after the gate electrode is formed. As a result, the surface of the silicon film 18 is oxidized to form a thermal oxide film 26.

Referring to FIG. 3, an LDD layer (not shown) is formed in a substrate on both sides of a gate electrode by applying the defect curing and an ion implantation process, and sidewall spacers 30 are formed on sidewalls of the gate electrode. After the sidewall spacers 30 are formed, impurities are implanted into the substrate to form a high concentration source / drain (not shown).

As described above, when the polymetal gate electrode including the silicon film and the metal film is adopted in the transistor manufacturing process, a conventional transistor manufacturing process can be applied by replacing tungsten silicide with a conventional tungsten silicide or a laminate layer of an adhesive layer and tungsten.

As mentioned above, a thermal oxidation process is performed to cure the etch loss of the sidewalls of the silicon film while patterning the gate electrode. At this time, since the interface between the silicon film 18 and the tungsten film 22 is exposed in the conventional gate structure, oxygen may diffuse through these interfaces and interface oxidation may occur. When the interface of the conductive film constituting the gate electrode is oxidized, parasitic capacitance and parasitic resistance are increased, resulting in degrading the performance of the transistor.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a gate electrode of a transistor having a structure capable of preventing interfacial oxidation of a silicon film and a tungsten film and a method of forming the same in introducing a polymetal gate.

In order to achieve the above technical problem, the present invention provides a gate electrode embedded in a substrate and a method of forming the same. The gate electrode includes a trench formed in the substrate and a silicon pattern conformally covering the inner wall of the trench and having a gap region at the center thereof. A tungsten pattern is filled in the gap region of the silicon pattern, and an adhesive layer pattern is interposed between the silicon pattern and the tungsten pattern. A capping layer covers an upper portion of the silicon pattern and the tungsten pattern. Thus, ends of the silicon pattern and the tungsten pattern interface may be covered by the capping layer. The silicon pattern may have sidewalls extending vertically from the substrate surface. Sidewalls of the silicon pattern are aligned with sidewalls of the capping layer. A gate poly oxide layer may be formed on the stretched sidewall of the silicon pattern.

Specifically, an isolation layer may be formed on the substrate to define an active region, and the trench may be formed to cross the active region and the isolation layer. In addition, sidewall spacers may be formed on substrates on both sides of the silicon pattern. The sidewall spacer is aligned with an inner wall on the sidewall of the capping layer.

The method for forming the gate electrode includes etching a substrate to form a trench, and forming a silicon film on the substrate to conformally cover the inner wall of the trench. The silicon film has a gap region at the center of the trench. An adhesive layer is conformally formed on the silicon film, and a tungsten film is formed on the adhesive layer to fill a gap region. The tungsten film and the adhesive layer are recessed to expose the silicon film and to form a tungsten pattern filled in the gap region. A capping layer is formed on the entire surface of the substrate on which the tungsten film is formed. The capping layer and the silicon film are sequentially patterned. As a result, a silicon pattern is formed below the capping layer and a tungsten pattern is formed in the center. After forming the silicon pattern, the method may further include thermally oxidizing a sidewall of the silicon pattern vertically extended from the substrate surface to form a thermal oxide film.

According to the present invention as described above, the end portion of the interface between the silicon pattern and the adhesive layer is covered with the capping layer and protected. Therefore, the diffusion of oxygen into the interface of the silicon pattern while the gate poly oxide film is formed can be suppressed to prevent interfacial oxidation of the silicon pattern. Therefore, the parasitic resistance and the parasitic capacitance are prevented from increasing due to the interfacial oxidation of the silicon pattern, so that the signal transmission speed of the gate electrode is improved, and a transistor having a high operating speed can be provided.

1 to 3 are cross-sectional views illustrating a conventional transistor and a manufacturing method.
4 is a cross-sectional view illustrating a transistor according to a preferred embodiment of the present invention.
5 to 9 are cross-sectional views illustrating a method of manufacturing a transistor according to a preferred embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thicknesses of the layers and regions are exaggerated for clarity. If a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween. Where a structure is said to be "adjacent" to another structure or substrate, it may be formed directly adjacent to another structure or substrate, or a third structure may be interposed therebetween.

4 is a cross-sectional view illustrating a transistor according to a preferred embodiment of the present invention.

Referring to FIG. 4, an isolation layer 52 is formed on the substrate 10 to define an active region. A plurality of trenches 54 are formed across the active region and the device isolation layer 52. A conformal silicon pattern 58p is formed on the inner wall of the trench 54. The silicon pattern 58p has a gap region in the center thereof, and a tungsten pattern 62p is filled in the gap region. An adhesive layer pattern 60p is interposed between the tungsten pattern 62p and the silicon pattern 58p, and a gate insulating layer 56 is interposed between the silicon pattern and the substrate 10. A capping layer 64 is formed on the silicon pattern 58p and the tungsten pattern 62p. Thus, an end portion of the interface between the silicon pattern 58p and the adhesive layer pattern 60p and the interface between the tungsten pattern 62p and the adhesive layer pattern 60p is covered with the capping layer 64. The silicon pattern 58p has sidewalls extending vertically from the substrate surface, and a gate poly oxide film 66 is formed on the sidewalls. A sidewall oxide film having an inner wall aligned with the sidewall of the capping layer 64 is formed on the substrate on both sides of the silicon pattern 58p. The silicon pattern 58p, the adhesive layer pattern 60p, and the tungsten pattern 62p form a gate electrode 68. Since the trench 54 extends not only into the active region but also to the device isolation layer, the gate electrode 68 may cross the active region and the upper portion of the device isolation layer corresponding to the trench 54.

A gate insulating film 56 is interposed between the gate electrode 68 and the substrate 10. The gate insulating layer 56 may be a silicon oxide layer or a dielectric layer having a high dielectric constant. For example, the gate insulating layer 56 may include a silicon oxide layer, a hafnium oxide layer (HfO), an aluminum oxide layer (Al ₂ O ₃ ), a zirconium oxide layer (ZrO), a tantalum oxide layer (Ta ₂ O ₅ ), a titanium oxide layer (TiO ₂ ), and It may be one selected from hafnium silicon oxide (HfSiO) or a composite film thereof.

5 to 9 are cross-sectional views illustrating a method of manufacturing a transistor according to a preferred embodiment of the present invention.

Referring to FIG. 5, an isolation region 52 is formed on a substrate 10 to define an active region. The substrate of the active region and the device isolation layer 52 are etched to form trenches 54 that cross the active region and the device isolation layer 52. The plurality of active regions is present in the cell array region and arranged vertically and horizontally. Thus, the trench 54 crosses the plurality of active regions and the plurality of device isolation layers. In addition, the trench 54 is formed at a position corresponding to the gate electrode disposed in the cell array.

Referring to FIG. 6, a gate insulating film 56, a silicon film 58, an adhesive layer 60, and a tungsten film 62 are formed on the entire surface of the substrate. By forming and removing the sacrificial thermal oxide film on the entire surface of the substrate prior to forming the gate insulating film 56, a process of curing the damage caused during the trench formation may be added. The gate insulating layer 56, the silicon layer 58, and the adhesive layer 60 are conformally formed. Therefore, the silicon layer 58 may have a gap region at the center of the trench. The gate insulating film 56 may be formed of a silicon oxide film or a dielectric film having a high dielectric constant. For example, the gate insulating layer 56 may include a silicon oxide layer, a hafnium oxide layer (HfO), an aluminum oxide layer (Al ₂ O ₃ ), a zirconium oxide layer (ZrO), a tantalum oxide layer (Ta ₂ O ₅ ), a titanium oxide layer (TiO ₂ ), and The hafnium silicon oxide (HfSiO) may be formed of one or a composite film thereof.

The tungsten film 62 is formed to fill the gap region. The silicon film 58 may be formed of amorphous silicon or polysilicon. The silicon film may be replaced with a silicon germanium film or a germanium film. Also, if necessary, n-type or n-type impurities may be doped.

Referring to FIG. 7, the tungsten film 62 and the adhesive layer 60 are sequentially recessed. At this time, the tungsten pattern 62p filled in the gap region of the silicon film 58 by polishing the tungsten film 62 and the adhesive layer 60 so that the silicon film 58 is exposed by applying a chemical mechanical polishing process. And an adhesive layer pattern 60p interposed between the tungsten pattern 62p and the silicon layer 58.

Referring to FIG. 8, capping layers 64 are formed on the trenches, respectively. The capping layer 64 may be formed by forming an insulating film, which is a capping layer, on the entire surface of the substrate, and patterning the insulating film.

Referring to FIG. 9, after the capping layer 64 is formed, the silicon layer 58 is subsequently patterned to form a silicon pattern 58p aligned with each trench 54. The capping layer 64 and the silicon pattern 58p may be continuously formed through a single photo process, or the capping layer 64 may be formed as an etch mask after the capping layer 64 is formed. have. As a result, the buried gate electrode 68 formed of the silicon pattern 58p, the adhesive layer pattern 60p, and the tungsten pattern 62p is formed. The buried gate electrode 68 crosses the active region and the upper portion of the device isolation layer, respectively, corresponding to the trench.

Due to damage caused during the formation of the silicon pattern 58p, defects may occur on the sidewalls of the silicon pattern vertically extending above the substrate surface. Therefore, as in the conventional gate forming technique, the substrate is heat-treated to form a gate poly oxide film 66 on sidewalls of the silicon pattern. At this time, in the conventional gate structure, since the interface between the silicon pattern and the adhesive layer and the tungsten pattern and the adhesive layer is exposed to the outside, oxygen diffuses through these interfaces to form an oxide film at the interface of the silicon pattern. However, according to the present invention as shown in FIG. 9, the interface between the silicon pattern 58p and the adhesive layer pattern 60p and the tungsten pattern 62p and the adhesive layer pattern 60p is covered by the capping layer 64. And the ends of these interfaces are also covered with the capping layer and have a structure protected from oxygen diffusion. Therefore, interfacial oxidation of the silicon pattern can be prevented while the gate poly oxide film 66 is formed.

Subsequently, impurities are implanted into the substrate of the active region to form an LDD region (not shown), and sidewall spacers (70 in FIG. 4) aligned with sidewalls of the capping layer 64 are formed on the substrates on both sides of the silicon pattern. In the substrate of the active region to form a high concentration source / drain can be carried out.

Claims (6)

Etching the substrate to form a trench;
Forming a silicon film on the substrate conformally covering the inner wall of the trench and having a gap region at the center of the trench;
Conformally forming an adhesive layer on the silicon film;
Forming a tungsten film filling a gap region on the adhesive layer;
Recessing the tungsten film and the adhesive layer using a chemical mechanical polishing process to expose the top surface of the silicon film and simultaneously form a tungsten pattern and an adhesive layer pattern filled in the gap region;
Forming a capping layer on an entire surface of the substrate on which the tungsten pattern and the adhesive layer pattern are formed; and
And sequentially patterning the capping layer and the silicon layer to form a silicon pattern under the capping layer and having a tungsten pattern formed in the center thereof.
The capping layer is in contact with the upper surface of the silicon pattern, the adhesive layer pattern and the tungsten pattern at the same time,
And the thermal oxide layer is formed to contact the lower surface of the capping layer. The method of claim 1,
Forming the trench,
Forming an isolation layer on the substrate to define an active region;
And forming a trench that crosses the active region and the device isolation layer by etching the substrate and the device isolation layer in the active region. The method of claim 1,
After forming the silicon pattern,
And thermally oxidizing sidewalls of the silicon pattern vertically extended from the substrate surface to form a thermal oxide film. The method of claim 1,
And forming sidewall spacers simultaneously covering sidewalls of the capping layer and sidewalls of the silicon pattern on substrates on both sides of the silicon pattern. The method according to any one of claims 1 to 4,
The gate insulating film may be a silicon oxide film, a hafnium oxide film (HfO), an aluminum oxide film (Al ₂ O ₃ ), a zirconium oxide film (ZrO), a tantalum oxide film (Ta ₂ O ₅ ), a titanium oxide film (TiO ₂ ), and a hafnium silicon oxide film (HfSiO). And one or a composite film thereof. The method of claim 1,
And the top surfaces of the silicon pattern, the adhesive layer pattern, and the tungsten pattern are formed to have the same height as the bottom surface of the capping layer.

Images