JPH11237440A - Method and apparatus for creating data for integrated circuit test - Google Patents

Abstract

(57) [Problem] To reduce labor and time required for generating test pattern data and expected value mask data used for an integrated circuit tester and for testing them. SOLUTION: An expected value mask means 155 includes a minimum delay execution result of a simulation test result by a simulation test pattern used in a logic simulator,
The standard value delay execution result and the maximum value delay execution result are collated with each other, and tester expected value mask data used for the integrated circuit tester 174 is created. Eliminating the troublesome work regarding the tester expected value mask data is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit test data creating method and apparatus for creating data used in an integrated circuit tester for testing product operation of an integrated circuit while providing a test pattern for the tester. In particular, the present invention relates to an integrated circuit test data generation method and apparatus that can reduce the labor and time required for generating test pattern data and expected value mask data used for an integrated circuit tester and for testing them.

[0002]

2. Description of the Related Art FIG. 1 is a flowchart showing a procedure for preparing data for testing an integrated circuit in the related art.

In FIG. 1, a logic simulator 150,
Execution result file 1 in which Type delayed execution results are written
The test pattern conversion means 156 and the test pattern conversion means 156 are configured in a computer device for CAD (computer aided design) used by a logic designer. Further, the tester patterns 158 and 172, the logic simulator 162, and the expected value masking means 170 are configured in a CAD computer device used by a semiconductor vendor. or,
In addition to the computer device, an integrated circuit tester 174 is provided on the semiconductor vendor side.

[0004] In FIG. 1, first, the work is performed on the logic designer side.

First, the logic simulator 150 simulates a circuit built in an integrated circuit under test while giving a test pattern for simulation,
Perform a logic simulation to test the validity of the circuit. At reference numeral 152, if there is no problem in the Min delay execution result, the Type delay execution result, and the Max delay execution result, the data of the execution result file 154 is obtained. The data is usually data of a Type delay execution result, but may be data of a Min delay execution result or Max delay execution result in some cases.

Next, the test pattern conversion means 156 converts the test pattern for simulation stored in the execution result file 154 so as to be used by the integrated circuit tester. This conversion is to generate tester test pattern data 158 from any of the output results of the Min delay execution result, the Type delay execution result, and the Max delay execution result. Usually, Ty
Data is generated from the output result of the p-delay execution result.

After the above logic designer work, the following semiconductor vendor work is performed.

[0008] The logic simulator 162 executes a logic simulation based on the input pattern for the logic simulator obtained from the tester pattern 158. At reference numeral 164, it is determined whether there is no problem in the result of the logic simulation.

If it is determined that there is no problem, the tester test pattern of the tester pattern 158 is adopted. or,
Using the pattern, an integrated circuit tester 174 tests the product operation of the integrated circuit.

On the other hand, if it is determined that there is a problem, the reason is investigated, and the expected value masking means 170 sets the expected value mask of the tester pattern 158 to obtain the tester pattern 172. Thereafter, the tester pattern 17
2, the integrated circuit tester 174 tests the product operation of the integrated circuit.

As described above, in the logic simulation and the product integrated circuit test, three types of execution results are usually called a Min delay execution result, a Type delay execution result, and a Max delay execution result. Is obtained. These execution results are based on the operating conditions of the simulation and the operating conditions of the integrated circuit of the product.
Mutually different.

First, the result of the execution of the Min delay is also referred to as the result of the execution of the minimum delay, and is used when various operating conditions are advantageous for the stable operation of the circuit. That is, the variation in the manufacturing process of the integrated circuit is small. The ambient temperature during operation of the integrated circuit is low. The power supply voltage during operation of the integrated circuit is high.

On the other hand, the result of the Max delay execution is also called the result of the maximum delay execution when the various operating conditions are disadvantageous for the stable operation of the circuit. That is, the manufacturing process of the integrated circuit varies greatly. Ambient temperature during operation of the integrated circuit is high. The power supply voltage during the operation of the integrated circuit is low.

The result of the Type delay execution is also referred to as a result of the standard delay execution, and is a case in which various operating conditions are standard in terms of stable operation of the circuit. That is, variations in the manufacturing process of the integrated circuit are standard. The ambient temperature during operation of the integrated circuit is standard. The power supply voltage during the operation of the integrated circuit is standard.

[0015]

In the above-described conventional method for producing data for an integrated circuit test, reference numeral 164 may indicate that there is a problem. For example, a Min delay execution result, a Type delay execution result, and Max in the logic simulator 150, and a Min delay execution result, a Type delay execution result, and Ma in the logic simulator 162
This is the case where x does not match.

When it is determined that the execution results do not match due to various factors, the semiconductor vendor side specifically explains the mismatched portion to the logic designer side to investigate the cause. On the other hand, the logic designer investigates the circuit in question.

If it is determined in the investigation that the mismatch does not cause a problem in circuit operation, the fact is notified to the semiconductor vendor. Then, the semiconductor vendor side sets and corrects the corresponding unmatched portion of the expected value mask to “X” (don't care treatment: indefinite value treatment) in the expected value masking means 170 described above. The portion where the expected value mask is set to “X” is excluded from the test target in the integrated circuit tester 174 regardless of the execution result.

On the other hand, in the investigation, the discrepancy indicates that
If there is a problem, the logic designer further exchanges information with the semiconductor vendor, clarifies the cause, and solves the problem. For example, provide an error message output by the expected value collation tool from the semiconductor vendor to the logic designer,
Make sure to check.

As described above, when it is determined that the execution results do not match, the required labor and time increase. If the execution results do not match, the related error message output by the expected value matching tool may become enormous. This analysis takes a lot of time. Further, the execution speed of the expected value matching tool is reduced. In addition, there is a problem in that information is exchanged between the logic designer side and the semiconductor vendor side, so that the number of design steps is increased, and the required labor and time are enormous in some cases. In addition, there is a problem that the labor and time required for correcting the test pattern data and the expected value mask data used for the integrated circuit tester thereafter are increased and may be enormous.

The present invention has been made to solve the above-mentioned conventional problems, and reduces the labor and time required for creating test pattern data and expected value mask data used for an integrated circuit tester and for testing these data themselves. It is an object of the present invention to provide an integrated circuit test data generation method and apparatus capable of performing the above.

[0021]

First, an integrated circuit test data creating method according to a first aspect of the present invention creates data used in an integrated circuit tester for testing the product operation of an integrated circuit while providing a tester test pattern. In the method of creating data for an integrated circuit test, a circuit built in the integrated circuit to be tested is simulated while giving a test pattern for simulation, and a logic simulation for testing the validity of the circuit is performed. When the target circuit is determined to be valid by the logic simulation, based on the data of the test pattern for simulation, data of a test pattern for a tester used for the integrated circuit tester is generated, and the test pattern for simulation is generated. Of delay test result of test result using The standard-value delay execution result and the maximum-value delay execution result are compared with each other to create tester expected value mask data used for the integrated circuit tester, and the tester test pattern data and the tester expected value mask data are used. Is provided to a product operation test of an integrated circuit by the integrated circuit tester, thereby solving the above-mentioned problem.

Next, an integrated circuit test data creating apparatus according to a second aspect of the present invention provides an integrated circuit for creating data used in an integrated circuit tester for testing the product operation of an integrated circuit while providing a tester test pattern. A test for generating data of a test pattern for a tester used in the integrated circuit tester based on data of a test pattern for a simulation used in a logic simulator for simulating the functional operation of the integrated circuit in the test data creating device. A pattern conversion means for comparing a minimum value delay execution result, a standard value delay execution result, and a maximum value delay execution result of a test result using the simulation test pattern with each other, for a tester used in the integrated circuit tester; And expected value mask means for creating expected value mask data. It is obtained by solving the above problems.

Hereinafter, the operation of the present invention will be briefly described.

FIG. 2 is a flowchart for explaining the operation of the present invention.

In the present invention, the logic simulator 15
Make the most of the execution result of 0. From the logic simulator 150, as the execution result, the Min delay execution result, T
Since the yp delay execution result and the Max delay execution result are obtained, these are used as the execution result files 154A to 154C.

The expected value masking unit 155 checks the Min delay execution result of the execution result file 154A, the Type delay execution result of the execution result file 154B, and the Max delay execution result of the execution result file 154C with each other.
Tester expected value mask data used for the integrated circuit tester 174 is created and stored in the tester pattern 158. The tester pattern 158 stores a tester test pattern used for the integrated circuit tester 174.

As described above, according to the present invention, the test pattern data for the tester and the expected value mask data for the tester can be automatically created and provided for the product operation test of the integrated circuit by the integrated circuit tester 174. In particular, the tester expected value mask data can be provided only with information on the logic designer side.

In the case where mask data is used, the masked portion does not matter if there is a problem in the execution result, for example, the reference numeral 164 described above. Therefore, there is no enormous amount of labor and time to deal with such a case where the execution results do not match. Or less.

As described above, according to the present invention, it is possible to reduce the labor and time required for creating test pattern data and expected value mask data used for an integrated circuit tester and for testing them.

In the present invention, for example, in FIG. 2, the expected value mask means 170 and the tester pattern 172 shown in FIG. 1 may be provided. However, by applying the present invention, the determination of the problem with the reference numeral 164 is considerably reduced, so that the expected value masking means 170 and the tester pattern 172 are usually unnecessary.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 3 is a block diagram showing a configuration of various devices for testing an integrated circuit in an embodiment including an integrated circuit test data generating device to which the present invention is applied.
FIG. 4 is a flowchart showing an integrated circuit test data generating method to which the present invention is applied in the integrated circuit test data generating apparatus.

In the present embodiment, an expected value mask means 155 which is not provided in the past is newly provided. In this embodiment, the test pattern conversion means 156 and the expected value mask means 155 constitute an integrated circuit test data creation device corresponding to the first invention.

When there is no problem in the functional operation in the simulation with the logic simulator 150, the expected value masking means 155 obtains the Min delay execution result, Typ obtained by the logic simulator 150 and stored in the execution result file 154. The delayed execution result and the Max delayed execution result are used. In the expected value masking unit 155, the Min delay execution result, the Type delay execution result, and M
The ax delay execution results are collated with each other to generate tester expected value mask data used for the integrated circuit tester.
Also, based on the inconsistency found by cross-matching,
The corresponding unmatched part is set to “X” (don't care treatment: undefined value treatment), and an expected value mask is created. The part where the expected value mask is set to “X” is the logical simulator 16
In the logic simulation of No. 2 and in the integrated circuit test of the integrated circuit tester 174, good or bad execution results are not considered, and are excluded from the test target.

The operation of the present embodiment will be described below with reference to the flowchart of FIG.

In FIG. 4, first, in step 112, while giving a test pattern for simulation,
A circuit built in the integrated circuit to be tested is simulated, a logic simulation for testing the validity of the circuit is performed by the logic simulator 150 in FIG. 3, and data of the execution result files 154A to 154C is obtained. The data of the execution result first includes the simulation test pattern used for the execution. In addition, as the data, usually, a Min delay execution result, a Type delay execution result,
Also, information of three types of execution results, called Max delayed execution results, is included. Also, data on expected values, such as expected value mask data, is included.

Next, in step 114, tester test pattern data used for the integrated circuit tester 174 is generated based on the simulation test patterns stored in the execution result files 154A to 154C. The generation is performed by the data conversion processing unit 156 to convert the test pattern for simulation of the Type delay execution result in the execution result file 154B into the test pattern data 158 for tester.

In step 130, the processing of the expected value masking means 155 is performed. This is the result of the Min delayed execution of the execution result file 154A, the execution result file 1
The type delay execution result of the 54B and the Max delay execution result of the execution result file 154C are compared with each other to generate tester expected value mask data to be used for the integrated circuit tester 174, and to store the data in the tester pattern 158. It is. Based on the unmatched portion found by the cross-matching, the corresponding mismatched portion is set to “X” (don't care treatment: undefined value treatment), and an expected value mask is created.

Steps 112 to 130 are performed by the logic designer. On the other hand, steps after step 116 are performed on the semiconductor vendor side.

In step 116, the functional operation of the circuit to be built in the integrated circuit is reconfirmed, and the tester pattern data 1
To reconfirm the validity of the test pattern for the tester at 58, a logic simulator 162 on the semiconductor vendor side
The logic simulation is performed again. Expected value masking means 1
The part where the expected value mask is set to “X” by 55 is
In the logic simulation of step 116,
Regardless of the execution result of the defect, it is excluded from the test target.

At step 118, execution result confirmation means 1
At 66, it is determined whether the execution result of step 116 matches the execution result of step 112 described above. If it is determined that they match, the tester test pattern of the tester pattern data 158 is adopted as the tester test pattern of the integrated circuit tester 174. On the other hand, if it is determined that they do not match, the reason is investigated, and the simulation test pattern is partially corrected to be a tester test pattern. Alternatively, in step 120, the expected value masking means 170 sets or corrects the expected value mask of the tester pattern data 158.

Subsequently, in step 122, an integrated circuit test is actually performed by the integrated circuit tester 174. The portion where the expected value mask is set to “X” by the expected value masking unit 155 is excluded from the test target irrespective of the good / bad execution result in the integrated circuit test in step 122.

As described above, in the present embodiment, the present invention can be effectively applied. Therefore, it is possible to reduce the labor and time required for creating test pattern data and expected value mask data used for the integrated circuit tester and for testing them.

Here, as a modification, the processing of the expected value masking means 155 is performed by modifying the expected value mask of the data of the tester pattern 158 created by the test pattern converting means 156 as a means for correcting the already set mask. It is assumed that the data is to be rewritten. After the data conversion processing in step 114, the expected value masking means 155 in step 130 is executed.
May be performed. Alternatively, if there is already an area in the execution result files 154A to 154C for writing the mask data, the expected value masking unit 155 rewrites the expected value mask data of the data in the execution result files 154A to 154C. The data conversion processing of step 114 may be performed after the processing of the expected value masking means 155. The present invention does not limit the processing procedure related to the expected value masking means 155.

In FIG. 3, the test pattern conversion means 156 and the expected value mask means 155 are configured to directly write in the tester pattern 158 on the integrated circuit tester side. However, the test pattern conversion means 156 and the expected value mask means 155 once write data to a file on the CAD computer side, and write the contents of the file to the tester pattern 158 online or offline. May be written indirectly to the use pattern 158.

[0046]

According to the present invention, it is possible to reduce the labor and time required for creating test pattern data and expected value mask data used for an integrated circuit tester and for testing them.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a procedure for creating integrated circuit test data in the related art.

FIG. 2 is a flowchart for explaining the operation of the present invention.

FIG. 3 is a block diagram showing the configuration of various devices for testing an integrated circuit in an embodiment including an integrated circuit test data creation device to which the present invention is applied;

FIG. 4 is a flowchart showing an integrated circuit test data generation method to which the present invention is applied in the embodiment.

[Explanation of symbols]

 150, 162 ... Logic simulator 154, 154A-C ... Execution result file 156 ... Test pattern conversion means 158 ... Patter data for tester 166 ... Execution result confirmation means 155, 170 ... Expected value mask means 174 ... Integrated circuit tester

Claims (2)

[Claims] An integrated circuit test data creating method for creating data used for an integrated circuit tester for testing a product operation of an integrated circuit while providing a test pattern for a tester. A circuit built in the target integrated circuit is simulated, a logic simulation for testing the validity of the circuit is performed, and if the target circuit is determined to be valid by the logic simulation, the simulation test is performed. Based on the pattern data, tester test pattern data used for the integrated circuit tester is generated, and a minimum value delay execution result, a standard value delay execution result, and a maximum value of test results using the simulation test pattern are generated. The value delay execution results are compared with each other and the A tester expected value mask data used for a road tester, and providing the tester test pattern data and the tester expected value mask data to a product operation test of an integrated circuit by the integrated circuit tester. Characteristic method for creating integrated circuit test data. 2. An integrated circuit test data creating apparatus for creating data used in an integrated circuit tester for testing a product operation of an integrated circuit while providing a test pattern for a tester, wherein a functional operation of the integrated circuit is simulated. Test pattern conversion means for generating tester test pattern data used in the integrated circuit tester based on simulation test pattern data used in a logic simulator to be tested, and a test result using the simulation test pattern Expected value mask means for generating tester expected value mask data to be used for the integrated circuit tester by mutually comparing the minimum value delay execution result, the standard value delay execution result, and the maximum value delay execution result. An integrated circuit test data creation device, characterized in that: