TWM662198U - Integrated Circuit Design Verification System - Google Patents

Abstract

An integrated circuit design verification system has a verification platform and a control unit coupled to the verification platform, the control unit comprising: a file review unit for performing a content review operation on a register description file to generate a register description file that has completed the content review; a code file generation unit coupled to the file review unit for automatically generating a register verification code file according to the register description file that has completed the content review; a test case generation unit coupled to the file review unit for automatically generating a test case file according to the register description file that has completed the content review; and a RAL (register abstraction layer) model generation unit coupled to the code file generation unit for automatically generating a RAL model according to the register verification code file.

Description

Integrated Circuit Design Verification System

This work is related to the technical field of integrated circuit design verification, especially an integrated circuit design verification system.

As the functional requirements for integrated circuit chips in consumer electronics and automotive electronics continue to increase, the scale of circuit integration contained in integrated circuit chips is getting larger and larger, resulting in higher and higher circuit complexity. Therefore, as the scale of circuit integration becomes larger and larger, an integrated circuit chip usually contains multiple circuit modules, which are designed by different engineers. Electronic engineers who are familiar with the design and development of integrated circuit chips should know that the project development of an integrated circuit chip includes the following stages: product planning stage, design and simulation verification stage, design flow stage, and chip manufacturing and testing stage. In the design and simulation verification stage, engineers first use Verilog to complete the RTL circuit design (i.e., RTL coding) of the circuit module they are responsible for designing, and then use an integrated circuit design verification system to perform simulation verification to check the correctness of the RTL coding.

Specifically, an integrated circuit chip includes a plurality of registers that serve as the interactive interface between a plurality of circuit modules. Therefore, when performing simulation verification on a specific circuit module, it is usually performed by: (1) confirming the current state of the circuit module under test (DUT) by reading the current value of the register; and/or (2) configuring the register so that the circuit module under test works in a certain mode. Therefore, in a single simulation verification process, one or more registers must be read and written multiple times.

At present, the existing technology has realized the automation of register verification. For example, there is currently a register automation verification method that can reduce the workload of verification engineers to a certain extent. In the known register automation verification method, the user (i.e., system engineer) is responsible for filling out an Excel document of a register description file, and then using a code file to generate a script to generate a register verification code file (.ralf) based on the register description file, and then generating a RAL model (.sv) based on the register verification code file, and finally the verification platform (test bench) performs simulation verification on a specific circuit module through the RAL model. However, practical experience shows that since the register description file is filled out by the system engineer, it is inevitable that the register description file will contain erroneous content.

For example, the data width and address range of a register are 8 bits and 16 bits respectively, but when the system engineer fills in the description file of the register, he fills in the wrong value of the data width or address range. For another example, in practice, a single register can be divided into multiple register domains, and different domains often represent a certain independent function, such as: WO (write-only), RO (read-only), RW (read and write), or Reserved. Therefore, when filling in the bit header and bit tail (i.e., the start bit and the end bit) of each domain, it is also very easy to make human errors, such as filling in discontinuously.

It is easy to imagine that if there is a requirement to group thousands of registers into a register module, the system engineer will inevitably encounter a lot of errors after editing the register description file of the register module. In this case, even if the code file generation script can still successfully generate a register verification code file (.ralf) based on the register description file, the register verification code file is obviously not correct, resulting in the RAL model generated in the end not 100% corresponding to the hardware registers contained in the integrated circuit under test (DUT). In this case, whether the result of the simulation verification is pass or fail is meaningless.

From the above description, it can be seen that a new register verification code file generation solution is urgently needed in the field.

The main purpose of this invention is to provide a register verification code file generation solution, which is applied to an integrated circuit design verification system including a verification platform and a control unit. When the verification solution of this invention is applied, it is possible to automatically check whether the content of the register description file (such as Excel) is correct before generating the register verification code file, and when there are partial filling errors in the Excel content, the correct register verification code file and test case are automatically generated. Subsequently, after generating a RAL model (.sv) based on the register verification code file, the control unit uses the RAL model, the test case file and the verification platform to complete the simulation verification of a circuit module under test (DUT).

To achieve the above-mentioned purpose, an integrated circuit design verification system is proposed, which has a verification platform and a control unit coupled to the verification platform, the control unit comprising: A file review unit, used to perform a content review operation on a register description file to generate a register description file that has completed the content review; A code file generation unit, coupled to the file review unit, used to automatically generate a register verification code file according to the register description file that has completed the content review; A test case generation unit, coupled to the file review unit, used to automatically generate a test case file according to the register description file that has completed the content review; and A RAL (register abstraction layer; register abstraction layer) model generation unit, coupled to the code file generation unit, used to automatically generate a RAL model according to the register verification code file.

In one embodiment, the control unit transmits the RAL model and the test case file to the verification platform to execute a circuit module verification operation on the verification platform.

In one embodiment, the register description file records basic parameters of a plurality of registers according to a plurality of entry fields, and the entry fields include an identifier field.

In one embodiment, the control unit checks whether the bit width, byte number, word number and field bit range of the register are recorded correctly according to the content of the identification word field, thereby generating a check record.

In one embodiment, the inspection log is used to record at least one error message contained in the register description file.

In one embodiment, the content of the register verification code file includes: A register code for defining a plurality of registers and their corresponding bit widths; A register domain code for defining a plurality of register domains and their corresponding functions; An address code for defining the address, access attributes and common bus of each of the registers; A register module code for defining a register module including a plurality of the registers; and A storage unit code for defining a storage unit.

In one embodiment, the content of the test case file includes: a test sequence code, a sequencer code and a universal bus driver code.

In order to enable the review committee to further understand the structure, features, purpose, and advantages of this creation, the following are attached with diagrams and detailed descriptions of the preferred specific implementation examples.

FIG1 shows a block diagram of an integrated circuit design verification system to which the present invention is applied. As shown in FIG1 , in the design simulation verification stage of an integrated circuit chip, an integrated circuit design verification system 1 including a control unit 12 and a verification platform 11 is constructed to perform simulation verification on an integrated circuit (e.g., an RTL circuit completed using Verilog). When performing simulation verification, the control unit 12 performs a verification operation to perform verification testing on an integrated circuit including a plurality of circuit modules. To explain in more detail, the verification operation includes: a code file generation program, a RAL (register abstraction layer) model generation program and a circuit module verification program, wherein the control unit 12 completes the code file generation program by executing a register verification code file generation scheme of the present invention, thereby generating a register verification code file and a test case file.

FIG2 shows a flow chart of a register verification code file generation solution of the present invention. As shown in FIG1 and FIG2, the flow of the register verification code file generation solution of the present invention is to execute step S1: obtain a register description file. And, then execute step S2: after performing a content review operation on the register description file, generate a register verification code file (.ralf) according to the register description file. In one embodiment, the control unit 12 is provided with a file review unit 121 including a content review script. In this way, the control unit 12 can activate the content review script to automatically perform the content review operation.

Verification engineers should know that the register description file is filled in by system engineers, also known as a register list, usually an Excel or CVS file. In particular, the present invention organizes the storage path of the register description file in a text file (such as .txt) to generate a file path file. In this way, when executing step S1, the control unit 12 obtains an access path of the register description file by reading the file path file, and thereby obtains the register description file through the access path. The advantage of doing this is that when the access path of the register description file is changed, only the txt file needs to be modified, and there is no need to modify the content viewing script.

Usually, the register description file (Excel) includes multiple item fields such as register name, address, register bit width (such as 8bit, 16bit, 32bit), register domain, bit range of register domain, function of register domain, etc. When filling in the basic parameters of each register, the system engineer fills in each item field one by one. In particular, the present invention allows the multiple item fields to further include an identifier field, and the identifier field records an identifier used to describe the bit width of the register. For example, the identifier "word" indicates that the bit width of the register is 32bit, and the identifier "byte" indicates that the bit width of the register is 8bit. Users can define the identifiers they are used to. With such a design, when executing the content inspection operation, the control unit 12 checks the register bit width, byte number, word number and field bit range according to the identification word to see if they are recorded correctly.

Specifically, the control unit 12 calculates whether the number of bytes/words is consistent based on the bit range of the register and the identification word, that is, the bit range is divided by the bit width to confirm whether the operation result is equal to the number of bytes/words filled in the table. In addition, the content inspection also includes checking whether the bit range of the register field is continuous. For example, for a register with an 8-bit width and three register fields, the three register fields can be configured to have bit ranges of [5:0], [6:6] and [7:7] respectively when the table is filled normally. Therefore, specifically, the bit range of the register field can be checked to see whether the bit tail of the previous row and the bit head of the next row in the table are continuous. After the content review operation is completed, a review log is generated after the content review operation, and the review log records at least one error message contained in the register description file. For example, if the review process finds that the sum of the bit ranges of the three register fields exceeds the bit width of the register, this error message will be recorded in the log file. For another example, if the review process finds that the head and tail of the bit ranges of the three register fields are continuous, this error message will also be recorded in the log file.

In one embodiment, the control unit 12 is provided with a code file generation unit 122 including a code file generation script. With such a configuration, the control unit 12 can enable the code file generation script to generate a register verification code file according to the register description file. In this process, for each register including multiple register domains, the control unit 12 will automatically calculate the bit header and bit tail (i.e., the start bit and the end bit) of each register domain contained therein according to the bit width of the register. Specifically, when the number of bytes/words is greater than 1, it can be known that the register includes multiple register domains. At this time, if it is found in the previous content check process that the bit range of some register domains is filled in incorrectly, the incorrect ones are replaced with the automatically calculated correct start bit and/or end bit. Finally, after completing the content modification of the register description file, the control unit 12 generates a register verification code file according to the register description file.

It is worth noting that the generated register verification code file contains hierarchical structure codes; specifically, it includes: register module code, register code, address code, register field code, and storage unit code. Among them, the register code is used to define a plurality of registers (uvm_reg) and their corresponding bit widths, the register field code is used to define a plurality of register fields (uvm_reg_field) and their corresponding functions, the address code is used to define the address, access attributes and universal bus of each of the registers, the register module code is used to define a register module (uvm_reg_blcok) containing a plurality of the registers, and the storage unit code is used to define a storage unit (uvm_mem).

As shown in FIG. 1 and FIG. 2 , after completing the content review of the register description file (Excel) and generating a register verification code file (.ralf), the process of the register verification code file generation solution of the present invention can then execute step S3: adjusting a test case template file into a test case file according to the register description file. In one embodiment, the control unit 12 is provided with a test case generation unit 123 including a test case file generation script. In this way, the control unit 12 can activate the test case file generation script to adjust a test case template file into a test case file according to the register description file. The advantage of doing this is that when the test case file is run to generate the script, it can automatically refer to the correct register description file (Excel), and then generate the test case file corresponding to each register module (uvm_reg_blcok) according to the pre-written test case template.

In other words, after the system engineer changes the register description file (Excel), the file review unit 121 automatically checks the correctness of its content, the code file generation unit 122 automatically generates a register verification code file (.ralf) based on the register description file that has completed the content review, and the test case generation unit 123 also automatically generates a test case file based on the register description file that has completed the content review. The entire process does not require the intervention of the verification engineer, thereby greatly reducing the workload of the verification engineer and improving the simulation verification efficiency of the chip's integrated circuit. On the other hand, when the content of the test case needs to be modified in the later project, only the test case template file needs to be modified, and the update of all test case files can be realized by running the test case file generation script.

After completing the code file generation procedure, the verification process then enters a RAL model generation procedure and a circuit module verification procedure. In one embodiment, the control unit 12 is provided with a RAL model generation unit 124 including a RAL model generation script. In this configuration, in the RAL model generation procedure, the control unit 12 runs the RAL model generation script, thereby automatically generating a RAL model (.sv) based on the register verification code file (.ralf). Finally, in the circuit module verification procedure, the control unit 12 uses the RAL model, the test case file and the verification platform to complete the simulation verification of at least one of the circuit modules.

As can be seen from the above, this invention discloses an integrated circuit design verification system, which has a verification platform and a control unit coupled to the verification platform, the control unit comprising: a file review unit, used to perform a content review operation on a register description file to generate a register description file that has completed the content review; a code file generation unit, coupled to the file review unit, used to automatically generate a register verification code file according to the register description file that has completed the content review; a test case generation unit, coupled to the file review unit, used to automatically generate a test case file according to the register description file that has completed the content review; and a RAL (register abstraction layer; register abstraction layer) model generation unit, coupled to the code file generation unit, used to automatically generate a RAL model according to the register verification code file.

In addition, during operation, the control unit is used to transmit the RAL model and the test case file to the verification platform to perform a circuit module verification operation on the verification platform.

Thus, the above has completely and clearly explained the integrated circuit design verification system of this creation; and, from the above, it can be known that this creation has the following advantages:

This invention provides an integrated circuit design verification system, which includes a verification platform and a control unit; its feature is that the control unit executes a verification operation to perform simulation verification on an integrated circuit including a plurality of circuit modules; the verification operation includes: the register verification code file generation program of this invention as mentioned above, a RAL model generation program and a circuit module verification program, thereby greatly reducing the workload of verification engineers and improving the simulation verification efficiency of integrated circuits.

It must be emphasized that the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that its purpose, means and effects are all different from the known technology, and its creation is the first to be practical, which indeed meets the patent requirements of a new model. We sincerely ask the review committee to examine it carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

1: Integrated circuit design verification system

11: Verification platform

12: Control unit

121: Document viewing unit

122: Code file generation unit

123: Test case generation unit

124: RAL model generation unit

S1: Get a register description file

S2: After performing a content review operation on the register description file, a register verification code file is generated based on the register description file

S3: Adjust a test case template file into a test case file based on the register description file

FIG1 is a block diagram of an integrated circuit design verification system using a register verification code file generation method of the present invention; and FIG2 is a flow chart of a register verification code file generation method of the present invention.

1: Integrated circuit design verification system

11: Verification platform

12: Control unit

121: Document viewing unit

122: Code file generation unit

123: Test case generation unit

124: RAL model generation unit

Claims (7)

An integrated circuit design verification system has a verification platform and a control unit coupled to the verification platform, the control unit comprising: a file review unit for performing a content review operation on a register description file to generate a register description file that has completed the content review; a code file generation unit coupled to the file review unit for automatically generating a register verification code file according to the register description file that has completed the content review; a test case generation unit coupled to the file review unit for automatically generating a test case file according to the register description file that has completed the content review; and a RAL (register abstraction layer) model generation unit coupled to the code file generation unit for automatically generating a RAL model according to the register verification code file. An integrated circuit design verification system as described in claim 1, wherein the control unit transmits the RAL model and the test case file to the verification platform to execute a circuit module verification operation on the verification platform. The integrated circuit design verification system as described in claim 1, wherein the register description file records basic parameters of a plurality of registers according to a plurality of item fields, and the item fields include an identification word field. The integrated circuit design verification system as described in claim 3, wherein the control unit checks whether the bit width, byte number, word number and field bit range of the register are recorded correctly based on the content of the identification word field, thereby generating a review record. The integrated circuit design verification system as described in claim 4, wherein the review record is used to record at least one error message contained in the register description file. The integrated circuit design verification system as described in claim 1, wherein the content of the register verification code file includes: A register code for defining a plurality of registers and their corresponding bit widths; A register domain code for defining a plurality of register domains and their corresponding functions; An address code for defining the address, access attributes and common bus of each of the registers; A register module code for defining a register module including a plurality of the registers; and A storage unit code for defining a storage unit. The integrated circuit design verification system as described in claim 1, wherein the content of the test case file includes: a test sequence code, a sequencer code and a universal bus driver code.

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