JPH051649B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit suitable for an integrated circuit constructed of insulated gate field effect transistors.

[Background of the invention]

In differential amplifier circuits using insulated gate field effect transistors, improvements in semiconductor processing precision have made it possible to reduce the gate width, thereby enabling high-speed operation and increasing the degree of integration.

However, as the gate width becomes narrower, the Early effect in which the transistor and drain resistance values decrease becomes stronger, and there is a problem that the amplification factor at low frequencies decreases. When a differential amplifier circuit is used as an operational amplifier, a decrease in amplification factor causes an error in the calculation result, so a differential amplifier circuit with a high amplification factor is required.

One way to ensure an amplification factor even if the drain resistance of each transistor is small is to connect amplifier circuits in multiple stages. As one method, we considered a differential amplifier circuit consisting of a differential amplifier stage, a cascode stage, and a buffer stage. However, there is a problem in that the biasing method for the cascode stage transistors is complicated, so this will be explained.

An example of a conventional differential amplifier circuit using insulated gate field effect transistors is shown in FIG. In the figure, differential input transistors 1 and 2 are connected to load transistors 3 and 4. Transistors 5 and 6 are connected in cascode with transistors 1 and 2, and operate as a common gate amplifier circuit. Cascode stage output terminal 23 is connected to a buffer stage consisting of transistors 9 and 10. In such a conventional circuit, in order to stably operate the cascode stage transistors 5 and 6, the gate bias is determined as follows. That is, transistors 11 and 12 biased to have high resistance are connected to cascode stage output terminals 22 and 23, and the obtained in-phase signal component is detected by transistor 13 and compared with reference voltage 18. When the common mode signal voltage of the cascode stage output voltage is high, the current flowing through transistor 13 decreases, the output voltage of the current mirror circuit of transistors 14 and 15 increases, and the cascode stage output voltage biased with this voltage decreases. In this way, a bias circuit using negative feedback is provided so that the common mode signal voltage of the cascode stage becomes a desired voltage, and stability determined by the circuit itself is achieved.

However, in the bias circuit described above, poles and zero points may occur within the frequency band used, and in this case, the frequency characteristics and response waveform of the differential amplifier circuit deteriorate. In addition, the number of elements in the bias circuit is 6 transistors 11 to 16 in this example, and the bias voltage is 1.
Two types, 7 and 18, are required, and a lot of effort is required to design the above-mentioned poles and zeros so as not to occur.

[Purpose of the invention]

An object of the present invention is to provide a differential amplifier circuit with good characteristics that can generate a bias voltage for a cascode stage transistor with a simpler circuit configuration.

[Summary of the invention]

The present invention is characterized in that it adopts a method of applying a self-bias by connecting one of the cascode stage outputs to the gate electrode of the cascode transistor.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. Differential input transistors 1, 2 are connected to load transistors 3, 4. transistor 5,
6 is connected in cascode with transistors 1 and 2,
Operates as a gate-grounded amplifier circuit. Cascode stage output terminal 25 is connected to a buffer stage consisting of transistors 9 and 10. The present invention is to use the terminal 24 among the cascode stage output terminals 24 and 25 as a gate bias for the transistors 5 and 6, and the transistor 5 becomes a self-bias circuit with its drain and gate connected. Drain,
Once the current flowing between the sources is determined, the voltage between the gate and source of the transistor 5 is determined. Therefore, if the differential signal voltage of the cascode stage input signal is sufficiently small, the source potentials of transistors 5 and 6 are approximately equal, and the same bias conditions can be obtained. However, the voltage amplification factors of the cascode stage and output stage are
Since it is about 40 dB, when changing the output voltage by several volts, the bias voltage between the gates and sources of transistors 5 and 6 differs by only about several tens of millivolts, which is sufficiently small. Therefore, the bias condition of transistor 6 is that transistor 5 is self-biased.
The conditions are almost the same. From the above, it can be seen that the self-bias voltage of transistor 5 biases transistor 6 under substantially the same conditions.

Transistors 1 and 2 if input signal is present
Since the gate voltage difference between the transistors 5 and 6 is amplified to generate a current difference between the transistors 5 and 6, the cascode stage outputs 24 and
5 to generate a voltage difference. The output stage transistors 9 and 10 further amplify the voltage change of the cascode stage output 25 and output it. As described above, a differential amplifier circuit with a high amplification factor can be obtained by a total of three stages: differential stage transistors 1 and 2, cascode stage transistors 5 and 6, and output stage transistors 9 and 10.

Next, the stability of the cascode stage self-bias will be explained.

In the differential amplifier circuit, the signal to be amplified is a differential signal, but since the bias voltage is a common mode voltage, it is sufficient to consider the case where there is no differential signal. The bias voltage needs to bias the cascode stage transistor to an active state even if the power supply voltage or temperature changes. When the common mode component voltage of the cascode stage output voltage increases for some reason, the gate bias voltage of transistors 5 and 6 increases, and negative feedback is applied to lower the cascode stage output voltage, so the function is not the same as the conventional example. There is also a point of stability determined by the circuit itself. Moreover, this negative feedback operates at the speed of the self-bias circuit of the transistor 5, so it is very fast, and the problem of unnecessary poles and zeros seen in the conventional example does not occur. Furthermore, since the bias point can be set by the sizes of the transistors 5, 6, 7, and 8 and the current values of the current sources 12 and 13, the design is extremely easy compared to the conventional example.

〔Effect of the invention〕

According to the present invention, a complicated negative feedback bias circuit for stable operation of the cascode stage is not required, and the circuit configuration is not only simplified, but also the problem of unnecessary poles and zeros is solved, and the differential This has the effect of facilitating the design of the amplifier circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional differential amplifier circuit, and FIG. 2 is a circuit diagram showing an embodiment of the differential amplifier circuit according to the present invention. 1-10... Insulated gate field effect transistor, 11-13... Bias current source, 24, 25
...Cascode stage output.

Claims (1)

[Claims] 1. A differential input stage consisting of a pair of input differential transistors each having a load connected to its drain, and a differential output of the differential input stage as its source input signal, and its output as its source input signal. and a cascode stage consisting of a pair of transistors, one of which is applied as a gate bias voltage. 2. The differential amplifier circuit according to claim 1, wherein the load is constituted by an active load transistor forming a current mirror. 3. The differential amplifier circuit according to claim 2, wherein each of the transistors is constructed of an insulated gate field effect transistor.