JP2018156699A - Semiconductor device, electronic component, and electronic device - Google Patents

Abstract

A memory having a data write-back function is provided. A semiconductor device having a data write circuit, a data read circuit, and a memory cell, wherein the data write circuit has a function of writing first data and correction data to the memory cell. have. The data reading circuit has a function of reading a first potential corresponding to the first data, a function of holding the first potential corresponding to the first data, and a function of reading a second potential corresponding to the correction data. and a function of writing back first data to the memory cell. [Selection drawing] Fig. 1

Description

  One embodiment of the present invention relates to a semiconductor device, an electronic component, and an electronic device.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

  Note that in this specification and the like, a semiconductor device refers to an element, a circuit, a device, or the like that can function by utilizing semiconductor characteristics. As an example, a semiconductor device such as a transistor or a diode is a semiconductor device. As another example, the circuit including a semiconductor element is a semiconductor device. As another example, a device including a circuit including a semiconductor element is a semiconductor device.

  With the development of information technology such as IoT (Internet of things) and AI (Artificial Intelligence), the amount of data handled has been increasing. In order for an electronic device to use information technology such as IoT and AI, a semiconductor device capable of storing a large amount of data is required. Furthermore, in order to use electronic devices comfortably, there is a demand for a semiconductor device capable of high-speed access such as reading and writing.

  The semiconductor device described in Patent Document 1 discloses a configuration in which multi-value data is stored by using the fact that the threshold voltage of a transistor differs according to the amount of charge accumulated in the floating node of the transistor in the memory cell. ing.

  The semiconductor device described in Patent Document 2 discloses a transistor (OS transistor) having a metal oxide in a semiconductor layer, which has a smaller S value than a Si transistor.

US Patent Application Publication No. 2012/0033488 JP2016-027701A

  The SRAM and DRAM, which are conventional semiconductor devices, lose their data when the power is turned off. Further, it is known that data stored in a DRAM decreases with time because information is stored by electric charge. Therefore, a rewrite process for periodically holding the memory is required. The DRAM destroys the data to be read when reading the data, and therefore needs to be written back again. Therefore, the DRAM has a problem that it takes time to write back data that is destroyed by data reading.

  In AI, a detection effect excellent in feature extraction can be obtained from various information (image, sound, big data, etc.) by machine learning. AI is processed by a neural network. In the neural network, a neuron that functions as a multilayer perceptron is used. As for a neuron, a product-sum operation process is known in which a sum of a plurality of inputs to which a weight coefficient is added is calculated. It has been studied to perform an operation with a weighting factor added with a small number of elements by processing neurons with analog data. However, analog memories that handle analog data have a problem that they are easily affected by time constants such as wiring resistance and parasitic capacitance.

  In view of the above problems, an object of one embodiment of the present invention is to provide a semiconductor device with a novel structure. Another object of one embodiment of the present invention is to provide a semiconductor device in which data that is destroyed by reading can be easily written back. Another object of one embodiment of the present invention is to provide a semiconductor device that can handle analog data without being affected by a time constant.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not disturb the existence of other problems. Other issues are issues not mentioned in this section, which are described in the following description. Problems not mentioned in this item can be derived from descriptions of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above-described description and / or other problems.

  One embodiment of the present invention is a semiconductor device including a data write circuit, a data read circuit, a memory cell, a data read line, and a data write line, the memory cell including a first transistor, a first transistor, 2 transistor, a third transistor, and a first node, and one of a source and a drain of the first transistor is electrically connected to a data write line, and a source or a source of the first transistor The other of the drains is electrically connected to the gate of the second transistor, and one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the second transistor, and the second transistor The other of the source and the drain of the transistor is electrically connected to the data read line, and the first node is the source or the source of the first transistor. The other side of the drain is connected to the gate of the second transistor, and the data writing circuit has a function of writing the first data and the correction data to the memory cell through the data writing line. The first transistor has a function of holding electric charge according to the first data or the correction data stored in the first node by being turned off, and the data reading circuit includes the third transistor Is turned on, the function of reading the first potential corresponding to the first data through the data readout line, the function of holding the first potential, the function of reading the second potential, 1 is a semiconductor device having a function of writing back one data to a memory cell through a data write line.

  In each of the above structures, the semiconductor device further includes a first switch, a second switch, and a third switch, and the data read circuit is electrically connected to the data read line via the first switch. The data write circuit is electrically connected to the data write line via the second switch, the data read circuit is electrically connected to the data write line via the third switch, and The second switch and the third switch are turned off, the first switch is turned on, and the data reading circuit has a function of reading and storing the first potential from the memory cell, and the first switch And the third switch is turned off, the second switch is turned on, and the data write circuit has a function of writing correction data into the memory cell, The third switch is turned off, the first switch is turned on, and the data read circuit has a function of reading the second potential from the memory cell, and the first switch and the second switch are turned off. It is preferable that the semiconductor device have a function of turning on the third switch, turning on the third switch, and writing the first data back to the memory cell.

  In each of the above structures, the semiconductor device is preferably characterized in that the data writing circuit includes a digital-analog conversion circuit.

  In each of the above structures, the semiconductor device is preferably characterized in that the data writing circuit includes a comparison circuit.

  In each of the above structures, the data read circuit includes a first source follower circuit, a second source follower circuit, a third source follower circuit, a capacitor, a second node, a third node, an input terminal, and a first The first source follower circuit includes a fourth transistor, and the second source follower circuit includes a fifth transistor, a sixth transistor, and a seventh transistor. The third source follower circuit includes a fifth transistor, an eighth transistor, a ninth transistor, and a tenth transistor, and an input terminal is connected via the first switch. The output terminal is electrically connected to the data write line via the third switch, and the input terminal is the source or drain of the fourth transistor. One of the source and drain of the tenth transistor and the gate of the sixth transistor are electrically connected, and the output terminal is connected to one of the source or drain of the fifth transistor and the sixth transistor. One of the source and the drain, one of the source and the drain of the eighth transistor, and one of the electrodes of the capacitor are electrically connected, and the other of the source and the drain of the sixth transistor is connected to the seventh transistor One of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the eighth transistor, and the other of the source and the drain of the ninth transistor is electrically connected to the source and the drain of the tenth transistor. The other is electrically connected to the gate of the eighth transistor, and the second node is connected to the gate of the eighth transistor. And the other of the source and the drain of the tenth transistor are connected to each other, and the third node is formed by connecting the output terminal and one of the electrodes of the capacitor element. The source follower circuit includes a function in which the first data is applied to the gate of the second transistor included in the memory cell, a function in which the first input is applied to the gate of the fourth transistor, and a first potential. Has a function applied to the input terminal, and the second source follower circuit has a function in which the third input is applied to the gate of the fifth transistor and the first potential is the sixth transistor. The third source follower circuit has a function that is applied to the gate of the fifth transistor, and a function that the second output is provided to the third node. Functions A semiconductor having a function in which the first potential held in the second node is applied to the gate of the eighth transistor and a function in which the third output is applied to the third node. An apparatus is preferred.

  In each of the above configurations, the data read circuit further includes a second output terminal and an analog-digital conversion circuit, and outputs the first data to the second output circuit via the analog-digital conversion circuit. A semiconductor device characterized by having:

In each of the above structures, the data reading circuit further includes a second output terminal and a comparison circuit, and has a function of outputting the first data to the second output circuit via the comparison circuit. The featured semiconductor device is preferred.

  In each of the above structures, the first transistor is preferably a semiconductor device including a metal oxide in a semiconductor layer.

  In each of the above structures, the semiconductor device is preferably a semiconductor device in which the first transistor including a metal oxide in a semiconductor layer includes a back gate.

  In each of the above structures, an electronic component including a lead electrically connected to the semiconductor device is preferable.

  In each of the above structures, an electronic device including a printed board on which electronic components are provided and a housing in which the printed board is stored is preferable.

  In the electronic apparatus including any one of the above semiconductor devices, the electronic apparatus includes a neural network, the neural network includes a plurality of neurons, and the neuron includes a semiconductor device, an amplifier circuit, and a feature. An extraction circuit and a determination output circuit; the amplifier circuit has a function of receiving a weighting factor of analog data from the semiconductor device; and the determination output circuit has a function of receiving a determination threshold of analog data from the semiconductor device. The electronic device characterized by having is preferable.

  One embodiment of the present invention can provide a semiconductor device with a novel structure. Alternatively, according to one embodiment of the present invention, a semiconductor device in which data to be destroyed by reading can be easily written back can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can handle analog data without being affected by a time constant can be provided.

  Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this item described in the following description. Effects not mentioned in this item can be derived from the description of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the above effects and / or other effects. Therefore, one embodiment of the present invention may not have the above-described effects depending on circumstances.

FIG. 10 is a block diagram illustrating a semiconductor device. FIG. 10 is a circuit diagram illustrating a semiconductor device. 6 is a timing chart illustrating a semiconductor device. FIG. 10 is a circuit diagram illustrating a semiconductor device. FIG. 10 is a block diagram illustrating a semiconductor device. FIG. 10 is a block diagram illustrating a semiconductor device. FIG. 10 is a block diagram illustrating a semiconductor device. FIG. 10 is a block diagram illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. The top view of a semiconductor wafer. 10A and 10B are a flowchart and a perspective schematic diagram illustrating an example of a manufacturing process of an electronic component. The figure explaining an electronic component. 10A and 10B each illustrate an electronic device.

(Embodiment 1)
In this embodiment, a novel semiconductor device capable of easily writing back data destroyed by data reading will be described with reference to FIGS.

  FIG. 1 is a circuit diagram for explaining the configuration of the semiconductor device 10.

  The semiconductor device 10 includes a memory cell 20, a data write circuit 28, a data read circuit 30, a switch S1, a switch S2, and a switch S3. The memory cell 20 includes a transistor 21, a transistor 22, a transistor 23, and a capacitor 24. The data writing circuit 28 preferably includes a digital / analog conversion circuit. The data read circuit 30 has an input terminal CDS1, an output terminal CDS2, and an output terminal CDS3. The data read circuit 30 will be described in detail with reference to FIG.

  The memory cell 20 is electrically connected to each wiring of a write selection line WWL, a read selection line RWL, a data write line WBL, a data read line RBL, a source line SL, and a common line COM. A signal or a voltage for controlling the operation of the memory cell is applied to each wiring.

  The switch S1 is electrically connected to the data read control line RDE. The switch S2 is electrically connected to the data write control line WE. The switch S3 is electrically connected to the data write back control line WBE. Transistors can be used as the switches S1 to S3. When a transistor is used, the data read control line RDE, the data write control line WE, and the data write back control line WBE are connected to the gates of the respective transistors, so that the on state and the off state of the switch are controlled. It is preferable.

  The write control line WWL is electrically connected to the gate of the transistor 21. The data write line WBL is electrically connected to one of the source and the drain of the transistor 21. The other of the source and the drain of the transistor 21 is electrically connected to the gate of the transistor 22, and the node FN is a node to which the other of the source and the drain of the transistor 21 and the gate of the transistor 22 are connected. The wiring BGEL is electrically connected to the second gate of the transistor 21. It is preferable that the gate and the second gate of the transistor 21 be arranged at a position sandwiching the semiconductor layer of the transistor. However, the wiring BGEL is not necessarily provided. In FIG. 2 and subsequent figures, the wiring BGEL is not shown, but can be provided as necessary.

  The read control line RWL is electrically connected to the gate of the transistor 23. One of the source and the drain of the transistor 23 is electrically connected to the source line SL. The other of the source and the drain of the transistor 23 is electrically connected to one of the source and the drain of the transistor 22. The data read line RBL is electrically connected to the other of the source and the drain of the transistor 22. The node FN is electrically connected to one of the electrodes of the capacitor 24, and the other electrode of the capacitor is electrically connected to the common line COM.

  The input of the data writing circuit 28 is electrically connected to the signal line DIN. The output of the data write circuit 28 is electrically connected to the data write line WBL via the switch S2. The data write line WBL is electrically connected to the output terminal CDS2 of the data read circuit 30 through the switch S3. The data read line RBL is electrically connected to the input terminal CDS1 of the data read circuit 30 via the switch S1.

  The data writing circuit 28 has a function of converting to analog data when digital data is supplied from the signal line DIN.

  The transistors 21 and 23 function as switches. The transistor 21 is controlled to be in an on state (conductive state) and in an off state (non-conductive state) by a signal supplied to the write control line WWL. The transistor 23 is controlled to be in an on state (conductive state) and in an off state (non-conductive state) by a signal supplied to the read control line RWL.

  Note that in FIG. 1, both the transistor 21 and the transistor 23 are illustrated as n-channel types. That is, the voltage applied to the gate is turned on at the H level and turned off at the L level. Note that the transistors 21 and 23 may be p-channel transistors. Control can be performed by inverting the signal applied to the write control line WWL and the read control line RWL.

  By turning off the transistor 21, the memory cell 20 can store data. The node FN holds charges corresponding to stored data. The transistor 21 is preferably a transistor with extremely small leakage current in the off state. An OS transistor having such characteristics is preferable.

  The OS transistor has a high upper limit of the voltage that can be applied between the source and drain or the voltage that can be applied between the source and gate. Therefore, since the OS transistor has an excellent breakdown voltage, the driving voltage can be increased. Further, the potential difference between the node FN and the data write line WBL can be increased. Therefore, the potential difference between the node FN and the data read line RBL can be increased. Therefore, a large voltage can be held in the node FN. That is, the OS transistor is effective for the node FN to hold multi-value data including digital data.

  Note that the transistor 23 may be a transistor having silicon in a semiconductor layer (Si transistor). The transistor 23 can increase the current flowing between the source and drain in the on state by using a Si transistor. Further, the transistor 23 using the Si transistor and the transistor 21 using the OS transistor described above can be stacked. With this structure, the transistors used in the memory cell 20 are arranged in the stacking direction, so that the area of the memory cell 20 can be reduced. At this time, the transistor arranged in the stacking direction may be arranged at a position where the transistor 21, the transistor 23, and a part of the transistor 21 overlap when viewed from above the film surface. Therefore, it is advantageous to realize the semiconductor device 10 having a large storage capacity.

  The transistor 22 may be a Si transistor. When the transistor 22 is a Si transistor, the transistor 21 and the transistor 22 can be stacked. Therefore, the area of the memory cell 20 can be reduced. Further, with the transistor 21 and the transistor 22 having a stacked structure, a capacitor can be added to the via forming the node FN. By increasing the capacitance of the node FN, the capacitor 24 can be reduced.

  The transistor 22 may be an OS transistor. It is known that the OS transistor has a smaller S value than the Si transistor. For example, the data writing circuit 28 can supply analog data to the node FN using a digital-analog conversion circuit. When the analog data given to the node FN is controlled in the saturation region of the transistor 22, the analog data can be easily controlled by the gate-source voltage of the transistor 22 if the S value of the transistor 22 is small.

  Next, a procedure for writing analog data to the memory cell 20 will be described. When an H signal is applied to the data write control line WE and an H signal is further applied to the write control line WWL, the memory cell 20 receives analog data (hereinafter referred to as Vdata) from the DIN via the data write circuit 28. ) Can be stored.

  Vdata stored in the memory cell 20 is supplied from the data write circuit 28 to the node FN via the switch S2. Vdata is preferably given as a voltage. Therefore, the charge corresponding to Vdata is held in the capacitor of the node FN in the node FN. Although FIG. 1 illustrates an example in which the capacitor 24 is connected to the node FN, a configuration in which the capacitor 24 is not provided may be employed. When the capacitor 24 is not provided, it is preferable that the leakage current in the off state of the transistor 21 is extremely small like the OS transistor. When the capacitor 24 is provided, data deterioration can be suppressed even if the leakage current of the transistor 21 is not as small as that of the OS transistor. For example, when a Si transistor is used for the transistor 21, it is preferable to provide the capacitor element 24.

  The transistor 21 is turned off by applying an L signal to the write control line WWL, and the node FN holds Vdata. The switch S2 is turned off by applying an L signal to the data write control line WE.

  Next, a novel semiconductor device 10 that can easily write back data destroyed by data reading will be described. The description will be divided into four periods.

  The first period will be described. In the fourth period, the data read circuit 30 can read Vdata from the memory cell 20. An H signal is applied to the data read control line RDE, and an H signal is applied to the read control line RWL. The data read circuit 30 can read Vdata of the memory cell 20. The transistor 23 is turned on, and a sufficient drain current can be supplied to the transistor 22.

  Therefore, the transistor 22 can output a first potential (hereinafter referred to as Vdata1) corresponding to the node FN to the data read line RBL. As will be described in detail with reference to FIG. 2, the transistor 22 and the transistor connected to the input terminal CDS1 of the readout circuit 30 form a first source follower circuit. Therefore, Vdata1 is lower than the potential of the node FN by the gate-source voltage of the transistor. At this time, the gate-source voltage of the transistor is preferably larger than a threshold voltage (Vth) which is an electrical characteristic of the transistor. Therefore, Vdata1 is applied to the input terminal CDS1 of the data read circuit 30 via the switch S1. The first source follower circuit will be described in detail with reference to the readout circuit 30 in FIG.

  The data read circuit 30 can store Vdata1. As will be described in detail with reference to FIG. 2, the read circuit 30 includes a third source follower circuit, and holds Vdata1 in the third source follower circuit. The source line SL is preferably supplied with the highest potential in the semiconductor device 10. Alternatively, it is preferably larger than the maximum voltage of data given to the node FN. The common line COM is preferably supplied with the smallest potential among the semiconductor devices. Alternatively, it is preferably smaller than the minimum voltage of data given to the node FN.

  The second period to the third period will be described. In the second period to the third period, not only electrical characteristics of the transistor 22 but also variations in wiring resistance, parasitic capacitance, and the like can be corrected. Here, the description will be made focusing on the threshold value of the transistor 22 as an electrical characteristic, but the correction is not limited to the threshold value. Variations in the wiring resistance of the memory cell 20 connected to the data read circuit 30 via the switch S1, the electrical characteristics of the switch S1, the parasitic capacitance of the data read line RBL, and the like can also be corrected.

  In the second period, an H signal is applied to the data write control line WE and an H signal is applied to the write control line WWL, and correction data (hereinafter referred to as Vref) can be stored in the memory cell 20. Vref stored in the memory cell 20 is applied from the data write circuit 28 to the node FN via the switch S2. Vref is preferably given as a voltage. Accordingly, in the node FN, a charge corresponding to Vref is held in the capacitor of the node FN.

  The transistor 21 is turned off by applying an L signal to the write control line WWL, and the node FN holds Vref. The switch S2 is turned off by applying an L signal to the data write control line WE.

  The third period will be described. In the third period, the data read circuit 30 can read Vref from the memory cell 20. An H signal is applied to the data read control line RDE, and an H signal is applied to the read control line RWL. The data read circuit 30 can read Vref of the memory cell 20. The transistor 23 is turned on, and the transistor 22 can output a second potential (hereinafter referred to as Vdata2) corresponding to the node FN to the data read line RBL.

  Similarly to the first period, Vdata2 becomes a potential lower than the potential of the node FN by the gate-source voltage of the transistor connected to the input terminal CDS1 of the reading circuit 30. Therefore, Vdata2 is applied to the input terminal CDS1 of the data read circuit 30 via the switch S1. The data read circuit 30 can calculate the difference between Vdata1 and Vdata2.

  Vdata1 and Vdata2 include variations in electrical characteristics of the transistor 22, variations in wiring resistance, parasitic capacitance, and the like. Therefore, by calculating the difference between Vdata1 and Vdata2, variations in electrical characteristics, variations in wiring resistance, parasitic capacitance, and the like can be corrected.

  Therefore, the data read circuit 30 can read Vdata2 from the memory cell 20.

  The fourth period will be described. In the fourth period, Vdata can be written back from the data read circuit 30 to the memory cell 20. The data to be written back can be output to the output terminal CDS2.

  Further, an H signal is applied to the data write control line WBE, and an H signal is applied to the write control line WWL. As a result, the data read circuit 30 can store Vdata1 in the node FN. Next, an L signal is supplied to the write control line WWL, so that the transistor 21 is turned off. Therefore, the node FN can hold Vdata1. Further, an L signal is applied to the data write control line WBE, and the switch S3 is turned off.

  FIG. 2 illustrates the data read circuit 30.

  The data read circuit 30 includes a first source follower circuit, a second source follower circuit, a third source follower circuit, and an output circuit.

  The data read circuit 30 includes an input terminal CDS1, an output terminal CDS2, an output terminal CDS3, a transistor 31, a transistor 32, a transistor 33, a transistor 34, a transistor 35, a transistor 36, a transistor 37, a transistor 39, a capacitor 38, a node FNSH, and a node. Vout, node SFout, power supply line Bias1, power supply line Bias2, power supply line VDD, power supply line Cds, signal line SH, signal line SF1EN, signal line SF2EN, signal line CL, and an analog-digital conversion circuit.

  The first source follower circuit includes a transistor 22 included in the memory cell 20 and a transistor 31. The second source follower circuit includes a transistor 32, a transistor 35, and a transistor 36. The third source follower circuit includes a transistor 32, a transistor 33, a transistor 34, and a transistor 37.

  The transistor 31, the transistor 34, the transistor 36, the transistor 37, and the transistor 39 are n-channel transistors. The transistors 32, 33, and 35 are p-channel transistors.

  The input terminal CDS1 is electrically connected to the data read line RBL via the switch S1. The output terminal CDS2 is electrically connected to the data write line WBL via the switch S3. In the input terminal CDS1, one of the source and the drain of the transistor 31, the one of the source and the drain of the transistor 37, and the gate of the transistor 35 are electrically connected. In the output terminal CDS2, one of the source and the drain of the transistor 32, one of the source and the drain of the transistor 33, one of the source and the drain of the transistor 35, and one of the electrodes of the capacitor 38 are electrically connected. Yes. The other of the source and the drain of the transistor 35 is electrically connected to one of the source and the drain of the transistor 36. The other of the source and the drain of the transistor 33 is electrically connected to one of the source and the drain of the transistor 34. The other of the source and the drain of the transistor 37 is electrically connected to the gate of the transistor 33. The other of the source and the drain of the transistor 31, the other of the source and the drain of the transistor 34, and the other of the source and the drain of the transistor 36 are electrically connected to a common line COM. The other electrode of the capacitor 38 is electrically connected to one of the source and drain of the transistor 39 and the input of the analog-digital conversion circuit 39a. The output of the analog-digital conversion circuit 39a is electrically connected to the output terminal CDS3.

  The gate of the transistor 31 is electrically connected to the power supply line Bias1. The gate of the transistor 32 is electrically connected to the power supply line Bias2. The other of the source and the drain of the transistor 32 is electrically connected to the power supply line VDD. The other of the source and the drain of the transistor 39 is electrically connected to the power supply line Cds. The gate of the transistor 37 is electrically connected to the signal line SH. The gate of the transistor 36 is electrically connected to the signal line SF1EN. The gate of the transistor 34 is electrically connected to the signal line SF2EN. The gate of the transistor 39 is electrically connected to the signal line CL.

  The power supply line Bias1 is given a potential of Vbias1. The power supply line Bias2 is given a potential of Vbias2. The power supply line VDD is given a potential of VDD. The power supply line Cds is given a potential of Vcds. The common line is given a potential of Vcom.

  The node FNSH is formed by connecting the gate of the transistor 33 and the other of the source and the drain of the transistor 37. The node Vout is formed by connecting the other electrode of the capacitor 38, one of the source and the drain of the transistor 39, and the analog-digital conversion circuit. The node SFout is formed by connecting the output terminal CDS2 and one of the electrodes of the capacitive element 38. The node FNSH may include a capacitor.

  Here, the first period to the fourth period will be described in detail.

  First, the first period will be described. The data read circuit 30 holds a read potential Vdata1 corresponding to the potential of Vdata held at the node FN at the node FNSH. For this purpose, it is preferable that the transistor 22 and the transistor 31 form a first source follower circuit based on the potential of Vcom. It is more preferable to apply a voltage slightly higher than the threshold voltage (Vth31) of the transistor 31 to the gate of the transistor 31.

  In addition, the transistor 22 and the transistor 31 preferably have the same L length, W length, electrical characteristics, and the like. The transistor 22 and the transistor 31 operate with saturation characteristics. Therefore, it is preferable that the transistor 22 and the transistor 31 have the same threshold voltage. From the above conditions, the first source follower circuit can be expressed by Equation 1.

  Vdata1 = Vdata−Vbias1 (Formula 1)

  Therefore, Vdata1 is applied to the input terminal CDS1.

  Subsequently, the transistor 37 is turned on by applying an H signal to the signal line SH. When the transistor 37 is turned on, the node FNSH can store Vdata1. At this time, an H signal is applied to the signal line CL, whereby the transistor 39 is turned on. When the transistor 39 is turned on, the node Vout becomes a potential of Vcds.

  Further, by applying an L signal to the signal line SF2EN, the transistor 34 is turned off. Further, the transistor 36 is turned on by applying a signal H to the signal line SF1EN. Therefore, the transistor 32 and the transistor 35 form a second source follower circuit based on the potential of VDD. At this time, the transistor 36 is in a conductive state. The transistor 32 and the transistor 35 preferably have the same L length, W length, electrical characteristics, and the like. A voltage applied to SFout is defined as VSFout. VSFout can be expressed by Equation 2.

  VSFout = (VDD−Vbias2) + Vdata1 (Formula 2)

  Expression 1 is substituted into Vdata1 of Expression 2. Therefore, Vbias2 given to the gate of the transistor 32 gives the potential of VDD-Vbias1, so that the node SFout becomes the potential of Vdata.

  Subsequently, by supplying an L signal to the signal line SH, the transistor 37 is turned off. Therefore, the node FNSH can hold Vdata1. Further, the transistor 39 is turned off by applying an L signal to the signal line CL. Therefore, the node Vout can hold Vcds. Since the node Vout is at the potential of Vcds, the node SFout temporarily holds the potential of Vdata with Vcds as the reference potential. When an OS transistor is used for the transistor 37, leakage of charges stored in the node FNSH can be reduced. Therefore, deterioration of data held in the node FNSH can be suppressed.

  The second period is a period for writing Vref to the node FN. The description here is omitted.

  In the third period, the data read circuit 30 reads Vref from the memory cell 20 in the same procedure as in the first period. Vref is converted into Vdata2 and read out in the same manner as in Expression 1. To read Vdata2, the first source follower circuit and the second source follower circuit are used. Therefore, the node SFout is updated with the potential of Vref. However, an L signal is continuously applied to the signal line SH. As a result, the node FNSH can continue to hold Vdata1 from the first and second periods.

  By updating the node SFout from Vdata to Vref, the node Vout is updated from Vcds to Vcds + Vref−Vdata due to capacitive coupling of the capacitive element 38. Therefore, the capacitor 38 holds a potential of Vcds + Vref−Vdata. Since Vref and Vdata are read out through the same path, variations in electrical characteristics, wiring resistance, parasitic capacitance, and the like of the transistor 22 included in both potentials are the same amount. Therefore, Vout = Vcds + Vref−Vdata is a potential in which the variation is corrected. By applying an appropriate reference voltage to the analog-digital conversion circuit 39a, digital data corresponding to Vdata is output to DOUT via the output terminal CDS3. That is, high-precision reading with reduced variations in transistor electrical characteristics, wiring resistance, parasitic capacitance, and the like is possible.

  In the fourth period, the data read circuit 30 writes Vdata back to the memory cell 20. By applying an L signal to the signal line SF1EN, the transistor 36 is turned off. Further, the transistor 34 is turned on by applying an H signal to the signal line SF2EN. Therefore, the transistor 32 and the transistor 33 form a third source follower circuit based on the potential of VDD. At this time, the transistor 34 is in a conductive state. The transistor 32 and the transistor 33 preferably have the same L length, W length, electrical characteristics, and the like.

  Since the potential of the node FNSH holds Vdata1, the potential of the node SFout is updated with Vdata. When the switch S3 is on and the transistor 21 is on, the potential of the node FN is updated by the potential of the node SFout. Further, a current can be supplied from the transistor 32 as the potential of the node SFout. Therefore, the node FN can suppress the influence of a voltage drop due to parasitic capacitances such as the data write line WBL and the switch S3. Therefore, deterioration of data can be suppressed when Vdata is written back to the node FN.

  Finally, the transistor 21 is turned off and the switch S3 is turned off to complete the data write-back.

  In the present embodiment, data is restored by writing back data that is destroyed when data is read from the memory cell 20. Therefore, it is possible to provide a semiconductor device that has good data retention characteristics and can suppress the influence of a time constant of a wiring or the like.

  FIG. 3 is a timing chart showing the operation of the semiconductor device 10 of FIG. T1-T3 is an initial state and will be described from T4. In addition, a description will be given from the state where the potential of Vdata is held in the node FN. The drive timing is not limited to the timing chart of FIG. The drive timing can be adjusted as appropriate.

  Start the first period.

  T4 turns on the switch S1 by applying an H signal to the signal line RDE.

  T5 reads Vdata from the memory cell 20 by applying an H signal to the read selection line RWL. In addition, the transistor 36, the transistor 37, and the transistor 39 are turned on by supplying a signal H to the signal line SH, the signal line SF1EN, and the signal line CL. Further, the transistor 36 is turned off by applying an L signal to the signal line SF2EN. Therefore, the reading circuit 30 can hold the read potential of Vdata1 in the node FNSH. At this time, the data read line has a potential of Vdata1. The node SFout has a potential of Vdata. The node Vout has a potential of Vcds. Note that the node FNSH has a potential of Vdata−Vbias1.

  T6 gives an L signal to the signal line SH. Therefore, the node FNSH holds the potential of Vdata−Vbias1.

  T7 gives an L signal to the signal line CL. Therefore, the node Vout holds the potential of Vcds.

  In T8, the transistor 23 is turned off by applying an L signal to the read selection line RWL. Further, an L signal is given to the signal line SF1EN. The node SFout has a potential of VDD because the signal line SF1EN and the signal line SF2EN are L.

  At T9, the switch S1 is turned off by applying an L signal to the signal line RDE. The first period ends.

  Next, the second period starts.

  T10 turns on the switch S2 by giving a signal H to the data write control line WE. Further, the data write circuit 28 outputs the potential of Vref when the correction data is given to the signal line DIN.

  In T11, the transistor 21 is turned on by applying an H signal to the write control line WWL. The potential of Vref is stored in the node FN.

  In T12, the transistor 21 is turned off by applying an L signal to the write control line WWL. As for the potential of Vref, electric charge corresponding to Vref is stored in the node FN.

  In T13, the switch S2 is turned off by giving an L signal to the data write control line WE. The second period ends.

  Next, the third period starts.

  T14 applies the H signal to the signal line RDE to turn on the switch S1.

  In T15, data is read from the memory cell 20 by applying a signal H to the read selection line RWL. At this time, the data read line RBL has a potential of Vdata2. The node SFout is updated to the potential of Vref. The node Vout holds the potential of Vcds + Vref−Vdata because the transistor 39 is off. The node FNSH holds the potential of Vdata−Vbias1 without being updated.

  Between T15 and T16, the analog-digital conversion circuit 39a converts the potential of the node Vout into digital data and outputs it to Dout. Next, at T16, the switch S1 is turned off by applying an L signal to the signal line RWL.

  T17 turns off the switch S1 by applying an L signal to the signal line RDE. The third period ends.

  Next, the fourth period starts.

  T18 applies the H signal to the signal line WBE to turn on the switch S3. Data write line WBL and node SFout are electrically connected via switch S3. By applying an L signal to the signal line SF1EN, the transistor 36 is turned off. By applying an H signal to the signal line SF2EN, the transistor 34 is turned on, and the third source follower circuit is operated. A potential of Vdata is applied to the node SFout, and a potential of Vcds is applied to the node Vout.

  In T19, the transistor 21 is turned on by applying an H signal to the write control line WWL. The potential of Vdata of the node SFout is stored in the node FN.

  T20 turns off the transistor 21 by applying an L signal to the write control line WWL. The node FN stores a charge corresponding to the Vdatan potential.

  T21 turns off the transistor 34 by applying an L signal to the signal line SF2EN. By applying an L signal to the signal line WBE, the switch S3 is turned off. The fourth period ends.

  FIG. 4 shows a circuit having a configuration different from the readout circuit 30 described in FIG. 2 as an example. The transistors 31, 32, 33, 35, 37, and 39 are n-channel transistors. The transistors 34 and 36 are p-channel transistors. Therefore, in FIG. 4, the second source follower circuit and the third source follower circuit operate with reference to the potential of Vcom.

  The semiconductor device 10 of FIG. 5 shows an example in which a register is configured by using a plurality of memory cells 20. The memory cell 20 has a register function capable of handling digital data and analog data. The difference from FIG. 1 is that a selection signal CS is provided to control the switch S1, the switch S2, and the switch S3. By having the selection signal CS, the data write circuit 28 and the data read circuit 30 can be shared. In FIG. 5, the source line SL is also provided with a wiring independently in accordance with the selection signal CS. However, the source line SL may be a common wiring.

  The semiconductor device 10 in FIG. 6 has a plurality of memory cells 20. The memory cells 20 are different in that they are arranged from MC (0, 0) to MC (m, n). When the memory cell 20 extends in the n direction, the data write line WBL, the data read line RBL, and the source line SL can be shared. Therefore, the memory cell 20 extending in the n direction can share the data read circuit 30. m and n are positive integers of 1 or more.

  The data read circuit 30 is preferably provided for each column. By simultaneously controlling the read control line RWL, data can be read in parallel from the memory cells 20 extending in the m direction. Furthermore, data can be written back in parallel.

  In FIG. 6, the data write circuit 28 can be controlled by the selection signal CS. In the second period, it is preferable that data can be written to the memory cells 20 processed in parallel with the same Vref. However, the data write circuit 28 may have a configuration for each column as in the data read circuit.

  The semiconductor device 10 can be configured to have a plurality of memory cells 20. By using the data reading circuit 30 shown in this embodiment mode, data destroyed by data reading can be easily written back. In the present embodiment, the data write circuit 28 has a digital-analog conversion circuit, and the data read circuit 30 has an analog-digital conversion circuit 39a, whereby the memory cell 20 can handle analog data. A comparison circuit may be used instead of the digital-analog conversion circuit and the analog-digital circuit. By using the comparison circuit, a configuration excellent in handling digital data can be obtained. When dealing with digital data, data degradation can be suppressed compared to when dealing with analog data.

  Note that one embodiment of the present invention is described in this embodiment. Alternatively, in another embodiment, one embodiment of the present invention is described. Note that one embodiment of the present invention is not limited thereto. That is, in this embodiment and other embodiments, various aspects of the invention are described, and thus one embodiment of the present invention is not limited to a particular aspect. For example, as an embodiment of the present invention, an example in which the present invention is applied to a semiconductor device having memory cells has been described; however, one embodiment of the present invention is not limited thereto. Depending on circumstances or circumstances, one embodiment of the present invention may not be applied to a semiconductor device including a memory cell. For example, one embodiment of the present invention may be applied to a semiconductor device having another function. For example, although an example in which a channel formation region, a source / drain region, and the like of a transistor include an oxide semiconductor is described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. Depending on circumstances or conditions, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, or the like may include various semiconductors. Depending on circumstances or conditions, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, or the like can be formed using, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium. At least one of arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included. Alternatively, for example, depending on circumstances or circumstances, a variety of transistors, channel formation regions of the transistors, source and drain regions of the transistors, and the like of the transistor may not include an oxide semiconductor. Good.

  The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 2)
In this embodiment, a structure in which an electronic device includes a neural network and the neural network includes the semiconductor device of Embodiment 1 will be described with reference to FIGS.

  The semiconductor device 10a shown in FIG. 7 is a schematic diagram of a neuron that can function as a multilayer perceptron in a neural network. The multilayer perceptron has a three-layer structure of an input layer, an intermediate layer, and an output layer, and information of the input layer can be output to the output layer by extracting or compressing information features.

  The neuron preferably has the following functions. A neuron has a plurality of input signals, and each input signal can be weighted. The neuron extracts features by adding a plurality of input signals to which weights are added. If the feature exceeds a specified threshold, it is determined that the feature is ignited and the output changes.

  Therefore, the neuron preferably includes an input signal, IN (0) to IN (n), an amplifier circuit 41, a feature extraction circuit 42, and a determination output circuit 43. The amplifier circuit 41 can apply a weight to the input signal. The feature extraction circuit 42 can add a plurality of input signals weighted by the amplification circuit 41. The total sum of the input signals can be determined by a determination threshold included in the determination output circuit 43. When the determined result exceeds the determination threshold value, it can be determined that ignition has occurred, and the output signal can be changed.

  Further detailed description will be given. The amplifier circuit 41 can add a weighting coefficient A to the input signal IN. The weight coefficient A is set in the memory cell MC. Here, the weighting factor A may be replaced with an amplification factor. Therefore, the data obtained by adding the weighting coefficient A to the input signal IN is given to the feature extraction circuit 42 as the output signal b. Further, an offset component may be added to the output signal b.

  Therefore, the output signal c of the feature extraction circuit 42 can be expressed by Equation 3. As the weighting factor A given to the amplifier circuit 41, the same weighting factor A may be set for all the input signals IN, or different weighting factors A may be set for the respective input signals IN.

  Under the above conditions, the feature extraction circuit 42 can express the total sum (net value) of the input signal IN by Expression 3. The output signal c (j) used here indicates the jth of a plurality of neurons. j is an integer of 1 or more. The sum is supplied to the determination output circuit 43 as an output signal c (j).

  c (j) = Σ (IN (i) · A (i) + B) (Formula 3)

  Therefore, the comparison circuit included in the determination output circuit 43 can be replaced with an output function. An output signal OUT (j) whose output function is a neuron is expressed by Expression 4.

  OUT (j) = f (c (j)) (Formula 4)

  It is known that the output function f uses a sigmoid function or the like as a neuron output function. In one embodiment of the present invention, the determination output circuit 43 can function as a neuron output function f. The determination output circuit 43 is preferably supplied with a threshold potential as a determination threshold value from the memory cell MC. However, a fixed threshold potential may be given as the determination threshold. Therefore, the decision output circuit 43 can be used to generate a condition called firing in the neural network and output a binarized digital signal as the output signal OUT (j).

  FIG. 8 shows a configuration in which the neuron weight coefficient A and the determination threshold are given by the semiconductor device of the first embodiment. In FIG. 8, the j-th neuron will be described as an example. The neuron shows an example in which an output signal OUT (j) is generated from four input signals IN (0) to IN (3).

  The neuron is determined by the memory cells MC (0) to MC (4), the data write circuit 28, the data read circuit 30, the switches S1 to S8, the amplifier circuits 41a to 41d, and the feature extraction circuit 42. Output circuit 43.

  Description of the memory cells MC (0) to MC (4), the data write circuit 28, the data read circuit 30, and the switches S1 to S3 has been described in Embodiment 1, and will be omitted hereinafter. Therefore, in FIG. 8, the switches S4 to S8, the amplifier circuits 41a to 41d, the feature extraction circuit 42, and the determination output circuit 43 will be described.

  Here, in order to simplify the description, the input signal IN (0) will be described. When the memory cell MC (0) is updated, the amplifier circuit 41a can update the weighting coefficient A by controlling the switch S4 with the signal SEL (0). Since the data read line RBL is connected as a common wiring to the memory cells MC (0) to MC (4), the weight coefficient A of the amplifier circuit 41a is updated after the memory cell MC (0) is updated. It is preferred that The amplifier circuit 41 is given an input signal IN (0).

  The amplifier circuit 41a adds a weight coefficient A to the input signal IN (0) and outputs an output signal b (0).

  The feature extraction circuit 42 calculates the sum of the input signals of the amplifier circuits 41a to 41d using Equation 3. The calculation result can be given to the determination output circuit 43 as a signal c (j).

  The determination output circuit 43 can compare with the determination threshold value when the signal c (j) is given. If it is determined that the comparison result is ignition, the determination result is binarized and H is output to the output signal OUT (j). Each neuron preferably has a different determination threshold. Therefore, it is preferable that the determination threshold is given from the memory cell MC (4). The determination threshold is preferably analog data.

  Therefore, it is preferable that the amplifier circuit 41 and the determination output circuit 43 can store analog data. Therefore, it is preferable that the amplifier circuit 41 and the determination output circuit 43 include the first source follower circuit to the third source follower circuit included in the reading circuit 30.

  As described above, it is preferable that neurons used in the neural network use analog data for the weighting factor A, the determination threshold value, and the like. By using the structure shown in this embodiment mode, analog data can be easily handled. Further, by assigning the selection signal CS, the weighting coefficient A, the determination threshold value, and the like can be controlled in units of neurons. Therefore, the control of the memory cell that stores the analog data can reduce the exclusive area of the circuit as compared with the neural network constituted by the digital circuit.

  The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 3)
In this embodiment, a cross-sectional structure of a semiconductor device is described. In this embodiment, a cross-sectional structure of a semiconductor device corresponding to the memory cell 20 illustrated in FIG. 1 is described.

  The memory cell 20 described with reference to FIG. 1 includes a transistor 21, a transistor 22, a transistor 23, and a capacitor 24 as illustrated in FIGS. 9, 11, and 12.

[Cross-section structure 1]
The semiconductor device illustrated in FIG. 9 includes a transistor 21, a transistor 22, a transistor 23, and a capacitor 24. The transistor 21 is provided above the transistors 22 and 23, and the capacitor 24 is provided above the transistor 21.

  The transistor 21 is a transistor (OS transistor) in which a channel is formed in a semiconductor layer including an oxide semiconductor. Although the description of the transistor 21 will be described later, by providing the OS transistor having the structure illustrated in FIG. 9, the transistor 21 can be formed with high yield even when miniaturized. By using such an OS transistor for a semiconductor device, miniaturization or high integration can be achieved. Since an OS transistor has a small off-state current, stored data can be held for a long time by using the OS transistor for a semiconductor device. In other words, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the semiconductor device can be sufficiently reduced.

  9 and 10, the data read line RBL is electrically connected to the source of the transistor 22, and the source line SL is electrically connected to the drain of the transistor 23. The data write line WBL is electrically connected to one of the source and the drain of the transistor 21, the write control line WWL is electrically connected to the first gate of the transistor 21, and the wiring BGEL is connected to the second gate of the transistor 21. It is electrically connected to the gate. The other of the gate of the transistor 22 and the other of the source and drain of the transistor 21 is electrically connected to one of the electrodes of the capacitor 24, and the other of the electrodes of the capacitor 24 is electrically connected to the common wiring COM. Yes. The read selection line RWL is electrically connected to the gate of the transistor 23.

  The transistor 22 and the transistor 23 are provided over a substrate 311, a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a functioning as a source region or a drain region, and It has a low resistance region 314b. Hereinafter, in order to simplify the description, the description will be given using the transistor 22.

  The transistor 22 may be either a p-channel type or an n-channel type.

  The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 22 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

  The low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or p-type conductivity such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.

  The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

  Note that the threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.

  Note that the transistor 22 illustrated in FIGS. 9A and 9B is an example, and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order so as to cover the transistor 22.

  As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.

  The insulator 322 may function as a planarization film that planarizes a step generated by the transistor 22 or the like provided below the insulator 322. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.

  The insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 22 into a region where the transistor 21 is provided.

  As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor such as the transistor 21 may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses diffusion of hydrogen between the transistor 21 and the transistor 22. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

The amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is 10 × 10 5 in terms of the amount of desorbed hydrogen atoms converted to hydrogen atoms per area of the insulator 324 in the range of 50 ° C. to 500 ° C. in TDS analysis. It may be ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

  Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 324 is preferably equal to or less than 0.7 times that of the insulator 326, and more preferably equal to or less than 0.6 times. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

  The insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitor 324, a conductor 328 that is electrically connected to the transistor 21, a conductor 330, or the like. Note that the conductor 328 and the conductor 330 function as plugs or wirings. In addition, a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures. In this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

  As a material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is formed in a single layer or a stacked layer. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Or it is preferable to form with low resistance conductive materials, such as aluminum and copper. Wiring resistance can be lowered by using a low-resistance conductive material.

  A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 9, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  For example, as the insulator 350, an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 22 and the transistor 21 can be separated by a barrier layer, and hydrogen diffusion from the transistor 22 to the transistor 21 can be suppressed.

  For example, tantalum nitride may be used as the conductor having a barrier property against hydrogen. In addition, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 22 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

  A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 9, an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked. Further, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 22 and the transistor 21 can be separated by a barrier layer, and hydrogen diffusion from the transistor 22 to the transistor 21 can be suppressed.

  A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 9, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 370. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 22 and the transistor 21 can be separated by a barrier layer, and hydrogen diffusion from the transistor 22 to the transistor 21 can be suppressed.

  A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 9, an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked. A conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 380. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 22 and the transistor 21 can be separated by a barrier layer, and hydrogen diffusion from the transistor 22 to the transistor 21 can be suppressed.

  An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked over the insulator 384. Any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216 is preferably formed using a substance having a barrier property against oxygen or hydrogen.

  For example, the insulator 210 and the insulator 214 are formed using a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 22 is provided to a region where the transistor 21 is provided. Is preferred. Therefore, a material similar to that of the insulator 324 can be used.

  As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor such as the transistor 21 may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses diffusion of hydrogen between the transistor 21 and the transistor 22. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

  As the film having a barrier property against hydrogen, for example, the insulator 210 and the insulator 214 are preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Accordingly, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 21 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 21 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 21.

  For example, the insulator 212 and the insulator 216 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 212 and the insulator 216, a silicon oxide film, a silicon oxynitride film, or the like can be used.

  The insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor that forms the transistor 21, and the like (conductor 205). Note that the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 24 or the transistor 22. The conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  In particular, the insulator 210 and the conductor 218 in a region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 22 and the transistor 21 are layers having a barrier property against oxygen, hydrogen, and water and can be completely separated from each other, so that diffusion of hydrogen from the transistor 22 to the transistor 21 can be suppressed. .

  A transistor 21 is provided above the insulator 214. Note that the transistor 21 illustrated in FIGS. 9A and 9B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  An insulator 280 is provided above the transistor 21. It is preferable that an excess oxygen region be formed in the insulator 280. In particular, in the case where an oxide semiconductor is used for the transistor 21, an insulator having an excess oxygen region is provided in an interlayer film or the like in the vicinity of the transistor 21 so that oxygen vacancies in the oxide 230 included in the transistor 21 are reduced. Can be improved. Further, the insulator 280 that covers the transistor 21 may function as a planarization film that covers the uneven shape below the transistor 21. Note that the insulator 280 is provided in contact with the insulator 281 and the insulator 225 which are formed over the transistor 21.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide which desorbs oxygen by heating means that the amount of desorbed oxygen converted to oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ in TDS analysis. An oxide film having atoms / cm ³ or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower.

  For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

  An insulator 282 is provided over the insulator 280. The insulator 282 is preferably formed using a substance having a barrier property against oxygen or hydrogen. Therefore, the insulator 282 can be formed using a material similar to that of the insulator 214. For example, the insulator 282 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Accordingly, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 21 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 21 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 21.

  An insulator 286 is provided over the insulator 282. The insulator 286 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 286, a silicon oxide film, a silicon oxynitride film, or the like can be used.

  A conductor 246, a conductor 248, and the like are embedded in the insulator 220, the insulator 222, the insulator 224, the insulator 280, the insulator 282, and the insulator 286.

  The conductor 246 and the conductor 248 function as plugs or wirings that are electrically connected to the capacitor 24, the transistor 21, or the transistor 22. The conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Subsequently, a capacitive element 24 is provided above the transistor 21. The capacitor 24 includes the conductor 110, the conductor 120, and the insulator 130.

  Further, the conductor 112 may be provided over the conductor 246 and the conductor 248. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 24, the transistor 21, or the transistor 22. The conductor 110 functions as an electrode of the capacitor 24. Note that the conductor 112 and the conductor 110 can be formed at the same time.

  The conductor 112 and the conductor 110 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-described element as a component. (Tantalum nitride, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.

  In FIGS. 9A and 9B, the conductor 112 and the conductor 110 have single-layer structures; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used. For example, a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.

  In addition, an insulator 130 is provided as a dielectric of the capacitor 24 over the conductor 112 and the conductor 110. Examples of the insulator 130 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, and hafnium nitride. What is necessary is just to use, and it can provide by lamination | stacking or single layer.

  For example, the insulator 130 may be formed using a material having high dielectric strength such as silicon oxynitride. With this configuration, the capacitor 24 includes the insulator 130, whereby the dielectric strength can be improved and electrostatic breakdown of the capacitor 24 can be suppressed.

  A conductor 120 is provided over the insulator 130 so as to overlap with the conductor 110. Note that the conductor 120 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.

  An insulator 150 is provided over the conductor 120 and the insulator 130. The insulator 150 can be provided using a material similar to that of the insulator 320. Further, the insulator 150 may function as a planarization film that covers the concave and convex shapes below the insulator 150.

  The above is the description of the configuration example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Transistor 21>
An example of an OS transistor applicable to the above-described transistor 21 will be described.

  FIG. 10A is a cross-sectional view of the transistor 21 and is also a cross-sectional view of the transistor 21 in the channel width direction.

  As shown in FIG. 10A, the transistor 21 includes at least one of an insulator 224 provided over the insulator 212, an oxide 406a provided over the insulator 224, and an upper surface of the oxide 406a. The oxide 406b disposed in contact with the portion, the oxide 406c disposed in contact with at least part of the top surface of the oxide 406a, the insulator 412 disposed over the oxide 406c, and the insulator 412 A conductor 404a disposed above, a conductor 404b disposed on the conductor 404a, an insulator 412, a conductor 404a, and a sidewall insulator 418 disposed in contact with a side surface of the conductor 404b; And an insulator 225 which is in contact with the top surface and the side surface of the oxides 406b and 406c and in contact with the side surface of the sidewall insulator 418.

  Hereinafter, the oxides 406a, 406b, and 406c may be collectively referred to as the oxide 406. The conductor 404a and the conductor 404b may be collectively referred to as the conductor 404. The conductor 310a and the conductor 310b may be collectively referred to as the conductor 310.

  The transistor 21 may include an insulator 216 disposed over the insulator 401 and a conductor 310 disposed to be embedded in the insulator 216.

  In the conductor 310, a conductor 310a is formed in contact with the inner wall of the opening of the insulator 216, and a conductor 310b is further formed inside. Here, the heights of the upper surfaces of the conductors 310a and 310b and the height of the upper surface of the insulator 216 can be approximately the same.

  The conductor 404 can function as a top gate, and the conductor 310 can function as a back gate. The potential of the back gate may be the same as that of the top gate, or may be a ground potential or an arbitrary potential. Further, the threshold voltage of the transistor can be changed by changing the potential of the back gate independently without interlocking with the top gate.

  Here, the conductor 310a is a conductive material having a function of suppressing the transmission of impurities such as water or hydrogen (difficult to transmit) (a conductive material having a function of suppressing the transmission of impurities such as water or hydrogen). Can also be used). For example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, and a single layer or a stacked layer may be used. Thus, impurities such as hydrogen and water from the lower layer than the insulator 214 can be prevented from diffusing into the upper layer through the conductor 310.

  The conductor 310b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Although not illustrated, the conductor 310b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

  The insulator 214 can function as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor from below. For the insulator 214, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen is preferably used. For example, aluminum oxide or the like is preferably used. Thus, impurities such as hydrogen and water can be prevented from diffusing into the upper layer than the insulator 214.

  The insulator 214 is preferably formed using an insulating material having a function of suppressing permeation of oxygen (eg, oxygen atoms or oxygen molecules). Thus, downward diffusion of oxygen contained in the insulator 224 and the like can be suppressed.

  The insulator 222 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, such as aluminum oxide or hafnium oxide. Accordingly, impurities such as hydrogen and water from a lower layer than the insulator 222 can be prevented from diffusing from the insulator 222 to an upper layer. Furthermore, downward diffusion of oxygen contained in the insulator 224 and the like can be suppressed.

In addition, the concentration of impurities such as water, hydrogen, or nitrogen oxide in the insulator 224 is preferably reduced. For example, the amount of hydrogen desorbed from the insulator 224 is determined by the desorption amount in terms of hydrogen molecules in a temperature desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)) in the range of 50 ° C. to 500 ° C. It may be 2 × 10 ¹⁵ molecules / cm ² or less, preferably 1 × 10 ¹⁵ molecules / cm ² or less, more preferably 5 × 10 ¹⁴ molecules / cm ² or less in terms of the area of the body 224. The insulator 224 is preferably formed using an insulator from which oxygen is released by heating.

  The insulator 412 can function as a first gate insulating film, and the insulator 220, the insulator 222, and the insulator 224 can function as a second gate insulating film.

  FIG. 10B illustrates a cross-sectional view of the transistor 21 having a structure different from that in FIG. FIG. 10B is also a cross-sectional view of the transistor 21 in the channel width direction, like FIG.

  As the oxide 406, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. As the metal oxide, it is preferable to use one having an energy gap of 2 eV or more, preferably 2.5 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.

  Since a transistor including an oxide semiconductor has extremely low leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.

  The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

  Here, a case where the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

  Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

  Here, in the metal oxide used for the oxide 406a, the atomic ratio of the element M in the constituent element is preferably larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 406b. . In the metal oxide used for the oxide 406a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 406b.

  When the metal oxide as described above is used as the oxide 406a, the energy at the lower end of the conduction band of the oxide 406a may be higher than the energy at the lower end of the conduction band in the region where the energy at the lower end of the conduction band of the oxide 406b is low. preferable. In other words, the electron affinity of the oxide 406a is preferably smaller than the electron affinity in a region where the energy at the lower end of the conduction band of the oxide 406b is low.

  Here, in the oxide 406a and the oxide 406b, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to achieve this, the density of defect states in the mixed layer formed at the interface between the oxide 406a and the oxide 406b is preferably reduced.

  Specifically, when the oxide 406a and the oxide 406b have a common element (main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide 406b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide 406a.

  At this time, the main path of carriers is a narrow gap portion formed in the oxide 406b. Since the density of defect states at the interface between the oxide 406a and the oxide 406b can be reduced, influence on carrier conduction due to interface scattering is small, and a high on-state current can be obtained.

  The oxide 406 includes a region 426a, a region 426b, and a region 426c. As illustrated in FIG. 10A, the region 426a is sandwiched between the region 426b and the region 426c. The region 426b and the region 426c are regions whose resistance is reduced by the formation of the insulator 225, and are regions having higher conductivity than the region 426a. The region 426b and the region 426c are added with an impurity element such as hydrogen or nitrogen included in the deposition atmosphere of the insulator 225. Accordingly, oxygen vacancies are formed by the added impurity element around the region overlapping with the insulator 225 of the oxide 406b, and the impurity element further enters the oxygen vacancies, whereby the carrier density is increased and the resistance is reduced. Is done.

  Therefore, the region 426b and the region 426c preferably have a higher concentration of at least one of hydrogen and nitrogen than the region 426a. The concentration of hydrogen or nitrogen may be measured using secondary ion mass spectrometry (SIMS) or the like.

  Note that the resistance of the region 426b and the region 426c is reduced by adding an element that forms oxygen vacancies or an element that combines with oxygen vacancies. Examples of such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. Therefore, the region 426b and the region 426c may include one or more of the above elements.

  The region 426b and the region 426c are formed in a region overlapping with at least the insulator 225 of the oxide 406. Here, one of the region 426b and the region 426c of the oxide 406b can function as a source region, and the other can function as a drain region. The region 426a of the oxide 406b can function as a channel formation region.

  The insulator 412 is preferably provided in contact with the upper surface of the oxide 406b. The insulator 412 is preferably formed using an insulator from which oxygen is released by heating. By providing such an insulator 412 in contact with the top surface of the oxide 406b, oxygen can be effectively supplied to the oxide 406b. Similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 412 is preferably reduced. The thickness of the insulator 412 is preferably greater than or equal to 1 nm and less than or equal to 20 nm, and may be, for example, approximately 10 nm.

The insulator 412 preferably contains oxygen. For example, in a temperature-programmed desorption gas spectroscopy analysis (TDS analysis), the amount of desorption of oxygen molecules per area of the insulator 412 is within a range of a surface temperature of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. 1 × 10 ¹⁴ molecules / cm ² or more, preferably 2 × 10 ¹⁴ molecules / cm ² or more, more preferably 4 × 10 ¹⁴ molecules / cm ² or more.

  The insulator 412 and the conductor 404 have a region overlapping with the oxide 406b. The side surfaces of the insulator 412, the conductor 404a, and the conductor 404b are preferably substantially matched.

  As the conductor 404a, a conductive oxide is preferably used. For example, a metal oxide that can be used as the oxides 406a to 406c can be used. In particular, among In—Ga—Zn-based oxides, the metal atomic ratio is high from [In]: [Ga]: [Zn] = 4: 2: 3 to 4.1, and the vicinity thereof. It is preferable to use those. By providing such a conductor 404a, permeation of oxygen to the conductor 404b can be suppressed and an increase in the electrical resistance value of the conductor 404c due to oxidation can be prevented.

  Further, by forming such a conductive oxide by a sputtering method, oxygen can be added to the insulator 412 and oxygen can be supplied to the oxide 406b. Accordingly, oxygen vacancies in the region 426a of the oxide 406 can be reduced.

  For the conductor 404b, a metal such as tungsten can be used, for example. Alternatively, a conductor that can improve conductivity of the conductor 404a by adding an impurity such as nitrogen to the conductor 404a may be used as the conductor 404b. For example, the conductor 404b is preferably formed using titanium nitride or the like. Alternatively, the conductor 404b may have a structure in which a metal nitride such as titanium nitride and a metal such as tungsten are stacked thereover.

  As the oxide 406, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.

  The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

  Here, a case where the oxide semiconductor is InMZnO containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

  Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

<Variation 1 of cross-sectional structure 1>
An example of a modification of the present embodiment is shown in FIG. FIG. 11 is different from FIG. 9 in the configuration of the transistor 22.

  In the transistor 22 illustrated in FIG. 11, a semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape. Further, the conductor 316 is provided so as to cover the side surface and the upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material that adjusts a work function. Such a transistor 22 is also referred to as a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

  The above is the description of the modified example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Modification 2 of cross-sectional structure 1>
An example of a modification of the present embodiment is shown in FIG. FIG. 12 is different from FIG. 9 in the configuration of the capacitive element 24.

  In the semiconductor device illustrated in FIG. 12, the insulator 287 is provided over the insulator 286, the conductor 112 is embedded in the insulator 287, the insulator 155 is provided over the insulator 287, and the insulator 155 is formed. The conductor 110 is provided in the plurality of openings, the insulator 130 is provided on the conductor 110, and the conductor 120 is provided on the insulator 130 so as to overlap the conductor 110. Further, the conductor 112 is provided so as to connect the conductor 248 electrically connected to the transistor 21 and the conductor 248 electrically connected to the transistor 22, and the conductor 112 is in contact with the conductor 112. 110 may be provided. The insulator 287 and the insulator 155 can be formed using a material similar to that of the insulator 320.

  In the capacitor 24 shown in FIG. 12, the conductor 110, the insulator 130, and the conductor 120 overlap each other in the opening formed in the insulator 155. Therefore, the conductor 110, the insulator 130, and the conductor 120 are overlapped. Is preferably a film having good coverage. Therefore, the conductor 110, the insulator 130, and the conductor 120 are preferably formed using a film formation method having good step coverage such as a CVD method or an ALD method.

  Since the capacitor 24 is formed along the shape of the opening provided in the insulator 155, the capacitance can be increased as the opening is formed deeper. Further, the capacitance can be increased as the number of the openings is increased. By forming such a capacitive element 24, the capacitance can be increased without increasing the upper area of the capacitive element 24.

  The above is the description of the modified example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

<Semiconductor wafer, chip>
FIG. 13A shows a top view of the substrate 711 before the dicing process is performed. As the substrate 711, for example, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used. A plurality of circuit regions 712 are provided on the substrate 711. The circuit region 712 can be provided with a semiconductor device according to one embodiment of the present invention.

  Each of the plurality of circuit regions 712 is surrounded by the isolation region 713. A separation line (also referred to as “dicing line”) 714 is set at a position overlapping with the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit region 712 can be cut out from the substrate 711. FIG. 13B shows an enlarged view of the chip 715.

  Further, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, ESD that may occur in the dicing process can be reduced, and a reduction in yield due to the dicing process can be prevented. In general, the dicing process is performed while supplying pure water having a specific resistance lowered by dissolving carbon dioxide gas or the like for the purpose of cooling the substrate, removing shavings, preventing charging, and the like. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, the amount of pure water used can be reduced. Thus, the production cost of the semiconductor device can be reduced. In addition, the productivity of the semiconductor device can be increased.

<Electronic parts>
An example of an electronic component using the chip 715 will be described with reference to FIGS. 14A, 14B, and 15A to 15E. Note that the electronic component is also referred to as a semiconductor package or an IC package. Electronic parts have a plurality of standards, names, and the like depending on the terminal take-out direction, the terminal shape, and the like.

  Electronic components are completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post-process).

  The post-process will be described with reference to the flowchart shown in FIG. After the semiconductor device or the like according to one embodiment of the present invention is formed over the substrate 711 in the previous step, a “back surface grinding step” of grinding the back surface (the surface where the semiconductor device or the like is not formed) of the substrate 711 is performed (step S721). . By reducing the thickness of the substrate 711 by grinding, the electronic component can be downsized.

  Next, a “dicing process” for separating the substrate 711 into a plurality of chips 715 is performed (step S722). Then, a “die bonding step” is performed in which the separated chip 715 is bonded onto each lead frame (step S723). For the bonding of the chip 715 and the lead frame in the die bonding step, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. Note that the chip 715 may be bonded on the interposer substrate instead of the lead frame.

  Next, a “wire bonding process” is performed in which the lead of the lead frame and the electrode on the chip 715 are electrically connected with a thin metal wire (step S724). A silver wire, a gold wire, etc. can be used for a metal fine wire. For wire bonding, for example, ball bonding or wedge bonding can be used.

  The chip 715 that has been wire bonded is subjected to a “sealing process (molding process)” that is sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, the wire connecting the chip 715 and the lead can be protected from mechanical external force, and deterioration of characteristics due to moisture, dust, etc. (reliability Reduction) can be reduced.

  Next, a “lead plating process” for plating the leads of the lead frame is performed (step S726). The plating process prevents rusting of the lead, and soldering when mounted on a printed circuit board later can be performed more reliably. Next, a “molding process” for cutting and molding the lead is performed (step S727).

  Next, a “marking process” is performed in which a printing process (marking) is performed on the surface of the package (step S728). An electronic component is completed through an “inspection process” (step S729) for checking whether the external shape is good or not, and whether there is a malfunction.

  FIG. 14B shows a schematic perspective view of the completed electronic component. FIG. 14B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 750 illustrated in FIG. 14B includes a lead 755 and a chip 715. The electronic component 750 may have a plurality of chips 715.

  An electronic component 750 illustrated in FIG. 14B is mounted on a printed board 752, for example. A plurality of such electronic components 750 are combined and each is electrically connected on the printed circuit board 752 to complete a substrate (mounting substrate 754) on which the electronic components are mounted. The completed mounting board 754 is used for an electronic device or the like.

  An application example of the electronic component 750 illustrated in FIG. 14B will be described. The electronic component 750 can be applied to various types of removable storage devices such as a memory card (for example, an SD card), a USB memory (USB; Universal Serial Bus), and an SSD (Solid State Drive). Several configuration examples of the removable storage device will be described with reference to FIGS.

  FIG. 15A is a schematic diagram of a USB memory. The USB memory 5100 includes a housing 5101, a cap 5102, a USB connector 5103, and a substrate 5104. The substrate 5104 is housed in the housing 5101. The substrate 5104 is provided with a memory chip or the like which is an electronic component. For example, a memory chip 5105 and a controller chip 5106 are attached to the substrate 5104. The memory chip 5105 includes the memory cell array 2610, the row decoder 2621, the word line driver circuit 2622, the bit line driver circuit 2630, the column decoder 2631, the precharge circuit 2632, the sense amplifier 2633, the output circuit 2640, and the like described in the above embodiment. Is incorporated. The controller chip 5106 incorporates a processor, work memory, ECC circuit, and the like. Note that the circuit configurations of the memory chip 5105 and the controller chip 5106 are not limited to those described above, and the circuit configurations may be changed as appropriate according to circumstances or in some cases. For example, the row decoder 2621, the word line driver circuit 2622, the bit line driver circuit 2630, the column decoder 2631, the precharge circuit 2632, and the sense amplifier 2633 may be incorporated in the controller chip 5106 instead of the memory chip 5105. The USB connector 5103 functions as an interface for connecting to an external device.

  FIG. 15B is a schematic diagram of the appearance of the SD card, and FIG. 15C is a schematic diagram of the internal structure of the SD card. The SD card 5110 includes a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. The substrate 5113 is provided with a memory chip or the like which is an electronic component. For example, a memory chip 5114 and a controller chip 5115 are attached to the substrate 5113. The memory chip 5114 includes the memory cell array 2610, the row decoder 2621, the word line driver circuit 2622, the bit line driver circuit 2630, the column decoder 2631, the precharge circuit 2632, the sense amplifier 2633, and the output circuit 2640 described in the above embodiment. Etc. are incorporated. The controller chip 5115 incorporates a processor, work memory, ECC circuit, and the like. Note that the circuit configurations of the memory chip 5114 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate according to circumstances or in some cases. For example, the row decoder 2621, the word line driver circuit 2622, the bit line driver circuit 2630, the column decoder 2631, the precharge circuit 2632, and the sense amplifier 2633 may be incorporated in the controller chip 5115 instead of the memory chip 5114.

  By providing the memory chip 5114 on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 5113. Accordingly, wireless communication can be performed between the external device and the SD card 5110, and data can be read from and written to the memory chip 5114.

  FIG. 15D is a schematic diagram of the appearance of an SSD, and FIG. 15E is a schematic diagram of the internal structure of the SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. The substrate 5153 is provided with a memory chip or the like which is an electronic component. For example, a memory chip 5154, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153. The memory chip 5154 includes the memory cell array 2610, the row decoder 2621, the word line driver circuit 2622, the bit line driver circuit 2630, the column decoder 2631, the precharge circuit 2632, the sense amplifier 2633, and the output circuit 2640 described in the above embodiment. Etc. are incorporated. By providing the memory chip 5154 on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. A work memory is incorporated in the memory chip 5155. For example, a DRAM chip may be used as the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. Note that the circuit configurations of the memory chip 5154, the memory chip 5155, and the controller chip 5115 are not limited to the above description, and the circuit configurations may be changed as appropriate depending on the situation or in some cases. . For example, the controller chip 5156 may be provided with a memory that functions as a work memory.

  Note that the electronic component 750 illustrated in FIG. 14B can display at a resolution of Super Hi-Vision (also referred to as “8K resolution”, “8K4K”, “8K”, and the like) in which pixels are arranged in a 7680 × 4320 matrix. It is also effective to apply to a frame memory in a system that handles large-scale image data such as a simple display system. In the case of storing multilevel data in a memory cell as a plurality of voltage values, the semiconductor device of one embodiment of the present invention can store a voltage value to be written in a narrow range and improve the reliability of read data. Can do. By application of one embodiment of the present invention, the reading accuracy of the frame memory can be improved. Further, since the storage capacity can be increased, application to a display system capable of displaying at 8K resolution is extremely effective.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 5)
<Electronic equipment>
An electronic component including the semiconductor device according to one embodiment of the present invention can be used for various electronic devices. FIG. 16 illustrates a specific example of an electronic device using the electronic component according to one embodiment of the present invention.

  FIG. 16A is an external view illustrating an example of an automobile. The automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like. The automobile 2980 includes an antenna, a battery, and the like.

  An information terminal 2910 illustrated in FIG. 16B includes a housing 2911 including a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. In addition, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.

  A laptop personal computer 2920 illustrated in FIG. 16C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. The laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.

  A video camera 2940 illustrated in FIG. 16D includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like. The operation switch 2944 and the lens 2945 are provided in the housing 2941, and the display portion 2944 is provided in the housing 2942. In addition, the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941. The housing 2941 and the housing 2942 are connected to each other by a connection portion 2946. The angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.

  FIG. 16E illustrates an example of a bangle information terminal. The information terminal 2950 includes a housing 2951, a display portion 2952, and the like. In addition, an antenna, a battery, and the like are provided inside the information terminal 2950 and the housing 2951. The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.

  FIG. 16F illustrates an example of a wristwatch-type information terminal. The information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like. Further, an antenna, a battery, and the like are provided inside the information terminal 2960 and the housing 2961. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.

  The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. The display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be started by touching an icon 2967 displayed on the display unit 2962. The operation switch 2965 can have various functions such as time setting, power on / off operation, wireless communication on / off operation, manner mode execution and release, and power saving mode execution and release. . For example, the function of the operation switch 2965 can be set by an operating system incorporated in the information terminal 2960.

  In addition, the information terminal 2960 can execute short-range wireless communication that is a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. Further, the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with other information terminals via a connector. Charging can also be performed via the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.

  For example, an electronic component including the semiconductor device of one embodiment of the present invention can hold the above-described electronic device control information, a control program, and the like for a long period of time. With the use of the semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be realized.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Additional notes regarding the description of this specification etc.)
The above embodiment and description of each component in the embodiment will be added below.

  The structure described in each embodiment can be combined with the structure described in any of the other embodiments as appropriate, for one embodiment of the present invention. In addition, in the case where a plurality of structure examples are given in one embodiment, any of the structure examples can be combined as appropriate.

  Note that the content (may be a part of content) described in one embodiment is different from the content (may be a part of content) described in the embodiment and / or one or more Application, combination, replacement, or the like can be performed on content described in another embodiment (may be partial content).

  Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

  Note that a drawing (or a part) described in one embodiment may be another part of the drawing, another drawing (may be a part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment.

  Further, in the present specification and the like, in the block diagram, the constituent elements are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved over a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

  In the drawings, the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

  In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.

  Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

  In this specification and the like, voltage and potential can be described as appropriate. The voltage is a potential difference from a reference potential. For example, when the reference potential is a ground voltage (ground voltage), the voltage can be rephrased as a potential. The ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.

  Note that in this specification and the like, terms such as “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer”.

  In this specification and the like, a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass current. Alternatively, the switch refers to a switch having a function of selecting and switching a current flow path.

  As an example, an electrical switch or a mechanical switch can be used. That is, the switch is not limited to a specific one as long as it can control the current.

  Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or a logic circuit combining these.

  Note that in the case where a transistor is used as the switch, the “conducting state” of the transistor means a state where the source and the drain of the transistor can be regarded as being electrically short-circuited. In addition, the “non-conducting state” of a transistor refers to a state where the source and drain of the transistor can be regarded as being electrically cut off. Note that when a transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.

  An example of a mechanical switch is a switch using MEMS (micro electro mechanical system) technology, such as a digital micromirror device (DMD). The switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.

  In this specification and the like, the channel length means, for example, a region where a semiconductor (or a portion of a semiconductor through which a current flows when the transistor is on) and a gate overlap with each other, or a channel in a top view of the transistor. This is the distance between the source and drain in the region.

  In this specification and the like, the channel width refers to, for example, a source in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap or a region where a channel is formed And the length of the part where the drain faces.

  In this specification and the like, “A and B are connected” includes not only those in which A and B are directly connected but also those that are electrically connected. Here, A and B are electrically connected. When there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. It says that.

10a Semiconductor device 20 Memory cell 21 Transistor 22 Transistor 23 Transistor 24 Capacitor element 28 Data write circuit 30 Data read circuit 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Capacitor element 39 Transistor 39a Analog digital conversion circuit 41 Amplifier circuit 41a amplifier circuit 41d amplifier circuit 42 feature extraction circuit 43 judgment output circuit 110 conductor 112 conductor 120 conductor 130 insulator 150 insulator 155 insulator 205 conductor 210 insulator 212 insulator 214 insulator 216 insulator 218 conductor 220 Insulator 222 Insulator 224 Insulator 225 Insulator 230 Oxide 246 Conductor 248 Conductor 280 Insulator 281 Insulator 282 Insulator Body 286 insulator 287 insulator 310 conductor 310a conductor 310b conductor 311 substrate 313 semiconductor region 314a low resistance region 314b low resistance region 315 insulator 316 conductor 320 insulator 322 insulator 324 insulator 326 insulator 328 conductor 330 conductor 350 insulator 352 insulator 354 insulator 356 conductor 360 insulator 362 insulator 364 insulator 366 conductor 370 insulator 372 insulator 374 insulator 376 conductor 380 insulator 382 insulator 384 insulator 386 conductor Body 401 insulator 404 conductor 404a conductor 404b conductor 404c conductor 406 oxide 406a oxide 406b oxide 406c oxide 412 insulator 418 sidewall insulator 426a region 426b region 426c region 711 substrate 712 circuit region 713 min Separation area 714 Separation line 715 Chip 750 Electronic component 752 Printed circuit board 754 Mounting board 755 Lead 2610 Memory cell array 2621 Row decoder 2622 Word line driver circuit 2630 Bit line driver circuit 2631 Column decoder 2632 Precharge circuit 2633 Sense amplifier 2640 Output circuit 2910 Information terminal 2911 Case 2912 Display unit 2913 Camera 2914 Speaker unit 2915 Operation switch 2916 External connection unit 2917 Microphone 2920 Notebook personal computer 2921 Case 2922 Display unit 2923 Keyboard 2924 Pointing device 2940 Video camera 2941 Case 2942 Case 2943 Display unit 2944 Operation Switch 2945 Lens 2946 Connection unit 2950 Information terminal 2951 Case 952 Display unit 2960 Information terminal 2961 Case 2962 Display unit 2963 Band 2964 Buckle 2965 Operation switch 2966 Input / output terminal 2967 Icon 2980 Automobile 2981 Car body 2982 Wheel 2983 Dashboard 2984 Light 5100 USB memory 5101 Case 5102 Cap 5103 USB connector 5104 Board 5105 Memory chip 5106 Controller chip 5110 SD card 5111 Housing 5112 Connector 5113 Substrate 5114 Memory chip 5115 Controller chip 5150 SSD
5151 Housing 5152 Connector 5153 Substrate 5154 Memory chip 5155 Memory chip 5156 Controller chip

Claims (12)

A semiconductor device having a data write circuit, a data read circuit, a memory cell, a data read line, and a data write line,
The memory cell includes a first transistor, a second transistor, a third transistor, and a first node;
One of a source and a drain of the first transistor is electrically connected to the data write line;
The other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor;
One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor;
The other of the source and the drain of the third transistor is electrically connected to the data read line;
The first node is formed by connecting the other of the source or the drain of the first transistor and the gate of the second transistor,
The data write circuit has a function of writing the first data and correction data to the memory cell via the data write line,
The first transistor has a function of holding a charge corresponding to the first data stored in the first node or the correction data by being turned off,
The data read circuit includes:
A function of reading the first potential corresponding to the first data through the data read line by turning on the third transistor;
A function of holding the first potential;
A function of reading the second potential;
A function of writing back the first data to the memory cell via the data write line;
A semiconductor device comprising: In claim 1,
The semiconductor device further includes a first switch, a second switch, and a third switch,
The data read circuit is electrically connected to the data read line via the first switch,
The data write circuit is electrically connected to the data write line through the second switch,
The data read circuit is electrically connected to the data write line through the third switch,
Turning off the second switch and the third switch;
Turn on the first switch,
The data read circuit has a function of reading and storing the first potential from the memory cell;
Turning off the first switch and the third switch;
Turn on the second switch,
The data writing circuit has a function of writing the correction data to the memory cell;
Turning off the second switch and the third switch;
Turn on the first switch,
The data read circuit has a function of reading the second potential from the memory cell;
Turning off the first switch and the second switch;
Turn on the third switch,
A semiconductor device having a function of writing back the first data to the memory cell. In claim 1 or claim 2,
The data writing circuit includes a digital-analog conversion circuit. In claim 1 or claim 2,
The data writing circuit includes a comparison circuit. In claim 1 or claim 2,
The data read circuit includes a first source follower circuit, a second source follower circuit, a third source follower circuit, a capacitor, a second node, a third node, an input terminal, and a first output terminal. Have
The first source follower circuit includes a fourth transistor;
The second source follower circuit includes a fifth transistor, a sixth transistor, and a seventh transistor,
The third source follower circuit includes the fifth transistor, the eighth transistor, the ninth transistor, and the tenth transistor,
The input terminal is electrically connected to the data read line via the first switch,
The output terminal is electrically connected to the data write line through the third switch,
The input terminal is electrically connected to one of a source and a drain of the fourth transistor, one of a source and a drain of the tenth transistor, and a gate of the sixth transistor,
The output terminal includes one of a source and a drain of the fifth transistor, one of a source and a drain of the sixth transistor, one of a source and a drain of the eighth transistor, and an electrode of the capacitor. One is electrically connected,
The other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor;
The other of the source and the drain of the eighth transistor is electrically connected to one of the source and the drain of the ninth transistor;
The other of the source and the drain of the tenth transistor is electrically connected to the gate of the eighth transistor;
The second node is formed by connecting the gate of the eighth transistor and the other of the source and the drain of the tenth transistor,
The third node is formed by connecting the output terminal and one of the electrodes of the capacitive element,
The first source follower circuit includes:
A function in which the first data is given to a gate of the second transistor included in the memory cell;
A function wherein the first input is provided to the gate of the fourth transistor;
The first potential is applied to the input terminal;
The second source follower circuit is:
A function in which a third input is provided to the gate of the fifth transistor;
A function of applying the first potential to the gate of the sixth transistor;
A second output having a function provided to the third node;
The third source follower circuit is:
A function in which a third input is provided to the gate of the fifth transistor;
A function in which the first potential held in the second node is applied to the gate of the eighth transistor;
And a third output having a function given to the third node. In claim 5,
The data read circuit further includes a second output terminal and an analog-digital conversion circuit,
A semiconductor device having a function of outputting the first data to the second output circuit through the analog-digital conversion circuit. In claim 5,
The data read circuit further includes a second output terminal and a comparison circuit,
A semiconductor device having a function of outputting the first data to the second output circuit through the comparison circuit. In claim 1 or claim 5,
The semiconductor device, wherein the first transistor includes a metal oxide in a semiconductor layer. In claim 8,
The semiconductor device, wherein the first transistor having a metal oxide in a semiconductor layer has a back gate. The semiconductor device according to any one of claims 1 to 9,
A lead electrically connected to the semiconductor device;
An electronic component comprising: The electronic component according to claim 10;
A printed circuit board provided with the electronic component;
A housing in which the printed circuit board is stored;
An electronic device comprising: In the electronic device which has the semiconductor device according to any one of claims 1 to 9,
The electronic device has a neural network,
The neural network has a plurality of neurons,
The neuron includes the semiconductor device, an amplifier circuit, a feature extraction circuit, and a determination output circuit.
The amplifier circuit has a function of giving a weighting factor of analog data from the semiconductor device,
The determination output circuit has a function of giving a determination threshold value of analog data from the semiconductor device.

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