FR3159701A1 - Méthode de fabrication d’une structure empilée du type silicium contraint sur isolant en utilisant une technique de transfert de couche à base de matériau 2d - Google Patents
Méthode de fabrication d’une structure empilée du type silicium contraint sur isolant en utilisant une technique de transfert de couche à base de matériau 2dInfo
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- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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Abstract
L’invention concerne une méthode de fabrication d’une structure empilée comprenant une couche de matériau semi-conducteur collée à un substrat, comprenant :
la fabrication d’une hétérostructure par :
formation d’une couche intermédiaire constituée d’un matériau en deux dimensions sur un substrat de croissance (1) ;modelage de la couche intermédiaire avec une pluralité d’ouvertures pour former une couche intermédiaire modelée (3) ;croissance d’un matériau semi-conducteur sur la couche intermédiaire modelée (3) par surcroissance latérale épitaxiale pour former une couche épitaxiale continue (4) sur la couche intermédiaire modelée ;
la formation d’un premier ensemble par collage de l’hétérostructure à un substrat de manipulation (6), la couche épitaxiale continue étant située au niveau de l’interface de collage ;la séparation du premier ensemble au niveau de la couche intermédiaire modelée (3) de façon à obtenir un deuxième ensemble résultant du transfert de la couche épitaxiale continue (4) depuis l’hétérostructure vers le substrat de manipulation (6).
Figure pour l’abrégé : Figure 7
Description
The field of the invention is that of methods for manufacturing a stacked structure comprising a layer of semiconductor material adhered to a substrate. More particularly, the invention relates to processes that implement a 2D material-based layer transfer technique in order for instance to manufacture a stacked structure of the strained-SOI type.
Remote epitaxy is an emerging technology for producing single-crystalline, free-standing thin films and structures. The method uses 2D van der Waals materials as semi-transparent interlayers that enable epitaxy and exfoliation of epitaxial layers at the 2D layer interface by mechanical delamination, known as 2D material-based layer transfer (2DLT).
As for instance described in WO 2019/099461 A1, the 2DLT process may use a patterned 2D layer with a plurality of openings therein and the layer transfer is performed by first depositing a stressor layer made of nickel on the epitaxial layer previously grown on the patterned 2D material layer and then applying a tape layer on the stressor layer. The stack consisting of the tape layer, the stressor layer and the epitaxial layer can then be exfoliated following a detachment induced at the 2D patterned layer by mechanical energy. After exfoliation, the tape layer and the stressor layer are respectively released and etched away by a Fe-Cl3 solution. However, iron is an unwanted contaminant for making semiconductor devices in general.
The invention aims at proposing a 2DLT technique that would not require the use of a stressor layer and be therefore free of its associated contamination. To this purpose is proposed a method of manufacturing a stacked structure comprising a layer of semiconductor material adhered to a substrate, comprising:
- manufacturing a heterostructure by:
- forming an interlayer made of a two-dimensional material on a growth substrate;
- patterning the interlayer with a plurality of openings to form a patterned interlayer;
- growing a semiconductor material on the patterned interlayer by epitaxial lateral overgrowth to form a continuous epitaxial layer on the patterned interlayer;
- forming a first assembly by bonding the heterostructure with a handle substrate, the continuous epitaxial layer being located at the bonding interface;
- separating the first assembly at the level of the patterned interlayer so as to obtain a second assembly resulting from the transfer of the continuous epitaxial layer from the heterostructure towards the handle substrate.
Patterning the interlayer is performed so that 1% to 10% of a surface of the growth substrate on which the patterned interlayer is located is uncovered with the remainder being covered by the two-dimensional material.
Bonding the heterostructure with the handle substrate comprises one of a surface activated bonding, an atomic diffusion bonding and a hydrophilic bonding accompanied by a bonding strength reinforcement annealing.
Certain preferred, but non-limiting aspects of the method are as follows :
- the handle substrate includes a top oxide layer which is located at the bonding interface when forming the first assembly;
- the handle substrate further includes a trap rich layer underneath the top oxide layer;
- it further comprises planarizing the top oxide layer before forming the first assembly;
- the continuous epitaxial layer is a relaxed layer and manufacturing the heterostructure further comprises the epitaxial deposition of a strained layer on the continuous epitaxial layer;
- it further comprises removing the continuous epitaxial layer from the second assembly;
- the strained layer is a strained silicon layer;
- the growth substrate comprises a graded buffer and a relaxed growth layer on the graded buffer, the graded buffer having a lattice parameter graded between a first lattice parameter and a second lattice parameter and the relaxed growth layer having the second lattice parameter;
- it further comprises, after separating the first assembly at the level of the patterned interlayer, recycling the growth substrate, wherein said recycling comprises polishing the relaxed growth layer;
- the continuous epitaxial layer is a relaxed layer;
- it further comprises planarizing the continuous epitaxial layer before forming the first assembly;
- patterning the interlayer leaves a peripheral ring of the two-dimensional material on the growth substrate;
- two neighbouring openings of the patterned interlayer are separated by a distance which is less than 40 micrometers, preferably less than 20 micrometers.
Other aspects, aims, advantages and features of the invention will better appear upon reading the following detailed description of preferred embodiments thereof, provided as a non-limiting example, and done in reference to the appended drawings, in which:
- Figures 1 to 9 illustrate a possible embodiment of a method according to the invention;
- Figures 10 and 11 show two different embodiments of an heterostructure which can be used in a method according to the invention.
The invention relates to a method of manufacturing a stacked structure comprising a layer of semiconductor material adhered to a substrate, which method implements a 2DLT process. More particularly, the 2DLT process makes use of a patterned 2D material layer with a plurality of openings therein.
This method comprises manufacturing an heterostructure. With reference toFIG. 1 , this manufacturing starts with providing a growth substrate 1.
Then, with reference toFIG. 2 manufacturing the heterostructure comprises forming an interlayer 2 made of a two-dimensional material on the growth substrate 1. This formation may be performed after planarization of the surface of the growth substrate 1, for example by means of chemical mechanical polishing. This formation may include the deposition of the two-dimensional material on the growth substrate 1. Non-exhaustively, this deposition can be performed by means of MBE (Molecular Beam Epitaxy), CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Epitaxy).
The two-dimensional material can be hexagonal boron nitride h-BN, graphene or more generally any 2D "Van der Waals" material allowing remote epitaxy. The interlayer 2 of two-dimensional material is thus constituted of monoatomic sheets having weak interactions between them and whose number is limited to allow the remote epitaxy of a layer of semiconductor material.
With reference toFIG. 3 , manufacturing the heterostructure further comprises patterning the interlayer 2 with a plurality of openings to form a patterned interlayer 3.
Patterning the interlayer offers several advantages as for instance discussed in Kim, H., Lee, S., Shin, J.et al.Graphene nanopattern as a universal epitaxy platform for single-crystal membrane production and defect reduction.Nat. Nanotechnol. 17, 1054–1059 (2022). https://doi.org/10.1038/s41565-022-01200-6. In particular, patterning the interlayer can reduce the interface toughness between the growth substrate 1 and a continuous epitaxial layer 4 grown on the patterned interlayer as discussed below.
The openings may be made by etching the 2D material following a lithographic process. The openings may be trenches that delineate strips of 2D material. The trenches may be parallel to each other. A width of the trenches may be comprised between several tens of nanometers to several micrometers. Two neighbouring openings of the patterned interlayer are separated by a distance (the width of the stripes in case of parallel trenches) which is less than 40 micrometers, preferably less than 20 micrometers. This distance between openings is calibrated against lateral to vertical growth speed difference and CTE matching of materials so as to prevent bow, warp or cracks from occurring.
In a preferred embodiment, patterning the interlayer is performed so that the patterned interlayer 3 has an opening ratio comprised between 1% and 10%, i.e., 1% to 10% of a surface of the growth substrate on which the patterned interlayer is located is uncovered with the remainder being covered by the two-dimensional material. In other words, the growth substrate has a 2D material coverage percentage comprised between 90% and 99%.
The 1% lower bound is calibrated for a preferred embodiment described later (where a strained Si layer is grown on a continuous epitaxial layer 4 made of relaxed SiGe which is itself grown on a 2D material patterned with parallel trenches) and allows reaching coalescence for thicknesses not causing CTE mismatch issues. The 10% upper bond allows operating in the exfoliation regime, and not in the other two regimes, namely spalling or delamination.
In a possible embodiment, patterning the interlayer is performed so as to leave a peripheral ring of the two-dimensional material on the growth substrate. The presence of such a peripheral ring facilitates the initiation of the later separation at the level of the patterned interlayer.
With reference toFIG. 4 , manufacturing the heterostructure further comprises growing a semiconductor material on the patterned interlayer by epitaxial lateral overgrowth to form a continuous epitaxial layer 4 on the patterned interlayer 3. More particularly, growing the semiconductor material starts with the localized growth of seeds in the openings patterned in the 2D material. The lateral growth of these seeds is then activated which results in the seeds growing laterally over the 2D material and finally coalescing to produce the continuous epitaxial layer 4.
In a preferred embodiment, the continuous epitaxial layer 4 is then planarized, for instance by means of a chemical-mechanical polishing CMP, to improve its morphological quality and more particularly to obtain a uniform and controllable thickness and fewer coalescent defects.
In another embodiment shown onFIG. 5 , manufacturing the heterostructure may further comprise performing the epitaxial deposition of one (or more) additional layer(s) 5 on the continuous epitaxial layer 4. A bilayer can thereby be formed which is separated from the growth substrate 1 by the patterned interlayer 3. The additional layer 5 may be a strained layer, as will be exemplified below.
Once the heterostructure is manufactured, with reference toFIG. 6 the method of the invention comprises forming a first assembly by bonding the heterostructure with a handle substrate 6, the continuous epitaxial layer 4 being located at the bonding interface. In the case where an additional layer 5 has previously been formed on the continuous epitaxial layer, the bilayer which includes the continuous epitaxial layer 4 is located at the bonding interface.
In a preferred embodiment, the handle substrate 6 includes a top oxide layer 7 which is located at the bonding interface when forming the first assembly. The handle substrate 6 may further include a trap rich layer underneath the top oxide layer.
The top oxide layer 7 may be planarized, for instance by means of a chemical-mechanical polishing CMP, before forming the first assembly. In particular, such planarization proves to be advantageous to reduce the surface roughness of the top oxide layer when grown on a trap rich layer.
In an example embodiment, the handle substrate 6 is a silicon substrate and the top oxide layer 7 may have been formed by thermal oxidation of the silicon handle substrate.
Bonding the heterostructure with the handle substrate 6 is performed in such a way as to achieve an interface bonding energy at the bonding interface of the heterostructure and the handle substrate that is greater than the interface toughness, through the patterned interface 3, between the growth substrate 1 and the continuous epitaxial layer 4. Stated differently, the bonding strength is such compared to the patterned interface toughness that the later application of dissembling mechanical forces to the first assembly leads to the separation of the first assembly at the patterned interface rather than at the bonding interface.
When the growth of the continuous epitaxial layer 4 proceeds in the openings, the resulting interface energy is quite high as it is related to the binding energy between atoms of the 2D material and the overgrown layer whereas when the growth of the continuous epitaxial layer 4 proceeds on the 2D material in between the openings, the resulting interface energy is quite low as no bonds are formed between the 2D material and the overgrown layer, only a weak van der Waals interaction. Therefore, the opening ratio is a trade-off between the required global interface energy to allow the later separation and the process time needed to perform the epitaxial lateral overgrowth of the continuous epitaxial layer (this process time being all the more important as the openings are large as indeed the larger the openings, the thicker the growth is to be performed to reach coalescence).
In a possible embodiment, bonding the heterostructure with the handle substrate comprises a surface activated bonding SAB or an atomic diffusion bonding ADB. In such manner, a high bonding strength is achieved without the need for a bonding strength reinforcement annealing. This proves advantageous over the regular Smart CutTMprocess implemented with trap rich layers for which during a heat treatment (such as the one for strengthening hydrophilic bonding) grains reorganize leading to a localized deformation at the bonding interface, and therefore a localized weak bonding energy. Later, during splitting, the splitting wave will tend to pass through the weak bonded area and no layer transfer occurs around these regions. With the use of a 2D layer, there are no splitting waves. Furthermore, no heat treatments are required for SAB and ADB techniques.
In another possible embodiment, bonding the heterostructure with the handle substrate comprises a hydrophilic bonding and forming the first assembly further comprises performing a bonding strength reinforcement annealing, for instance between 900°C and 1100°C. A plasma treatment of the yet to-be-bonded surfaces may further be implemented, which allows for an increased bonding strength.
Once the first assembly is formed by bonding the heterostructure with the handle substrate 6, with reference toFIG. 7 , the method of the invention comprises separating the first assembly at the level of the patterned interlayer 3 so as to obtain a second assembly (shown onFIG. 8 ) resulting from the transfer of the continuous epitaxial layer 4 from the heterostructure towards the handle substrate 6. This separation can be a mechanical detachment at the patterned interlayer induced by pulling apart the heterostructure and the handle substrate, for instance using blade insertion at the interface. Advantageously, this separation can be performed at room temperature.
When the heterostructure includes a bilayer, with reference toFIG. 9 , the method may further comprises removing the continuous epitaxial layer 4 from the second assembly. This removing may comprise a selective wet or dry etching of the continuous epitaxial layer 4 in which the additional layer 5 acts as an etch-stop layer.
Figures 10 and 11 show two possible embodiments of a heterostructure which includes a bilayer 4, 5 in which the additional layer 5 is a strained layer grown by heteroepitaxy on the continuous epitaxial layer 4. The additional layer may be a strained layer as a result of:
- The continuous epitaxial layer 4 being a relaxed layer, its thickness being above a critical thickness which is the thickness up to which relaxation does not occur and beyond which relaxation occurs by plastic deformation;
- The additional layer 5 being made in a material which has a different lattice parameter than the material of the epitaxial layer and its thickness is below the critical thickness.
These two embodiments allow for transferring such a strained layer on the handle substrate by detachment at the 2D patterned interface 3. The transferred layer remains strained after its transfer onto the handle substrate.
As shown onFIG. 10 , the growth substrate 1 may be a silicon substrate on which is formed a 2D interlayer, for instance made of graphene. The 2D interlayer is patterned and the continuous epitaxial layer 4 is formed on the patterned 2D interlayer 3. The continuous epitaxial layer 4 may be a relaxed layer having a plateau of constant lattice, such as a relaxed SiGe layer with for instance a 20% Ge content. The additional layer 5 may be a strained silicon layer.
As shown onFIG. 11 , the growth substrate 1 may be a silicon substrate on which is formed a graded buffer 8 and a relaxed growth layer 9 on the graded buffer 8. The graded buffer has a lattice parameter graded between a first lattice parameter and a second lattice parameter and the relaxed growth layer has the second lattice parameter. The graded buffer may be a SiGe graded buffer which Ge content increases as the distance from the growth substrate 1 increases, for instance from 0% to 20% Ge content. The relaxed growth layer 9 may be a SiGe layer with a 20% Ge content. A 2D interlayer, for instance made of graphene, is formed on the relaxed growth layer 9. The 2D interlayer is patterned and the continuous epitaxial layer 4 is formed on the patterned 2D interlayer 3. The continuous epitaxial layer 4 may be a relaxed layer having a plateau of constant lattice, such as a relaxed SiGe layer with for instance a 20% Ge content. The additional layer 5 may be a strained silicon layer.
After the heterostructure is separated at the 2D patterned interlayer, it may be recycled as follows to be once again used in the method of the invention. First, remaining portions of the patterned interlayer can be removed, for instance by oxygen treatment in the case of graphene. Then, in the case ofFIG. 10 , grinding and polishing of the growth substrate can be performed before it can be used in a new cycle starting with the formation of a new 2D interlayer. In the case ofFIG. 11 , polishing of the relaxed growth layer 9 can be performed before a new 2D interlayer is former thereon. In a preferred embodiment, the initial thickness of the relaxed growth layer 9 is of several micrometers thereby allowing performing several recycling loops. Indeed, polishing the relaxed growth layer 9 in a recycling loop may remove a thickness comprises between 3 µm-4µm. Performing several recycling loops may necessitate performing CTE compensation as for instance disclosed in US 2008/017952 A1 by including a strained transitional layer in the graded buffer.
In addition to allowing the transfer of the continuous epitaxial layer onto the handle substrate without the need for a stressor layer, the invention also proves advantageous in that it provides a method for transferring a strained layer onto a handle substrate that overcomes the drawbacks of the prior art solutions.
Considering the transfer of a strained silicon layer, a prior art solution which makes use of the Smart CutTMprocess to manufacture a strained silicon on insulator structure is for instance exposed in WO 2007/019260 A1. It comprises forming a donor substrate by growing a strained Si layer on a relaxed SiGe layer and forming a cleave plane in the relaxed SiGe layer by implantation of ionic species. The donor substrate is then bonded to a handle substrate before it is separated at the cleave plane, thereby transferring the strained Si layer onto the handle substrate. Afterwards, the transferred strained Si layer is annealed to cure damages induced by the implantation, thereby improving its crystallinity. However, a high number of dislocations is still observed and it gets difficult to reduce the threading dislocation density below 105/cm². In addition, many macroscopic defects are present in the final structure, especially within the thin buried oxide layer. It shall also be noted that this prior art solution hinders the integration of a trap rich layer in the handle substrate because of the transfer sensitivity to the nanotopology/roughness of the bonded wafers.
By contrast to this prior art solution, the present invention has the following benefits. The number of dislocations in the strained Si film is reduced thanks to performing epitaxy through the patterned interlayer. In addition, because the detachment of the heterostructure at the 2D interlayer layer is completely different from the Smart CutTMsplitting, defectivity in the transferred layer is improved. Another benefit is also the fact that the 2D material covers the entire substrate surface (FIG. 2 ) allowing a full wafer layer transfer without non bonded edge crown which also simplifies the recycling process. Another benefit is that it is compatible with the presence of a trap rich layer. And finally, because the invention does not rely of an implantation of ionic species, there is need to for an annealing treatment to recover the implantation damages and the invention can be performed at very low thermal budget.
Claims (13)
- A method of manufacturing a stacked structure comprising a layer of semiconductor material adhered to a substrate, comprising:
- manufacturing a heterostructure by:
- forming an interlayer (2) made of a two-dimensional material on a growth substrate (1);
- patterning the interlayer with a plurality of openings to form a patterned interlayer (3);
- growing a semiconductor material on the patterned interlayer (3) by epitaxial lateral overgrowth to form a continuous epitaxial layer (4) on the patterned interlayer;
- forming a first assembly by bonding the heterostructure with a handle substrate (6), the continuous epitaxial layer being located at the bonding interface;
- separating the first assembly at the level of the patterned interlayer (3) so as to obtain a second assembly resulting from the transfer of the continuous epitaxial (4) layer from the heterostructure towards the handle substrate (6);
wherein bonding the heterostructure with the handle substrate comprises one of a surface activated bonding, an atomic diffusion bonding and a hydrophilic bonding accompanied by a bonding strength reinforcement annealing. - manufacturing a heterostructure by:
- The method of claim 1, wherein the handle substrate includes a top oxide layer (7) which is located at the bonding interface when forming the first assembly.
- The method of claim 2, wherein the handle substrate further includes a trap rich layer underneath the top oxide layer.
- The method of claim 3, further comprising planarizing the top oxide layer (7) before forming the first assembly.
- The method of one of claims 1 to 4, wherein the continuous epitaxial layer (4) is a relaxed layer and wherein manufacturing the heterostructure further comprises the epitaxial deposition of a strained layer (5) on the continuous epitaxial layer (4).
- The method of claim 5, further comprising removing the continuous epitaxial layer (4) from the second assembly.
- The method of one of claims 5 and 6, wherein the strained layer is a strained silicon layer.
- The method of any one of claims 1 to 7, wherein the growth substrate comprises a graded buffer (8) and a relaxed growth layer (9) on the graded buffer, the graded buffer having a lattice parameter graded between a first lattice parameter and a second lattice parameter and the relaxed growth layer having the second lattice parameter.
- The method of claim 8, further comprising, after separating the first assembly at the level of the patterned interlayer (3), recycling the growth substrate, wherein said recycling comprises polishing the relaxed growth layer (9).
- The method of one of claims 1 to 9, wherein the continuous epitaxial layer (4) is a relaxed layer.
- The method of one of claims 1 to 10, further comprising planarizing the continuous epitaxial layer (4) before forming the first assembly.
- The method of one of claims 1 to 11, wherein patterning the interlayer (2) leaves a peripheral ring of the two-dimensional material on the growth substrate.
- The method of one of claims 1 to 12, wherein two neighbouring openings of the patterned interlayer are separated by a distance which is less than 40 micrometers, preferably less than 20 micrometers.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2401753A FR3159701A1 (fr) | 2024-02-22 | 2024-02-22 | Méthode de fabrication d’une structure empilée du type silicium contraint sur isolant en utilisant une technique de transfert de couche à base de matériau 2d |
| PCT/EP2025/054656 WO2025176816A1 (fr) | 2024-02-22 | 2025-02-20 | Méthode de fabrication d'une structure empilée du type silicium contraint sur isolant en utilisant une technique de transfert de couche à base de matériau 2d |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2401753 | 2024-02-22 | ||
| FR2401753A FR3159701A1 (fr) | 2024-02-22 | 2024-02-22 | Méthode de fabrication d’une structure empilée du type silicium contraint sur isolant en utilisant une technique de transfert de couche à base de matériau 2d |
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| Publication Number | Publication Date |
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| FR3159701A1 true FR3159701A1 (fr) | 2025-08-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| FR2401753A Pending FR3159701A1 (fr) | 2024-02-22 | 2024-02-22 | Méthode de fabrication d’une structure empilée du type silicium contraint sur isolant en utilisant une technique de transfert de couche à base de matériau 2d |
Country Status (2)
| Country | Link |
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| FR (1) | FR3159701A1 (fr) |
| WO (1) | WO2025176816A1 (fr) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007019260A1 (fr) | 2005-08-03 | 2007-02-15 | Memc Electronic Materials, Inc. | Structure de silicium contraint sur isolant (ssoi) avec une cristallinité améliorée dans la couche de silicium contraint |
| US20080017952A1 (en) | 2006-07-24 | 2008-01-24 | Asm America, Inc. | Strained layers within semiconductor buffer structures |
| US20130285016A1 (en) * | 2012-04-25 | 2013-10-31 | Yang Wei | Epitaxial structure |
| WO2017044577A1 (fr) * | 2015-09-08 | 2017-03-16 | Massachusetts Institute Of Technology | Système et procédés pour transfert de couches fondé sur le graphène |
| WO2018156877A1 (fr) * | 2017-02-24 | 2018-08-30 | Massachusetts Institute Of Technology | Appareil et procédés pour réseau plan focal incurvé |
| WO2019099461A1 (fr) | 2017-11-14 | 2019-05-23 | Massachusetts Institute Of Technology | Croissance épitaxiale et transfert par l'intermédiaire de couches bidimensionnelles à motifs (2d) |
-
2024
- 2024-02-22 FR FR2401753A patent/FR3159701A1/fr active Pending
-
2025
- 2025-02-20 WO PCT/EP2025/054656 patent/WO2025176816A1/fr active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007019260A1 (fr) | 2005-08-03 | 2007-02-15 | Memc Electronic Materials, Inc. | Structure de silicium contraint sur isolant (ssoi) avec une cristallinité améliorée dans la couche de silicium contraint |
| US20080017952A1 (en) | 2006-07-24 | 2008-01-24 | Asm America, Inc. | Strained layers within semiconductor buffer structures |
| US20130285016A1 (en) * | 2012-04-25 | 2013-10-31 | Yang Wei | Epitaxial structure |
| WO2017044577A1 (fr) * | 2015-09-08 | 2017-03-16 | Massachusetts Institute Of Technology | Système et procédés pour transfert de couches fondé sur le graphène |
| WO2018156877A1 (fr) * | 2017-02-24 | 2018-08-30 | Massachusetts Institute Of Technology | Appareil et procédés pour réseau plan focal incurvé |
| WO2019099461A1 (fr) | 2017-11-14 | 2019-05-23 | Massachusetts Institute Of Technology | Croissance épitaxiale et transfert par l'intermédiaire de couches bidimensionnelles à motifs (2d) |
Non-Patent Citations (1)
| Title |
|---|
| KIM, H.LEE, S.SHIN, J. ET AL.: "Graphene nanopattern as a universal epitaxy platform for single-crystal membrane production and defect reduction", NAT. NANOTECHNOL., vol. 17, 2022, pages 1054 - 1059 |
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| Publication number | Publication date |
|---|---|
| WO2025176816A1 (fr) | 2025-08-28 |
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