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US20070278574A1 - Compound semiconductor-on-silicon wafer with a thermally soft insulator - Google Patents

Compound semiconductor-on-silicon wafer with a thermally soft insulator Download PDF

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Publication number
US20070278574A1
US20070278574A1 US11/443,144 US44314406A US2007278574A1 US 20070278574 A1 US20070278574 A1 US 20070278574A1 US 44314406 A US44314406 A US 44314406A US 2007278574 A1 US2007278574 A1 US 2007278574A1
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layer
wafer
thermally
soft insulator
forming
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US11/443,144
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Sheng Teng Hsu
Tingkai Li
Jong-Jan Lee
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Sharp Laboratories of America Inc
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Sharp Laboratories of America Inc
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Priority to US11/443,144 priority Critical patent/US20070278574A1/en
Assigned to SHARP LABORATORIES OF AMERICA, INC. reassignment SHARP LABORATORIES OF AMERICA, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, JONG-JAN, HSU, SHENG TENG, LI, TINGKAI
Priority to US11/481,437 priority patent/US7358160B2/en
Priority to JP2007114773A priority patent/JP4975513B2/en
Priority to JP2007136032A priority patent/JP2007326771A/en
Publication of US20070278574A1 publication Critical patent/US20070278574A1/en
Priority to US12/036,396 priority patent/US7723729B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials

Definitions

  • This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a wafer that uses a layer to insulate a compound semiconductor from thermally-induced lattice mismatches with an underlying silicon (Si) substrate.
  • IC integrated circuit
  • Si silicon
  • Gallium nitride is a Group III/Group V compound semiconductor material with wide bandgap (3.4 eV), which has optoelectronic, as well as other applications. Like other Group III nitrides, GaN has a low sensitivity to ionizing radiation, and so, is useful in solar cells. GaN is also useful in the fabrication of blue light-emitting diodes (LEDs) and lasers. Unlike previous indirect bandgap devices (e.g., silicon carbide), GaN LEDs are bright enough for daylight applications. GaN devices also have application in high power and high frequency devices, such as power amplifiers.
  • LEDs blue light-emitting diodes
  • GaN LEDs are conventionally fabricated using a metalorganic chemical vapor deposition (MOCVD) for deposition on a sapphire substrate.
  • MOCVD metalorganic chemical vapor deposition
  • Zinc oxide and silicon carbide (SiC) substrate are also used due to their relatively small lattice constant mismatch.
  • SiC silicon carbide
  • these substrates are expensive to make, and their small size also drives fabrication costs.
  • the state-of-the-art sapphire wafer size is only about 4 inches.
  • GaN-on-Si device technology There are two fundamental problems associated with GaN-on-Si device technology. First, there is a lattice mismatch between Si and GaN. This problem is solved by using a buffer layer of AlN, InGaN, AlGaN, or the like, prior to the growth of GaN.
  • the buffer layer provides a transition region between the GaN and Si.
  • the present invention describes GaN grown on a Si wafer with a soft buried insulator to absorb the thermal mismatches.
  • the structure is similar in concept to a buried oxide layer (BOX) of a Si-on-insulator (SOI) wafer. That is, the so-called “thermally soft insulator” (TSI) isolates mechanical stresses between the GaN layer and the Si substrate, avoiding wafer deformation.
  • thermal insulator conventional boronphosphosilicate glass (BPSG) is used as the thermal insulator. At high wafer temperatures, the BPSG becomes mechanically soft, isolating the thermal expansion of the top GaN layer and the bottom Si substrate.
  • the temperature at which BPSG is soft can be adjusted, dependent upon the density of boron and phosphorous in the silicon oxide.
  • the BPSG flow temperature is about 700° C. and the mechanically soft temperature is lower than 600° C. Therefore, there is no mechanical stress when the wafer temperature is higher than 600° C.
  • a method for forming a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator.
  • the method forms a Si substrate, with a thermally soft insulator layer overlying the Si substrate.
  • a silicon oxide layer is formed immediately overlying the thermally soft insulator layer, a top Si layer overlies the silicon oxide, and a lattice mismatch buffer layer overlies the top Si layer.
  • a compound semiconductor layer is formed overlying the lattice mismatch buffer layer.
  • the thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor.
  • the thermally soft insulator may have a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.
  • the compound semiconductor-on-Si wafer is fabricated using donor and handle wafers.
  • the thermally soft insulator is deposited on the handle Si wafer top surface.
  • the donor Si wafer top surface is thermally oxidized and implanted with hydrogen ions.
  • the thermally soft insulator layer of the handle wafer is bonded to the silicon oxide layer of the donor wafer.
  • the bonded wafers are split along the implant layer, exposing the top Si layer, which is planarized.
  • boronsilicate glass (BSG), and phosphosilicate glass (PSG) may be used as the thermally soft insulator.
  • the compound semiconductor layer may be a material such as GaN, GaAs, GaAlN, or SiC.
  • the lattice mismatch buffer layer may be a material such as AlN, InGaN, or AlGaN.
  • FIG. 1 is a partial cross-sectional view of a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator.
  • FIG. 2 is a partial cross-sectional view of a variation of the compound semiconductor-on-Si TSI wafer of FIG. 1 .
  • FIG. 3 is a partial cross-sectional view of a variation of the compound semiconductor-on-Si TSI wafer of FIG. 2 .
  • FIGS. 4 through 6 depict steps in the fabrication of an exemplary GaN-on-Si wafer with a BPSG TSI.
  • FIG. 7 is a flowchart illustrating a method for forming a compound semiconductor-on-Si wafer with a thermally soft insulator.
  • FIG. 1 is a partial cross-sectional view of a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator.
  • the thermally soft insulated (TSI) wafer 100 comprises a Si substrate 102 , a thermally soft insulator layer 104 overlying the Si substrate 102 , and a compound semiconductor layer 106 overlying the thermally soft insulator layer 104 .
  • the thermally soft insulator 104 has a liquid phase temperature lower than the liquid phase temperatures of Si 102 or the compound semiconductor 106 .
  • the thermally soft insulator (TSI) layer 104 has a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.
  • the TSI insulator layer 104 may be considered to be mechanically soft at the flow temperature, soft enough to isolate any differences in thermal expansion between the Si substrate 102 and the compound semiconductor 106 . That is, the TSI layer 104 may be considered to be “soft” at the flow temperature.
  • the compound semiconductor layer 106 can be a material such as GaN, GaAs, GaAlN, or SiC. However, the basic principle of the invention can be applied to any wafer with a thermal mismatch issue between film layers. While the invention has practical application to Si substrates, it is not limited to any particular type of underlying substrate material.
  • FIG. 2 is a partial cross-sectional view of a first variation of the compound semiconductor-on-Si TSI wafer of FIG. 1 .
  • a first silicon oxide layer 200 immediately overlies the thermally soft insulator layer 104 .
  • the first silicon oxide layer 200 has a thickness 202 in the range of about 2 to 100 nm.
  • a top Si layer 204 immediately overlies the first silicon oxide layer 200 .
  • the top Si layer 204 has a thickness 206 in the range of about 5 and 20 nm.
  • the top Si layer 202 has a ⁇ 111> crystallographic orientation.
  • a lattice mismatch buffer layer 208 is interposed between the top Si layer 204 and the compound semiconductor layer 106 .
  • the lattice mismatch buffer layer 208 can be a material such as AlN, InGaN, or AlGaN. However, other materials could also be used that have a high tolerance to lattice mismatch.
  • the thermally soft insulator 104 may be a doped silicate glass material such as boronsilicate glass (BSG), phosphosilicate glass (PSG), or boronphosphosilicate glass (BPSG). As shown in FIG. 2 , the doped silicate glass material 104 has a thickness 210 in the range of about 50 to 1000 nanometers (nm). Other materials may also be used that have a relatively low flow temperature.
  • BSG boronsilicate glass
  • PSG phosphosilicate glass
  • BPSG boronphosphosilicate glass
  • the doped silicate glass material 104 has a thickness 210 in the range of about 50 to 1000 nanometers (nm). Other materials may also be used that have a relatively low flow temperature.
  • the doped silicate glass material is BPSG, then it includes phosphorus in the range of about 2 to 4 atomic percentage (at %) and boron in the range of about 3 to 7 at %. If the doped silicate glass is PSG, then it includes phosphorus in the range of about 5 to 9 at %. If BSG, the doped silicate glass includes boron in the range of about 5 to 8 at %.
  • the flow temperature of the TSI material can be varied by adjusting the above-mentioned doping ratios.
  • FIG. 3 is a partial cross-sectional view of a variation of the compound semiconductor-on-Si TSI wafer of FIG. 2 .
  • the top Si layer 204 includes Si islands 300 separated from adjacent Si islands by etched trenches (cavities) 302 in the top Si layer.
  • the trenches 302 may be filed with a material such as silicon oxide.
  • an optional second silicon oxide layer 304 may be interposed between the thermally soft insulator layer 104 and the Si substrate 102 . Alternately, this optional Si oxide layer may be used in the wafer of FIG. 2 .
  • FIGS. 4 through 6 depict steps in the fabrication of an exemplary GaN-on-Si wafer with a BPSG TSI.
  • FIG. 4 is a partial cross-sectional depicting a handle wafer prior to bonding.
  • the BPSG layer is similar to the conventional undoped silicon oxide BOX of a SOI wafer. While conventional SOI may be used as a TSI in some aspects, the BOX of a conventional SOI is undoped silicon oxide, which only becomes soft at temperatures higher than 1000° C. Lower TSI flow temperature can be achieved using a BPSG layer.
  • FIG. 5 is a partial cross-sectional view of a donor wafer ready for bonding.
  • the handle wafer can be any type of silicon substrate.
  • the donor wafer may be a ⁇ 111> oriented silicon substrate.
  • the size of the handle wafer is the same as that of the donor wafer.
  • a thin layer of thermal oxide is grown on the donor wafer.
  • the thickness of this thermal oxide can be from about 2 nm to 100 nm.
  • a thin layer of thermal oxide (2 nm to 100 nm) may also be grown onto the handle wafer.
  • BPSG with 2 at % to 4 at % of phosphorus, and 3 at % to 7 at % boron, is deposited onto the handle wafer.
  • the thickness of the BPSG layer can be 50 nm to 1000 nm.
  • the BPSG doping density may be lower at the bottom and the top surfaces of the film, with a maximum in the center portion of the film. If the GaN is formed by epitaxial (epi) growth in subsequent processes, this form of distribution is likely to occur, even the initial doping of the thermally soft insulator is uniform across the thickness of the film.
  • High energy hydrogen ions are implanted into the donor wafers for wafer splitting.
  • the donor wafer is bonded to the handle wafer, and the donor wafer is split away to expose the top Si layer.
  • FIG. 6 is a partial cross-sectional view wafer following the splitting process.
  • a chemical-mechanical polish (CMP) process is performed to planarize the top silicon layer.
  • the silicon thickness remaining after planarization may be 5 nm to 50 nm.
  • the top ⁇ 111> Si layer may be etched to form ⁇ 111> Si islands prior to the formation of the GaN and lattice mismatch buffer layer, in order to have better stress release effect.
  • the BPSG BOX SOI wafer may also used as substrate to grow any other compound material besides the GaN shown in this example.
  • FIG. 7 is a flowchart illustrating a method for forming a compound semiconductor-on-Si wafer with a thermally soft insulator. Although the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily dictate the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of maintaining a strict order of sequence.
  • the method starts at Step 700 .
  • Step 702 forms a Si substrate.
  • Step 704 forms a thermally soft insulator layer overlying the Si substrate.
  • Step 706 forms a compound semiconductor layer overlying the thermally soft insulator layer.
  • the compound semiconductor layer may be GaN, GaAs, GaAlN, or SiC.
  • the thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor.
  • Step 705 b forms a silicon oxide layer immediately overlying the thermally soft insulator layer.
  • Step 705 f forms a top Si layer immediately overlying the silicon oxide layer, and
  • Step 705 i forms a lattice mismatch buffer layer interposed between the top Si layer and the compound semiconductor layer.
  • the lattice mismatch buffer layer may be a material such as AlN, InGaN, or AlGaN.
  • Step 702 provides a Si handle wafer with a top surface
  • forming the thermally soft insulator layer in Step 704 includes depositing the thermally soft insulator overlying the Si handle wafer top surface.
  • the thermally soft insulator may have a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.
  • Step 703 thermally oxidizes the handle wafer top surface, prior to forming the thermally soft insulator layer.
  • Step 704 deposits the doped silicate glass material to a thickness in the range of about 50 to 1000 nanometers (nm).
  • forming BPSG may include substeps.
  • Step 704 a deposits silicate glass
  • Step 704 b dopes the silicate glass with phosphorus in the range of about 2 to 4 atomic percentage (at %) and boron in the range of about 3 to 7 at %.
  • PSG phosphosilicate glass
  • Step 704 b dopes the silicate glass with phosphorus in the range of about 5 to 9 at %.
  • Step 704 b dopes the silicate glass with boron in the range of about 5 to 8 at %.
  • Step 705 a provides a donor Si wafer with a top surface
  • forming the silicon oxide layer in Step 705 b includes thermally oxidizes the donor wafer top surface.
  • the thermally oxidized layer may have a thickness in the range of about 2 to 100 nm.
  • the donor wafer may have a ⁇ 111> crystallographic orientation.
  • Step 705 c implants the donor wafer with hydrogen ions, forming an implant layer.
  • Step 705 d bonds the thermally soft insulator layer of the handle wafer to the silicon oxide layer of the donor wafer.
  • Step 705 e splits the bonded wafers along the implant layer, exposing the top Si layer.
  • forming the top Si layer in Step 705 f includes planarizing the top Si layer.
  • the planarized thickness is in the range of about 5 and 20 nm.
  • Step 705 g etches the top Si layer.
  • Step 705 h forms Si islands separated from adjacent Si islands by trenches in the top Si layer.
  • a compound semiconductor-on-Si substrate with a thermally soft insulator has been provided, along with a corresponding method of fabrication. Examples of specific layer orderings and materials have been given to illustrate the invention. Although the invention has been presented in the context of Si and GaN materials, the general principles are applicable to the thermal expansion mismatch between other materials. However, the invention is not limited to merely these examples. Other variations and embodiments of the invention will occur to those skilled in the art.

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Abstract

A method is provided for forming a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator. The method forms a Si substrate, with a thermally soft insulator layer overlying the Si substrate. A silicon oxide layer is formed immediately overlying the thermally soft insulator layer, a top Si layer overlies the silicon oxide, and a lattice mismatch buffer layer overlies the top Si layer. A compound semiconductor layer is formed overlying the lattice mismatch buffer layer. The thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor. For example, the thermally soft insulator may have a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a wafer that uses a layer to insulate a compound semiconductor from thermally-induced lattice mismatches with an underlying silicon (Si) substrate.
  • 2. Description of the Related Art
  • Gallium nitride (GaN) is a Group III/Group V compound semiconductor material with wide bandgap (3.4 eV), which has optoelectronic, as well as other applications. Like other Group III nitrides, GaN has a low sensitivity to ionizing radiation, and so, is useful in solar cells. GaN is also useful in the fabrication of blue light-emitting diodes (LEDs) and lasers. Unlike previous indirect bandgap devices (e.g., silicon carbide), GaN LEDs are bright enough for daylight applications. GaN devices also have application in high power and high frequency devices, such as power amplifiers.
  • GaN LEDs are conventionally fabricated using a metalorganic chemical vapor deposition (MOCVD) for deposition on a sapphire substrate. Zinc oxide and silicon carbide (SiC) substrate are also used due to their relatively small lattice constant mismatch. However, these substrates are expensive to make, and their small size also drives fabrication costs. For example, the state-of-the-art sapphire wafer size is only about 4 inches. To minimize costs, it would be desirable to integrate GaN device fabrication into more conventional Si-based IC processes, which has the added cost benefit of using large-sized (Si) wafers.
  • There are two fundamental problems associated with GaN-on-Si device technology. First, there is a lattice mismatch between Si and GaN. This problem is solved by using a buffer layer of AlN, InGaN, AlGaN, or the like, prior to the growth of GaN. The buffer layer provides a transition region between the GaN and Si.
  • However, an additional and more serious problem exists, as there is also a thermal mismatch between Si and GaN. The thermal expansion coefficient mismatch between GaN and Si is about 54%. Although the lattice buffer layer may absorb part of the thermal mismatch, the necessity of using temperatures higher than 1000° C. during epi growth and other device fabrication may cause wafer deformation. The wafer deformation can be reduced with a very slow rate of heating and cooling during wafer processing but this adds additional cost to the process, and doesn't completely solve the thermal stress and wafer deformation issues.
  • It would be advantageous if the thermal mismatch problem associated with GaN-on-Si device technology could be practically eliminated without using slow heating and cooling processes.
    • SUMMARY OF THE INVENTION
  • The present invention describes GaN grown on a Si wafer with a soft buried insulator to absorb the thermal mismatches. The structure is similar in concept to a buried oxide layer (BOX) of a Si-on-insulator (SOI) wafer. That is, the so-called “thermally soft insulator” (TSI) isolates mechanical stresses between the GaN layer and the Si substrate, avoiding wafer deformation. In one aspect, conventional boronphosphosilicate glass (BPSG) is used as the thermal insulator. At high wafer temperatures, the BPSG becomes mechanically soft, isolating the thermal expansion of the top GaN layer and the bottom Si substrate. The temperature at which BPSG is soft can be adjusted, dependent upon the density of boron and phosphorous in the silicon oxide. With 4 atomic percentage (at %) of P, and 7 at % of B, the BPSG flow temperature is about 700° C. and the mechanically soft temperature is lower than 600° C. Therefore, there is no mechanical stress when the wafer temperature is higher than 600° C.
  • Accordingly, a method is provided for forming a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator. The method forms a Si substrate, with a thermally soft insulator layer overlying the Si substrate. A silicon oxide layer is formed immediately overlying the thermally soft insulator layer, a top Si layer overlies the silicon oxide, and a lattice mismatch buffer layer overlies the top Si layer. A compound semiconductor layer is formed overlying the lattice mismatch buffer layer. The thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor. For example, the thermally soft insulator may have a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.
  • More explicitly, the compound semiconductor-on-Si wafer is fabricated using donor and handle wafers. The thermally soft insulator is deposited on the handle Si wafer top surface. The donor Si wafer top surface is thermally oxidized and implanted with hydrogen ions. The thermally soft insulator layer of the handle wafer is bonded to the silicon oxide layer of the donor wafer. The bonded wafers are split along the implant layer, exposing the top Si layer, which is planarized.
  • Besides BPSG, boronsilicate glass (BSG), and phosphosilicate glass (PSG) may be used as the thermally soft insulator. The compound semiconductor layer may be a material such as GaN, GaAs, GaAlN, or SiC. The lattice mismatch buffer layer may be a material such as AlN, InGaN, or AlGaN.
  • Additional details of the above-described method, and compound semiconductor-on-silicon wafer with a thermally soft insulator, are presented below.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a partial cross-sectional view of a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator.
  • FIG. 2 is a partial cross-sectional view of a variation of the compound semiconductor-on-Si TSI wafer of FIG. 1.
  • FIG. 3 is a partial cross-sectional view of a variation of the compound semiconductor-on-Si TSI wafer of FIG. 2.
  • FIGS. 4 through 6 depict steps in the fabrication of an exemplary GaN-on-Si wafer with a BPSG TSI.
  • FIG. 7 is a flowchart illustrating a method for forming a compound semiconductor-on-Si wafer with a thermally soft insulator.
    •  DETAILED DESCRIPTION
  • FIG. 1 is a partial cross-sectional view of a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator. In a simple aspect, the thermally soft insulated (TSI) wafer 100 comprises a Si substrate 102, a thermally soft insulator layer 104 overlying the Si substrate 102, and a compound semiconductor layer 106 overlying the thermally soft insulator layer 104. The thermally soft insulator 104 has a liquid phase temperature lower than the liquid phase temperatures of Si 102 or the compound semiconductor 106.
  • The thermally soft insulator (TSI) layer 104 has a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature. The TSI insulator layer 104 may be considered to be mechanically soft at the flow temperature, soft enough to isolate any differences in thermal expansion between the Si substrate 102 and the compound semiconductor 106. That is, the TSI layer 104 may be considered to be “soft” at the flow temperature. The compound semiconductor layer 106 can be a material such as GaN, GaAs, GaAlN, or SiC. However, the basic principle of the invention can be applied to any wafer with a thermal mismatch issue between film layers. While the invention has practical application to Si substrates, it is not limited to any particular type of underlying substrate material.
  • FIG. 2 is a partial cross-sectional view of a first variation of the compound semiconductor-on-Si TSI wafer of FIG. 1. In this aspect, a first silicon oxide layer 200 immediately overlies the thermally soft insulator layer 104. In one aspect, the first silicon oxide layer 200 has a thickness 202 in the range of about 2 to 100 nm. A top Si layer 204 immediately overlies the first silicon oxide layer 200. The top Si layer 204 has a thickness 206 in the range of about 5 and 20 nm. In one aspect, the top Si layer 202 has a <111> crystallographic orientation. A lattice mismatch buffer layer 208 is interposed between the top Si layer 204 and the compound semiconductor layer 106. The lattice mismatch buffer layer 208 can be a material such as AlN, InGaN, or AlGaN. However, other materials could also be used that have a high tolerance to lattice mismatch.
  • With respect to both FIGS. 1 and 2, the thermally soft insulator 104 may be a doped silicate glass material such as boronsilicate glass (BSG), phosphosilicate glass (PSG), or boronphosphosilicate glass (BPSG). As shown in FIG. 2, the doped silicate glass material 104 has a thickness 210 in the range of about 50 to 1000 nanometers (nm). Other materials may also be used that have a relatively low flow temperature.
  • If the doped silicate glass material is BPSG, then it includes phosphorus in the range of about 2 to 4 atomic percentage (at %) and boron in the range of about 3 to 7 at %. If the doped silicate glass is PSG, then it includes phosphorus in the range of about 5 to 9 at %. If BSG, the doped silicate glass includes boron in the range of about 5 to 8 at %. The flow temperature of the TSI material can be varied by adjusting the above-mentioned doping ratios.
  • FIG. 3 is a partial cross-sectional view of a variation of the compound semiconductor-on-Si TSI wafer of FIG. 2. In this aspect, the top Si layer 204 includes Si islands 300 separated from adjacent Si islands by etched trenches (cavities) 302 in the top Si layer. The trenches 302 may be filed with a material such as silicon oxide. In one aspect as shown, an optional second silicon oxide layer 304 may be interposed between the thermally soft insulator layer 104 and the Si substrate 102. Alternately, this optional Si oxide layer may be used in the wafer of FIG. 2.
    • Functional Description
  • FIGS. 4 through 6 depict steps in the fabrication of an exemplary GaN-on-Si wafer with a BPSG TSI. FIG. 4 is a partial cross-sectional depicting a handle wafer prior to bonding. The BPSG layer is similar to the conventional undoped silicon oxide BOX of a SOI wafer. While conventional SOI may be used as a TSI in some aspects, the BOX of a conventional SOI is undoped silicon oxide, which only becomes soft at temperatures higher than 1000° C. Lower TSI flow temperature can be achieved using a BPSG layer.
  • FIG. 5 is a partial cross-sectional view of a donor wafer ready for bonding. First, the handle wafer and a donor wafer are cleaned. The handle wafer can be any type of silicon substrate. The donor wafer may be a <111> oriented silicon substrate. The size of the handle wafer is the same as that of the donor wafer.
  • A thin layer of thermal oxide is grown on the donor wafer. The thickness of this thermal oxide can be from about 2 nm to 100 nm. Optionally, a thin layer of thermal oxide (2 nm to 100 nm) may also be grown onto the handle wafer.
  • BPSG, with 2 at % to 4 at % of phosphorus, and 3 at % to 7 at % boron, is deposited onto the handle wafer. The thickness of the BPSG layer can be 50 nm to 1000 nm. The BPSG doping density may be lower at the bottom and the top surfaces of the film, with a maximum in the center portion of the film. If the GaN is formed by epitaxial (epi) growth in subsequent processes, this form of distribution is likely to occur, even the initial doping of the thermally soft insulator is uniform across the thickness of the film.
  • High energy hydrogen ions are implanted into the donor wafers for wafer splitting. The donor wafer is bonded to the handle wafer, and the donor wafer is split away to expose the top Si layer.
  • FIG. 6 is a partial cross-sectional view wafer following the splitting process. A chemical-mechanical polish (CMP) process is performed to planarize the top silicon layer. The silicon thickness remaining after planarization may be 5 nm to 50 nm.
  • Optionally, the top <111> Si layer may be etched to form <111> Si islands prior to the formation of the GaN and lattice mismatch buffer layer, in order to have better stress release effect.
  • Any conventional method may be used to grow the lattice mismatch buffer layer and the GaN layer. The BPSG BOX SOI wafer may also used as substrate to grow any other compound material besides the GaN shown in this example.
  • FIG. 7 is a flowchart illustrating a method for forming a compound semiconductor-on-Si wafer with a thermally soft insulator. Although the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily dictate the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of maintaining a strict order of sequence. The method starts at Step 700.
  • Step 702 forms a Si substrate. Step 704 forms a thermally soft insulator layer overlying the Si substrate. Step 706 forms a compound semiconductor layer overlying the thermally soft insulator layer. The compound semiconductor layer may be GaN, GaAs, GaAlN, or SiC. The thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor.
  • In one aspect, Step 705 b forms a silicon oxide layer immediately overlying the thermally soft insulator layer. Step 705 f forms a top Si layer immediately overlying the silicon oxide layer, and Step 705 i forms a lattice mismatch buffer layer interposed between the top Si layer and the compound semiconductor layer. For example, the lattice mismatch buffer layer may be a material such as AlN, InGaN, or AlGaN.
  • In one aspect, Step 702 provides a Si handle wafer with a top surface, and forming the thermally soft insulator layer in Step 704 includes depositing the thermally soft insulator overlying the Si handle wafer top surface. The thermally soft insulator may have a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature. In one aspect, Step 703 thermally oxidizes the handle wafer top surface, prior to forming the thermally soft insulator layer.
  • Some examples of a thermally soft insulator include boronsilicate glass (BSG), phosphosilicate glass (PSG), and boronphosphosilicate glass (BPSG). In one aspect, Step 704 deposits the doped silicate glass material to a thickness in the range of about 50 to 1000 nanometers (nm). For example, forming BPSG may include substeps. Step 704 a deposits silicate glass, and Step 704 b dopes the silicate glass with phosphorus in the range of about 2 to 4 atomic percentage (at %) and boron in the range of about 3 to 7 at %. Alternately, if PSG is formed, Step 704 b dopes the silicate glass with phosphorus in the range of about 5 to 9 at %. If BSG is formed, Step 704 b dopes the silicate glass with boron in the range of about 5 to 8 at %.
  • In another aspect, Step 705 a provides a donor Si wafer with a top surface, and forming the silicon oxide layer in Step 705 b includes thermally oxidizes the donor wafer top surface. For example, the thermally oxidized layer may have a thickness in the range of about 2 to 100 nm. In one aspect, the donor wafer may have a <111> crystallographic orientation.
  • Step 705 c implants the donor wafer with hydrogen ions, forming an implant layer. Step 705 d bonds the thermally soft insulator layer of the handle wafer to the silicon oxide layer of the donor wafer. Step 705 e splits the bonded wafers along the implant layer, exposing the top Si layer. Then, forming the top Si layer in Step 705 f includes planarizing the top Si layer. In one aspect, the planarized thickness is in the range of about 5 and 20 nm. In another aspect following the formation of the top Si layer, Step 705 g etches the top Si layer. Step 705 h forms Si islands separated from adjacent Si islands by trenches in the top Si layer.
  • A compound semiconductor-on-Si substrate with a thermally soft insulator has been provided, along with a corresponding method of fabrication. Examples of specific layer orderings and materials have been given to illustrate the invention. Although the invention has been presented in the context of Si and GaN materials, the general principles are applicable to the thermal expansion mismatch between other materials. However, the invention is not limited to merely these examples. Other variations and embodiments of the invention will occur to those skilled in the art.

Claims (31)

1. A method for forming a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator, the method comprising:
forming a Si substrate;
forming a thermally soft insulator layer overlying the Si substrate;
forming a compound semiconductor layer overlying the thermally soft insulator layer; and,
wherein the thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor.
2. The method of claim 1 further comprising:
forming a silicon oxide layer immediately overlying the thermally soft insulator layer;
forming a top Si layer immediately overlying the silicon oxide layer; and,
forming a lattice mismatch buffer layer interposed between the top Si layer and the compound semiconductor layer.
3. The method of claim 2 wherein providing the substrate includes providing a Si handle wafer with a top surface;
wherein forming the thermally soft insulator layer includes depositing the thermally soft insulator overlying the Si handle wafer top surface.
4. The method of claim 1 wherein forming the thermally soft insulator includes depositing a material having a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.
5. The method of claim 4 wherein depositing the thermally soft insulator includes forming a doped silicate glass material selected from a group consisting of boronsilicate glass (BSG), phosphosilicate glass (PSG), and boronphosphosilicate glass (BPSG).
6. The method of claim 5 wherein depositing the doped silicate glass material includes forming the doped silicate glass material to a thickness in the range of about 50 to 1000 nanometers (nm).
7. The method of claim 5 wherein forming BPSG includes:
depositing silicate glass; and,
doping the silicate glass with phosphorus in the range of about 2 to 4 atomic percentage (at %) and boron in the range of about 3 to 7 at %.
8. The method of claim 5 wherein forming PSG includes:
depositing silicate glass; and,
doping the silicate glass with phosphorus in the range of about 5 to 9 at %.
9. The method of claim 5 wherein forming BSG includes:
depositing silicate glass; and,
doping the silicate glass with boron in the range of about 5 to 8 at %.
10. The method of claim 3 further comprising:
prior to forming the thermally soft insulator layer, thermally oxidizing the handle wafer top surface.
11. The method of claim 3 further comprising:
providing a donor Si wafer with a top surface;
wherein forming the silicon oxide layer includes thermally oxidizing the donor wafer top surface;
the method further comprising:
implanting the donor wafer with hydrogen ions, forming an j implant layer;
bonding the thermally soft insulator layer of the handle wafer to the silicon oxide layer of the donor wafer;
splitting the bonded wafers along the implant layer, exposing the top Si layer; and,
wherein forming the top Si layer includes planarizing the top Si layer.
12. The method of claim 11 wherein providing the donor Si wafer includes providing a donor Si wafer having a <111> crystallographic orientation.
13. The method of claim 11 wherein thermally oxidizing the donor wafer top surface includes forming a silicon oxide layer having a thickness in the range of about 2 to 100 nm.
14. The method of claim 2 wherein forming the compound semiconductor layer includes forming a compound semiconductor layer from a material selected from a group consisting of GaN, GaAs, GaAlN, and SiC.
15. The method of claim 2 wherein forming the lattice mismatch buffer layer includes forming the lattice mismatch buffer layer from a material selected from a group consisting of AlN, InGaN, and AlGaN.
16. The method of claim 2 further comprising:
following the formation of the top Si layer, etching the top Si layer; and,
forming Si islands separated from adjacent Si islands by trenches in the top Si layer.
17. A compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator, the thermally soft insulated wafer comprising:
a Si substrate;
a thermally soft insulator layer overlying the Si substrate;
a compound semiconductor layer overlying the thermally soft insulator layer; and,
wherein the thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor.
18. The thermally soft insulator wafer of claim 17 further comprising:
a first silicon oxide layer immediately overlying the thermally soft insulator layer;
a top Si layer immediately overlying the first silicon oxide layer; and,
a lattice mismatch buffer layer interposed between the top Si layer and the compound semiconductor layer.
19. The thermally soft insulator wafer of claim 18 wherein the thermally soft insulator layer has a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.
20. The thermally soft insulator wafer of claim 19 wherein the thermally soft insulator is a doped silicate glass material selected from a group consisting of boronsilicate glass (BSG), phosphosilicate glass (PSG), and boronphosphosilicate glass (BPSG).
21. The thermally soft insulator wafer of claim 20 wherein the doped silicate glass material has a thickness in the range of about 50 to 1000 nanometers (nm).
22. The thermally soft insulator wafer of claim 20 wherein the doped silicate glass material is BPSG, including phosphorus in the range of about 2 to 4 atomic percentage (at %) and boron in the range of about 3 to 7 at %.
23. The thermally soft insulator wafer of claim 20 wherein the doped silicate glass is PSG, including phosphorus in the range of about 5 to 9 at %.
24. The thermally soft insulator wafer of claim 20 wherein the doped silicate glass is BSG, including boron in the range of about 5 to 8 at %.
25. The thermally soft insulator wafer of claim 18 further comprising:
a second silicon oxide layer interposed between the thermally soft insulator layer and the Si substrate.
26. The thermally soft insulator wafer of claim 18 wherein the top Si layer has a thickness in the range of about 5 and 20 nm.
27. The thermally soft insulator wafer of claim 18 wherein the top Si layer has a <111> crystallographic orientation.
28. The thermally soft insulator wafer of claim 18 wherein the first silicon oxide layer has a thickness in the range of about 2 to 100 nm.
29. The thermally soft insulator wafer of claim 17 wherein the compound semiconductor layer is a material selected from a group consisting of GaN, GaAs, GaAlN, and SiC.
30. The thermally soft insulator wafer of claim 18 wherein the lattice mismatch buffer layer is a material selected from a group consisting of AlN, InGaN, and AlGaN.
31. The thermally soft insulator wafer of claim 18 wherein the top Si layer includes Si islands separated from adjacent Si islands by trenches in the top Si layer.
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