DE3485592D1 - Integrierte halbleiterschaltungsanordnung. - Google Patents

Integrierte halbleiterschaltungsanordnung.

Info

Publication number: DE3485592D1
Authority: DE; Germany
Prior art keywords: circuit arrangement; semiconductor circuit; integrated semiconductor; integrated; arrangement
Prior art date: 1983-12-14
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE8484308703T

Other languages

English (en)

Inventor

Tomoji Takada

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Toshiba Corp

Original Assignee

Toshiba Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1983-12-14

Filing date

1984-12-13

Publication date

1992-04-23

1984-12-13 Application filed by Toshiba Corp filed Critical Toshiba Corp

1992-04-23 Application granted granted Critical

1992-04-23 Publication of DE3485592D1 publication Critical patent/DE3485592D1/de

2004-12-14 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Static Random-Access Memory (AREA)

DE8484308703T 1983-12-14 1984-12-13 Integrierte halbleiterschaltungsanordnung. Expired - Lifetime DE3485592D1 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP58235475A JPS60127598A (ja)	1983-12-14	1983-12-14	半導体集積回路装置

Publications (1)

Publication Number	Publication Date
DE3485592D1 true DE3485592D1 (de)	1992-04-23

Family

ID=16986618

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE8484308703T Expired - Lifetime DE3485592D1 (de)	1983-12-14	1984-12-13	Integrierte halbleiterschaltungsanordnung.

Country Status (4)

Country	Link
US (1)	US4667310A (de)
EP (1)	EP0145497B1 (de)
JP (1)	JPS60127598A (de)
DE (1)	DE3485592D1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS60236187A (ja) *	1984-05-08	1985-11-22	Nec Corp	多ポ−トレジスタセル
FR2595859B1 (fr) *	1986-03-14	1988-05-13	Radiotechnique Compelec	Memoire avec tampon amplificateur
JP2748562B2 (ja) *	1988-07-13	1998-05-06	セイコーエプソン株式会社	画像処理装置
US5422857A (en) *	1989-11-21	1995-06-06	Matsushita Electric Industrial Co., Ltd.	Semiconductor memory unit having overlapping addresses
DE68922738T2 (de) *	1989-12-23	1996-01-25	Ibm	Hochintegrierter Halbleiterspeicher mit Mehrfachzugang.
US5426610A (en) *	1990-03-01	1995-06-20	Texas Instruments Incorporated	Storage circuitry using sense amplifier with temporary pause for voltage supply isolation
JPH0485788A (ja) *	1990-07-27	1992-03-18	Toshiba Corp	多ポートキャッシュメモリ
JPH04111297A (ja) *	1990-08-30	1992-04-13	Nippon Steel Corp	スタティック・ランダム・アクセス・メモリセル
JPH05151778A (ja) *	1991-06-05	1993-06-18	Mitsubishi Electric Corp	スタテイツクランダムアクセスメモリおよびその制御方法
JPH052888A (ja) *	1991-06-27	1993-01-08	Kawasaki Steel Corp	ゲートアレイ用メモリセル回路
JP3153568B2 (ja) *	1991-07-03	2001-04-09	株式会社東芝	マルチポートｒａｍ用メモリセル及びマルチポートｒａｍ
JP2667941B2 (ja) *	1992-09-17	1997-10-27	三菱電機株式会社	メモリセル回路
DE19737611C2 (de) *	1997-08-28	2002-09-26	Infineon Technologies Ag	Fuse-Anordnung für Halbleiterspeichervorrichtung
US6198305B1 (en)	1998-03-24	2001-03-06	Cypress Semiconductor Corp.	Reduced area product-term array
US6055177A (en) *	1998-06-26	2000-04-25	Cypress Semiconductor Corp.	Memory cell
US6675187B1 (en) *	1999-06-10	2004-01-06	Agere Systems Inc.	Pipelined linear array of processor elements for performing matrix computations
JP3520283B2 (ja)	2002-04-16	2004-04-19	沖電気工業株式会社	半導体記憶装置
JP4279620B2 (ja) *	2003-07-11	2009-06-17	Ｏｋｉセミコンダクタ株式会社	レベルシフト回路
JP2007172813A (ja) *	2005-11-25	2007-07-05	Semiconductor Energy Lab Co Ltd	半導体記憶装置及び半導体記憶装置の動作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US3493786A (en) *	1967-05-02	1970-02-03	Rca Corp	Unbalanced memory cell
US3968480A (en) *	1974-04-25	1976-07-06	Honeywell Inc.	Memory cell
JPS5825970B2 (ja) *	1976-10-01	1983-05-31	三菱電機株式会社	液温検知装置
US4070657A (en) *	1977-01-03	1978-01-24	Honeywell Information Systems Inc.	Current mode simultaneous dual-read/single-write memory device
JPS5578561A (en) *	1978-12-08	1980-06-13	Fujitsu Ltd	Master-slice lsi circuit device
JPS57113482A (en) *	1980-12-29	1982-07-14	Seiko Epson Corp	Semiconductor storage device
US4412143A (en) *	1981-03-26	1983-10-25	Ncr Corporation	MOS Sense amplifier
JPS58199539A (ja) *	1982-05-17	1983-11-19	Hitachi Ltd	マスタ−スライス方式の半導体集積回路装置
JPS5960793A (ja) *	1982-09-30	1984-04-06	Fujitsu Ltd	半導体メモリ

1983
- 1983-12-14 JP JP58235475A patent/JPS60127598A/ja active Granted
1984
- 1984-12-13 EP EP84308703A patent/EP0145497B1/de not_active Expired - Lifetime
- 1984-12-13 US US06/681,485 patent/US4667310A/en not_active Expired - Lifetime
- 1984-12-13 DE DE8484308703T patent/DE3485592D1/de not_active Expired - Lifetime

Also Published As

Publication number	Publication date
EP0145497B1 (de)	1992-03-18
US4667310A (en)	1987-05-19
JPH03715B2 (de)	1991-01-08
JPS60127598A (ja)	1985-07-08
EP0145497A2 (de)	1985-06-19
EP0145497A3 (en)	1988-08-31

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Legal Events

Date	Code	Title
1993-04-15	8364	No opposition during term of opposition
1999-02-25	8320	Willingness to grant licences declared (paragraph 23)
2002-11-07	8339	Ceased/non-payment of the annual fee