CN1912849A - Chip dynamic tracing method of microprocessor - Google Patents

Abstract

The invention relates to an on-chip dynamic tracking method of a microprocessor. This method uses an on-chip dynamic tracking module (On-Chip Tracer: OCT) integrated in the processor to set certain positions in the program execution process as observation points, and then perform information on the internal registers specified at these observation points. Tracking, logging and real-time output. The method of the invention can be applied to the field of 8051 series microprocessors, and can also be applied to the fields of other microprocessors.

Description

On-chip Dynamic Tracking Method of Microprocessor

technical field

The invention relates to an on-chip dynamic tracking method of a microprocessor, which can be applied to 8051 series single-chip microprocessors, and can also be applied to other microprocessors and microprocessor fields.

Background technique

Dynamic Trace (Dynamic Trace) refers to the process of recording the trajectory information of program operation in real time, and transmitting this information to an external debugging tool for analysis and debugging by some means. In the debugging and development process of embedded systems with microprocessors as the core, in order to facilitate the capture of high-speed signals and debug the processor, such as checking, recovering, and modifying according to the program execution history, it is necessary to record the high-speed running time of the processor. traces of. Therefore, in most devices such as logic analyzers and in-circuit emulators, there are tracking components used to dynamically track the running track of the processor, which are used to monitor various internal information of the processor, so that the debugger can easily detect the program. Execute the process, find program errors, reconstruct the program running track, etc. However, in the common practice of realizing dynamic tracking, a large-capacity memory is required to temporarily store various internal information of the processor being tracked. Therefore, for on-chip dynamic tracking, integrating a memory for dynamic tracking inside the processor will increase design difficulty and production cost.

Contents of the invention

The object of the present invention is to provide a dynamic tracking method on a microprocessor chip. Through an independent on-chip trace module (On-Chip Tracer: OCT) integrated inside the processor, some positions that the debugger cares about during program execution can be set as watchpoints (Watchpoint), and the information of these positions can be tracked , recording and real-time output to achieve the purpose of dynamic tracking. Moreover, the whole process does not need a special tracking buffer unit, and only a small number of registers can meet the temporary storage requirements of data.

For achieving the above object, design of the present invention is as follows:

Construct an on-chip dynamic tracking module (On-Chip Tracer: OCT) integrated in the processor, through this module, certain positions in the program execution process are marked as observation points, and then during the program execution, each instruction The address of the watchpoint is compared with these watchpoints to detect watchpoints. If an observation point is detected, the CPU suspends the operation and waits for the OCT module to serially output the information of the internal register specified at the observation point to an external debugging tool for analysis. If the data output is complete, the processor is notified to resume the execution of the program automatically. If the next observation point is encountered, the previous tracking, recording and output process is repeated. This goes on and on until the execution of the program is completed or the debugger suspends or terminates the current dynamic tracking process.

According to above-mentioned design, the present invention adopts following technical scheme:

A kind of on-chip dynamic tracking method of microprocessor is characterized in that by an on-chip dynamic tracking module (OCT), some positions in the program execution process are set as watchpoints (Watchpoint), and then the specified internal Register information is tracked, recorded and output in real time; the specific steps are:

a. Set an asynchronous serial transceiver sub-module to realize the communication between the OCT module and the outside of the processor;

b. Set a debug command register DBGCMD to store the dynamic tracking debug command sent by the debugger to the OCT module;

c. setting n observation point address registers WPi (i=0～n-1), to store the head address of the program that the debugged is set as the observation point;

d. Set an internal register selection signal register SFR_SEL to store the selection signal of the internal register tracked and recorded at each observation point;

e. Set a current instruction first address register PCC to automatically store the first address of the instruction currently being executed by the CPU;

f. Start the dynamic tracking process through the "start dynamic tracking command", and then during the dynamic tracking process, the OCT module performs dynamic tracking operations according to the situation and sets related signals.

The above method of setting an asynchronous serial transceiver sub-module is as follows:

The serial transceiver sub-module adopts a half-duplex asynchronous serial communication mode, and performs serial communication with the outside of the processor through a signal line, and sending and receiving are two independent processes. The main purpose of the receiving part is to receive various debugging commands issued by the debugging tool, as well as the data and program addresses related to each command, and the purpose of sending is to serially output the contents of the selected internal registers at each observation point . At the same time, the data frame format of 1 stop bit (1 level) + valid data bit + 1 start bit (0 level) is adopted in both receiving and sending processes (see Figure 2(a) and Figure 3 respectively).

Some signals and registers related to serial communication are defined as follows (see Figure 4):

a.NEA: The external pin of the asynchronous serial transceiver sub-module communicates with the outside of the processor. Inside the OCT module, it is divided into NEA_I (serial data input terminal) and NEA_O (serial data output terminal);

b. RX_CLK/TX_CLK: They are the sampling clocks when the asynchronous serial transceiver sub-module receives and sends serial data, and the frequency is 1/100 of the processor clock frequency;

c. RX_SHIFT/TX_SHIFT: They are the serial shift pulses when the asynchronous serial transceiver sub-module receives and sends data respectively, and the frequency is 1/8 of RX_CLK/TX_CLK. Therefore, the baud rate of communication is the speed of the processor 1/800;

d. RX_SHIFTER: Receive shift register, which receives various debugging commands and related data and addresses. The data format is shown in Figure 2;

e.TX_SHIFTER_1: Transmit shift register, which transmits the data of the internal register at each observation point and the address of the observation point. The data format is shown in Figure 3.

The above method of setting a debug command register DBGCMD is as follows:

Define DBGCMD as a 4-bit register, which is used to store the binary code of the debugging command issued by the debugging tool, and decode the received debugging command into a corresponding control signal.

DBGCMD can store 8 commands related to dynamic tracking, see Table 1. Among them, other binary codes not used in DBGCMD are temporarily reserved and can be expanded in the future.

Table 1 Dynamic tracking commands stored in DBGCMD binary code command symbol Functional description 0000 DBG_RST Reset the entire microprocessor system in debug state 1010 WP_SET Set an instruction in the program as a watchpoint 1011 WP_REMOVE remove a specified watchpoint 1100 WP_CLR Clear all watchpoints at once 0011 SFR_SET Set the internal registers that need to be tracked and logged at each watchpoint 1101 D_DBG Start dynamic tracking process 1110 D_DBG_PAUSE Pause dynamic tracking process 1111 D_DBG_Stop Stop dynamic tracking process

The above method of setting n observation point address registers WPi (i=0～n-1) is as follows:

Define WPi (i=0˜n−1) as n 16-bit registers, which store the first address of the instruction set as the observation point. After the system is reset, the values of the n observation point address registers are all high resistance values.

The OCT module sets or clears watchpoints according to the following three situations:

a) If the WP_SET command is received, the OCT module will store the 16-bit address received together with the command as the address of an observation point in a WPi register (the order of storage starts from WP0 and ends at WPn-1). If the debugger sets more than n watch points, the address of the n+1 watch point will cover the first watch point, the n+2 watch point will cover the second watch point, and so on.

b) If the WP_REMOVE command is received, the OCT module will compare the 16-bit address received at this time with the address previously set as the observation point, and then remove the observation point that matches the address.

c) If the WP_CLR command is received, the OCT module will clear all the observation points at one time, and the data in the observation point registers after being cleared are all high resistance values.

The method of setting an internal register selection signal register SFR_SEL above is:

Define SFR_SEL as an n-bit register, each of which corresponds to n commonly used internal registers in sequence, and its definition is as follows: Internal register n select signal ... Internal register 2 select signal Internal register 1 select signal

When the internal register selection command SFR_SET is received, the OCT module stores the n-bit register selection signal (see Figure 2(d)) received together with the SFR_SET command in SFR_SEL. At this time, if a certain bit of SFR_SEL is 1, the internal register corresponding to this bit will be tracked, and the content of the internal register will be output at each observation point. Conversely, if this bit is 0, then the corresponding internal register does not need to be tracked and recorded.

The above method of setting a current instruction first address register PCC is as follows:

Define PCC as a 16-bit address register, which stores the 16-bit first address of the instruction currently being executed. Its value is automatically set by the OCT module. After system reset, the value of PCC is 00h.

The specific method of setting the PCC register is: in the process of program execution, in the first clock cycle of each instruction, send the value of the program pointer pointing to the instruction to the PCC register. PCC will keep this address until the first clock cycle of the next instruction arrives, and it will be updated to a new address.

There are three types of dynamic tracking operations according to the situation in the above dynamic tracking process:

a. If the OCT module does not receive other control commands after the dynamic tracking process is started, the OCT module will automatically compare the contents of WPi (i=0～n-1) and PCC to carry out the observation point during the program execution process detection. If an observation point is detected, the OCT module serially outputs the information of the selected internal register at the observation point to an external debugging tool for analysis.

The specific steps to detect the observation point and output the internal register information are as follows:

a) WP_MATCH: observation point matching signal, active high;

WP_STOP: watch point match stop signal;

See Figure 7 for the method of detecting observation points. During program execution, at the third clock cycle of each instruction, the contents of n observation point address registers WPi (i=0~n-1) are compared with the current instruction first address register PCC respectively. As long as the content of a watchpoint address register exactly matches the content of the PCC, it means that a watchpoint has been detected, so the WP_MATCH signal is immediately valid. After executing the instruction at the observation point, the CPU needs to execute another no-operation instruction NOP to ensure the integrity of the instruction execution process. Then, in the second clock cycle of the NOP instruction, the WP_STOP signal is valid, and at the same time, the OCT module stores the values of all selected internal registers in the corresponding temporary registers, and those internal registers that are not selected The contents of the corresponding scratch registers are all 0. In the next clock cycle immediately after the WP_STOP signal is valid, the OCT module enters the preparation stage for serial transmission.

b) TX_SFR_DATA: a register that stores n internal register data and the first address of the current observation point;

TX_SHIFTER_1: transmit shift register;

TX_BEGIN: send start signal;

CPU_STOP: The signal to stop the CPU working clock.

In the preparation stage of serial transmission, that is, the third clock cycle of the NOP instruction, the TX_BEGIN signal is valid, and the serial transceiver sub-module stores the contents of the n temporary registers and the first address of the current observation point in the register TX_SFR_DATA in sequence . Then, store TX_SFR_DATA, 1 start bit and 1 stop bit in sequence in the transmit shift register TX_SHIFTER_1. Starting from the fourth clock cycle of the NOP instruction, the OCT module enters the output stage of serial transmission, as shown in Figure 7. At the same time, the CPU_STOP signal is valid, and the CPU stops running.

c) TX_END: The end signal of the serial output.

In the output stage of serial transmission, the serial transceiver sub-module sends the content of TX_SHIFTER_1 serially, and when outputting, the low bit is in front, and the left end is continuously filled with 0. When the stop bit reaches the rightmost end of TX_SHIFTER_1, the all zero signal at the left end of the stop bit is detected by an "all zero detector", so the TX_END signal is immediately valid, and the OCT module stops the serial transmission process. See Figure 4.

b. If the dynamic tracking process starts, the OCT module receives the command D_DBG_PAUSE to suspend dynamic tracking during the dynamic tracking process, then in the last clock cycle of the current instruction, the CPU_STOP signal is valid, the CPU stops running, and the entire system enters dynamic tracking suspended state. At this time, the debugger can analyze the operation of the program according to the internal information of the processor at the detected observation point, so as to find program errors, reconstruct the program flow, and so on.

If the system is currently in the pause state of the dynamic trace, if the debugger issues the command D_DBG_PAUSE to pause the dynamic trace again, the system will immediately exit the pause state and re-enter the dynamic trace process. At the same time, the CPU_STOP signal is invalid immediately, and the CPU restarts from the next instruction at the previous pause.

c. If the dynamic tracking process starts and the OCT module receives the command D_DBG_STOP to stop the dynamic tracking during the dynamic tracking process, the system immediately exits the dynamic tracking process and waits for the debugger to issue a new dynamic tracking command.

Compared with the prior art, the present invention has the following prominent substantive features and remarkable advantages: through an on-chip dynamic tracking module (OCT), some key positions in the program execution process can be set as watchpoints (Watchpoints) by the debugger ), and then trigger serial transmission by detecting the observation point, output the content of the internal register at the observation point to an external debugging tool for analysis, and use a small number of registers to track and record the internal register. The invention has realized the dynamic tracking of the program running process on the 8051 series MCU, and can also be applied to other microprocessors and microprocessor fields.

Description of drawings:

Figure 1 is a workflow diagram of dynamic tracking.

Figure 2 is a diagram of the data frame format during serial reception.

Fig. 3 is a diagram of the data frame format during serial transmission.

Fig. 4 is a schematic diagram of the internal structure of the serial communication sub-module.

FIG. 5 is a schematic diagram of the internal structure of an on-chip tracking module (OCT).

Figure 6 is a diagram of the correspondence between each bit of the SFR_SEL register and 24 internal registers.

FIG. 7 is a timing chart for detecting watchpoints.

Detailed ways

A preferred embodiment of the present invention is described in detail as follows in conjunction with accompanying drawing:

The on-chip dynamic tracking method of this microprocessor, through an on-chip dynamic tracking module (OCT), adopts the following workflow (see Fig. 1) to realize the dynamic tracking to the processor running process:

1) Several observation points in the program are specified by the debugger. In this example, n=8 is set, and there are 8 watchpoint address registers WPi (0-7) in total. Therefore, the debugger can arbitrarily set 0-8 watchpoints.

2) Internal registers that need to be traced and recorded at each observation point are specified by the debugger. In this example, 24 commonly used internal registers are set for selection, and the selection of these 24 internal registers is independent of each other. The debugger can select 1 to 24 internal registers that need to be tracked and recorded according to the situation.

3) Start the process of dynamic tracking by starting the dynamic tracking command D_DBG. Then in the process of dynamic tracking, the CPU runs normally, but at the beginning of each instruction, the 8 observation point registers are compared with the current instruction first address register PCC to detect the observation point.

4) In the process of dynamic tracking, if an observation point is detected, the CPU stops running immediately, and waits for the OCT module to serially output the contents of those selected internal registers at the observation point. After the output process ends, the CPU resumes operation immediately.

5) During the dynamic tracking process, if no observation point is detected, the CPU continues to run, and the OCT module continues the dynamic tracking process until the program is executed or the debugger issues a dynamic tracking pause or stop command.

6) In the process of dynamic tracking, if the debugger issues the command D_DBG_STOP to stop dynamic tracking, the entire system immediately exits the dynamic tracking mode and waits for the debugger to issue a new debugging command.

7) In the process of dynamic tracking, if the debugger issues the command D_DBG_PAUSE to suspend dynamic tracking, the system enters the pause state. At this time, the debugger can analyze the execution of the program according to the information of the internal registers at each observation point. If the debugger issues the suspend command again, the system will immediately exit the suspend state and return to the dynamic tracking process.

In this embodiment, when receiving and sending serial data, the data frame format shown in Figure 2 and Figure 3 is adopted, and the data received and sent include 1 start bit and 1 stop bit, but the effective data bits are different That's all. At the same time, the start bit is defined as 0 level, and the stop bit is 1 level. The definitions of valid data bits when receiving and sending are respectively:

1) Since the valid data received are various dynamic tracking commands issued by the debugging tool (see Table 1 above for definitions), as well as the data and program addresses related to each command, therefore, for different commands, it is necessary to define different valid data format, but their valid data bits are 28 bits (excluding 2 flag bits). Each command and the valid data bits associated with the command are defined as follows:

WP_SET/WP_REMOVE command: command to set and clear the specified watch point, the data bits related to these two commands are invalid bits, and the 16-bit address is the watch point that needs to be set or the watch point that needs to be removed address.

·WP_CLR command: command to clear all 8 observation points, the data bits and address bits related to this command are invalid at this time;

SFR_SET command: the command to select the internal register that needs to be tracked and recorded at each observation point, and the 8-bit data and 16-bit address received together with the command are used as the selection signal of 24 internal registers;

D_DBG command: the start command of dynamic tracking, the data bits related to this command are invalid, and the 16-bit address is the starting address of the CPU to start executing the program;

· D_DBG_PAUSE/D_DBG_STOP command: Pause and stop command of dynamic tracking, the data bits and address bits related to these two commands are invalid.

2) The valid data at the time of sending is composed of the data of the selected internal register at each observation point and the address of the current observation point (see FIG. 3 ). However, in order to ensure that the number of serial output bits is consistent each time, the contents of those internal registers that are not selected are also output as all 0 data. Therefore, a total of 24 internal registers and a 16-bit address need to be output.

In order to realize the serial communication between the OCT module and the external debugging tool, the present embodiment adopts the following asynchronous serial communication structure (see Fig. 4):

NEA: the pin for serial communication between the communication sub-module and the outside of the processor;

NEAOE: During serial communication, the enable signal of the NEA pin is multiplexed during receiving and sending;

NEA_I/NEA_O: respectively the serial receiving and serial sending data terminals inside the communication sub-module;

RX_CLK/TX_CLK: the working clocks of receiving and sending processes respectively;

RX_SHIFT/TX_SHIFT: the serial shift pulses of the receiving and sending processes respectively;

RX_SHIFTER/TX_SHIFTER_1: the shift registers for receiving and sending processes respectively;

RX_START/RX_OVER: the start and end signals of the receiving process, respectively;

TX_BEGIN/TX_SEND: the start and output signals of the sending process, respectively;

·DBGCMD/RX_DATA/RX_ADDR: They are the temporary storage registers of the debug command, data and address received after the receiving process is completed.

TX_SFR_DATA: A register that stores 24 internal register data and the first address of the current observation point.

As can be seen from Figure 4, the serial communication sub-module is divided into two independent parts: the receiving part and the sending part. When in the sending state (TX_BEGIN or TX_SEND signal is valid), the NEAOE signal is valid (1 level), and the NEA pin at this time is used as an output (ie NEA_O), otherwise if the NEAOE signal is invalid, NEA is used as an input (NEA_I) .

1) The receiving process is as follows:

First, when the system is reset or after the last receiving process is over, a 30-bit all-1 signal is written into a 30-bit receiving shift register RX_SHIFTER. Then, if the receiving controller detects a negative transition from 1 to 0 at the NEA_I terminal, the RX_START signal is immediately valid, so under the control of the receiving shift pulse RX_CLK, the data appearing at the NEA_I terminal is serially shifted to the right into RX_SHIFTER, Until the start bit 0 reaches the rightmost end of RX_SHIFTER. At this time, the 0 detector detects the 0 signal at the rightmost end of RX_SHIFTER, so that the received signal RX_OVER is valid, and at the same time, the command, data and address received in RX_SHIFTER are stored in the three registers DBGCMD, RX_DATA and RX_ADDR respectively.

In addition, when sampling the signal at the NEA_I terminal, a decision method of 2 out of 3 is adopted to improve the accuracy of reception and anti-interference. That is, use the sampling clock CLK_SAMP with the same frequency as RX_CLK (the frequency is 8 times the shift pulse RX_SHIFT) to continuously sample 3 times in the middle of each received character, and then take at least 2 of the 3 same sampling results as the character. actual value.

2) The sending process is as follows:

If the observation point is detected, that is, when the WP_STOP and WP_MATCH signals are valid at the same time, the start signal TX_BEGIN of the transmission process is valid, and the data of the internal register stored in TX_SFR_DATA and the address of the current observation point are downloaded to the transmission shift register TX_SHIFTER_1 middle. At the same time, a 1 signal generated by a D flip-flop is written into the leftmost end of TX_SHIFTER_1 as a stop bit. Then, the TX_SEND signal is valid, and the data in TX_SHIFTER_1 is serially shifted right to the NEA_O signal line under the control of the sending shift pulse TX_SHIFT. In the process of data shifting to the right, the D flip-flop continuously writes 0 signals to TX_SHIFTER_1 until the stop bit reaches the rightmost end of TX_SHIFTER_1. At this time, the all 0 data at the left end of the stop bit is detected by an all 0 detector, and the TX_END signal is triggered to notify the sending controller to stop sending data.

There are 8 dynamic tracking and debugging commands received by the above-mentioned serial communication sub-module. In order to store these debug commands received, a 4-bit debug command register DBGCMD is defined to store the binary codes of these 8 debug commands (see Table 1). Among them, those binary codes that are not used in DBGCMD are temporarily reserved and can be expanded in the future.

The dynamic tracking command stored in DBGCMD can control the OCT module to complete various dynamic tracking functions for the processor (see Figure 5), including: setting of observation points, selection of internal registers, and detection of observation points during dynamic tracking, etc. .

1) Setting of observation points:

·WP0～WP7: 8 watchpoint address registers, which store the first address of the instruction set as watchpoint. When the system is reset, the contents of the 8 observation point address registers WPi (i=0～7) are all high resistance values.

The setting of the observation point is realized by a special "observation point setting network" (see Figure 5). According to different commands received, different settings of the observation point can be performed:

i) If the observation point setting command WP_SET is received, the observation point setting network will write the 16-bit address (see Fig. 2 (b)) received at this time into one of the WPi as the address of an observation point, and write The order of entry starts from WP0 and ends with WP7. The debugger can set 0 to 8 observation points according to the situation. If the debugger sets more than 8 observation points, the 9th observation point will cover the 1st one, and the 10th one will cover the 2nd one, and so on.

ii) If the watchpoint removal command WP_REMOVE is received, the watchpoint setting network will compare the 16-bit address (see Figure 2(b)) received at this time with the address that has been set as the watchpoint, and then match the That watchpoint is removed.

iii) If the watchpoint clearing command WP_CLR is received, the watchpoint setting network will clear all 8 watchpoints together.

2) Selection of internal registers:

·SFR_SEL: Register selection signal register, the size is 24 bits, which stores the selection signals of 24 internal registers. When the system is reset, the 24-bit selection signals are all 0.

After setting the watchpoints, the debugger also needs to specify the internal registers that need to be tracked and recorded at each watchpoint, which is realized through the "internal register selection network" (see Figure 5). If the OCT module receives the SFR_SET command, the internal register selection network will store the "24-bit internal register selection signal" obtained together with the command (see Figure 2(d)) in the register SFR_SEL, and then according to SFR_SEL every The state of a bit selects the corresponding internal register.

Each bit of the SFR_SEL register is an independent register selection signal, active high, and corresponds to 24 commonly used internal registers one by one (see Figure 6). Therefore, there are 24 internal registers to choose from, and the debugger can choose 0-24 of them arbitrarily. For example, if the lowest bit SFR_SEL.0 of SFR_SEL is 1, the corresponding accumulator ACC is selected, so ACC must be tracked and recorded at each observation point, but if SFR_SEL.0 is 0, ACC There is no need to be tracked and recorded. The other internal registers are selected in the same way.

3) Detect observation points during dynamic tracking:

If the debugger has set watchpoints and internal registers that need to be traced and recorded at each watchpoint, you can use the D_DBG command to start the dynamic trace process, and then the CPU will start from the "start" obtained with this command. Start address" (see Figure 2(e)) to start running. During the normal operation of the CPU, the OCT module automatically detects the observation points. The method of detecting observation points is shown in Figure 7:

PCC: The 16-bit first address register of the instruction currently being executed.

· WP_MATCH: Watchpoint match signal.

· WP_STOP: Watch point matching stop signal.

· NOP: No operation instruction.

CCLK: The clock signal for the normal operation of the CPU.

·CPU_STOP: The signal to stop the working clock of the CPU.

It can be seen from Figure 7 that the address stored in the observation point register WP0 is 75H, which is the first address of a certain instruction. If the CPU is currently executing the instruction MOV A, #data, and the first address of the instruction is 75H, then the data in the PCC is 75H. Next, the steps to detect watchpoints are:

i) In the third clock cycle C1P3 of this MOV A, #data instruction, the OCT module compares the value of WP0 with PCC, and the two match, so the WP_MATCH signal is immediately valid. Then, due to the validity of the WP_MATCH signal, after executing the MOV instruction, the CPU will execute an additional empty operation instruction NOP to ensure the integrity of the MOV A, #data instruction. Therefore, in the first clock cycle C1P1 of the NOP instruction, the value of PCC immediately becomes the first address 77H of the NOP instruction (because MOVA, the machine code of #data occupies two byte addresses, and after executing the MOV instruction, The processor's program pointer will point to the first address of the instruction temporarily replaced by this extra NOP instruction).

ii) In the third clock cycle C1P3 of the NOP instruction, WP0 and PCC have not matched at this time, so the WP_MATCH signal is immediately invalid. At the same time, since the NOP instruction is additionally executed by the CPU, the OCT module will enable the WP_STOP signal in the second clock cycle C1P2 of the NOP instruction. Then, the next clock cycle after WP_STOP becomes effective (that is, the C1P3 time of the NOP instruction), the sending start signal TX_BEGIN becomes effective. Then, the tracked data at the observation point 75H is written into the transmission shift register TX_SHIFTER_1, and at the same time, the NEA_O terminal starts to transmit the start bit (0 level) of the serial data.

iii) Then, in the fourth clock cycle C1P4 of the NOP instruction, the CPU_STOP signal is valid, and the working clock CCLK of the CPU is stopped. Then the CPU pauses, waiting for the OCT module to serially output the CPU internal information at the observation point 75H to an external debugging tool for analysis. Since CCLK has stopped, the fourth clock cycle C1P4 of the NOP instruction will be maintained until CCLK resumes.

Claims (7)

1. dynamic tracking method on the sheet of a microprocessor, it is characterized in that: by an on-chip tracer OCT, some position in the program process is set to observation point, then the information of the internal register of these given viewpoint appointments is followed the tracks of, is write down and real-time output; Its concrete steps are:

A., an asynchronous serial transmitting-receiving submodule is set, to realize communicating by letter of OCT module and processor outside;

B. set a debug command register DBGCMD, store the dynamic tracking debug command that debugging person is sent to the OCT module;

C. set n observation point address register WPi (i=0～n-1), store the first address that debugged person is set to the program of observation point;

D. set internal register and select sign register SFR SEL, be stored in the selection signal of the internal register of the tracked and record of each given viewpoint;

E. set a present instruction first address register PCC, store the first address of the current instruction of carrying out of CPU automatically;

F. start the dynamic tracking process by " starting the dynamic tracking order ", in the process of dynamic tracking, the OCT module is according to circumstances carried out the dynamic tracking operation then, and sets coherent signal.

2. dynamic tracking method on the sheet of microprocessor according to claim 1 is characterized in that the method that an asynchronous serial transmitting-receiving submodule is set among the described step a is:

This serial transmitting-receiving submodule adopts semiduplex asynchronous serial communication pattern, carries out serial communication by 1 signal wire and processor outside, and transmission and reception are two independently processes; The fundamental purpose of receiving unit is to receive the various debug commands that debugging acid sends, and data and the program address relevant with each order, and the purpose that sends then is the content strings line output with the selected internal register that goes out of each given viewpoint; Simultaneously, reception and process of transmitting have all adopted the data frame format of 1 position of rest+valid data position+1 start bit, and wherein position of rest is 1 level, and start bit is 0 level.Some signals and the register relevant with serial communication are defined as follows:

A.NEA: the external pin that asynchronous serial transmitting-receiving submodule and processor outside communicate then is divided into NEA_I in the OCT inside modules, i.e. serial data input end, and NEA_O, i.e. serial data output terminal;

B.RX_CLK/TX_CLK: the sampling clock when being asynchronous serial transmitting-receiving submodule reception and transmission serial data respectively, frequency all is 1/100 of a processor clock frequency;

C.RX_SHIFT/TX_SHIFT: the serial-shift pulse when being asynchronous serial transmitting-receiving submodule reception and transmission data respectively, frequency all is 1/8 of RX_CLK/TX_CLK, therefore, the baud rate of communication is 1/800 of a processor operating rate;

D.RX_SHIFTER: receive shift register, reception be each debug command and relevant data and address;

E.TX_SHIFTER_1: send shift register, transmission be in the data of each given viewpoint internal register and the address of this observation point.

3. dynamic tracking method on the sheet of microprocessor according to claim 1 is characterized in that the method for setting a debug command register DBGCMD among the described step b is:

Definition DBGCMD is one 4 a register, and it is used to store the binary coding of the debug command that debugging acid sends, and the debug command that receives is decoded as control signal corresponding.

DBGCMD can store 8 orders relevant with dynamic tracking, sees Table 1, and wherein, other binary codings of not using among the DBGCMD temporarily keep, and can expand afterwards.

The dynamic tracking order of table 1 DBGCMD storage Binary coding The order symbol Functional description 0000 DBG_RST Under debugging mode, whole microprocessor system is resetted 1010 WP_SET Certain bar instruction in the program is set to an observation point 1011 WP_REMOVE Remove the observation point of an appointment 1100 WP_CLR The observation point that disposable removing is all 0011 SFR_SET Be set in each given viewpoint and need internal register tracked and record 1101 D_DBG Start the dynamic tracking process 1110 D_DBG_PAUSE Suspend the dynamic tracking process 1111 D_DBG_Stop Stop the dynamic tracking process

4. dynamic tracking method on the sheet of microprocessor according to claim 1, it is characterized in that setting among the described step c n observation point address register WPi (method of i=0～n-1) is:

Definition WPi (i=0～n-1) be the register of individual 16 of n, storage be the first address that is set to the instruction of observation point; After the system reset, the value of this n observation point address register all is a high value;

The OCT module is provided with or removes observation point according to following three kinds of situations:

A) if receive WP_SET order, 16 bit address that the OCT module just will receive with this order are stored in the WPi register as the address of an observation point, and the order of storage is from WP0, arrives WPn-1 at last; If the observation point that debugging person is provided with surpasses n, then the address of n+1 observation point just overrides the 1st observation point, and n+2 observation point overrides the 2nd, and the like;

B) if receive the WP_REMOVE order, the OCT module will be compared 16 bit address that receive this moment with the address that before was set at observation point, will remove with the observation point of this matching addresses then;

C) if receive the WP_CLR order, the OCT module is just with the disposable full scale clearance of all observation point, and the data of the observation point register after being eliminated all are high value.

5. dynamic tracking method on the sheet of microprocessor according to claim 1 is characterized in that setting in the described steps d internal register and selects the method for sign register SFR_SEL to be:

Definition SFR_SEL is the register of a n position, the corresponding according to the order of sequence n of it each internal register commonly used, and it is defined as follows: Internal register n selects signal …… Internal register 2 is selected signal Internal register 1 is selected signal

When receiving selection internal register order SFR_SET, the OCT module just will order the n bit register selection signal storage that receive in SFR_SEL with SFR_SET this moment; If this moment, a certain position of SFR_SEL was 1, then this pairing internal register will be tracked, and the content of this internal register all will be output in each given viewpoint simultaneously; Otherwise if this position is 0, so Dui Ying this internal register does not just need tracked and record.

6. dynamic tracking method on the sheet of microprocessor according to claim 1 is characterized in that the method for setting a present instruction first address register PCC among the described step e is:

Definition PCC is 1 16 a address register, storage be 16 first addresss of the current instruction of carrying out; Its value is by OCT module automatic setting; After the system reset, the value of PCC is 00h;

The concrete grammar of setting the PCC register is: in the process that program is carried out, in the 1st clock period of every instruction, the value of the program pointer that points to this instruction is delivered in the PCC register; PCC can preserve this address always, the 1st clock period up to next bar instruction, just is updated to new address.

7. dynamic tracking method on the sheet of microprocessor according to claim 1 is characterized in that among the described step f that in the process of dynamic tracking, the dynamic tracking operation that the OCT module is according to circumstances carried out has following three kinds:

If after a. the dynamic tracking process started, the OCT module did not receive other control commands, then the OCT module will compare WPi (i=0～n-1) carry out the detection of observation point with the content of PCC automatically in the process that program is carried out; If detect observation point, the OCT module is just analyzed the bit string line output of the selected internal register of this given viewpoint to outside debugging acid;

The concrete steps that detect observation point and export internal register information are:

A) WP_MATCH: the observation point matched signal, high level is effective;

WP_STOP: observation point coupling stop signal;

In the process that program is carried out, in the 3rd clock period of every instruction, (content of i=0～n-1) compares with present instruction first address register PCC respectively with n observation point address register WPi; As long as have the content of an observation point address register and the content of PCC to mate fully, just explanation has detected an observation point, so the WP_MATCH signal is effective immediately; After the instruction that executes this given viewpoint, CPU also needs to carry out a non-operation instruction NOP to guarantee the integrality of execution process instruction again; Then, in the 2nd clock period of this NOP instruction, the WP_STOP signal is effective, simultaneously, the OCT module all is stored in the value of all selected internal registers that go out in the corresponding temporary register, and not having the content of the selected pairing temporary register of internal register with those then all is 0; In the next clock period after effectively of WP_STOP signal and then, the OCT module enters the preparatory stage of serial transmission;

B) TX_SFR_DATA: the register of storing n internal register data and current observation point first address;

TX_SHIFTER_1: send shift register;

TX_BEGIN: send commencing signal;

CPU_STOP: the signal that stops the CPU work clock;

In the preparatory stage that serial sends, i.e. the 3rd clock period of NOP instruction, the TX_BEGIN signal is effective, and serial transmitting-receiving submodule all leaves in the content of n temporary register and the first address of current observation point among the register TX_SFR_DATA according to the order of sequence; Then, TX_SFR_DATA and 1 start bit and 1 position of rest are left in according to the order of sequence send among the shift register TX_SHIFTER_1 again; From the 4th clock period of NOP instruction, the OCT module enters the output stage that serial sends; Simultaneously, the CPU_STOP signal is effective, and CPU is out of service;

C) TX_END: the end signal of serial output;

At the output stage that serial sends, serial transmitting-receiving submodule is sent the content serial of TX_SHIFTER_1, and low level is preceding output the time, and left end constantly mends 0; When position of rest arrived the low order end of TX_SHIFTER_1, the all-zero signal of position of rest left end was detected by one " full null detector ", so the TX_END signal is effective immediately, the OCT module just stops the serial process of transmitting;

After b. if the dynamic tracking process starts, in the process of dynamic tracking, the OCT module receives the order D_DBG_PAUSE that suspends dynamic tracking, then in last clock period of present instruction, the CPU_STOP signal is effective, and CPU is out of service, and total system enters the halted state of dynamic tracking; At this moment, debugging person can come the ruuning situation of routine analyzer according to the processor internal information of the given viewpoint that is detected, thus search program mistake, reconfiguration program flow process etc.; If the current halted state that is in dynamic tracking of system, if debugging person sends the order D_DBG_PAUSE that suspends dynamic tracking once more, then system withdraws from halted state immediately, and reenters the dynamic tracking process; The CPU_STOP signal is invalid immediately simultaneously, and CPU begins to rerun from next bar instruction of previous time-out;

If after c. the dynamic tracking process started, in the process of dynamic tracking, the OCT module received the order D_DBG_STOP that stops dynamic tracking, then system withdraws from the dynamic tracking process immediately, and waits for that debugging person sends new dynamic tracking order.

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