CN101178685A - An Enhanced Microprocessor On-Chip Dynamic Tracing Method with Special Function Register Breakpoints - Google Patents

Abstract

The invention relates to an enhanced on-chip dynamic tracing method with special function register breakpoints. This method can set some positions or special function registers in the program execution process as breakpoints through an independent enhanced on-chip debugging module with SFR breakpoint function integrated in the microprocessor, and then set these breakpoints The information of the internal registers at the location is tracked, recorded and output in real time. And by adding a debug enable signal to realize the switching between the debug mode and the normal operation mode. The method of the invention can be applied to the field of 8051 series microprocessors, and can also be applied to the fields of other microprocessors.

Description

An Enhanced Microprocessor On-Chip Dynamic Tracing Method with Special Function Register Breakpoints

technical field

The invention relates to an enhanced on-chip dynamic tracking method of a microprocessor with special function register breakpoints, which supports online debugging functions, including single-step debugging, setting and detection of address breakpoints and SFR special function register breakpoints, and microprocessing View and modify the internal registers of the device, etc. It can be applied to single-chip microprocessors of 8051 series, and can also be applied to other microprocessors and microprocessor fields.

Background technique

Dynamic Trace (Dynamic Trace) refers to the process of recording the trajectory information of program operation in real time, and transmitting this information to an external debugging tool for analysis and debugging by some means. In most devices such as logic analyzers and in-circuit emulators, there are tracking components used to dynamically track the running track of the processor, which are used to monitor various internal information of the processor, so that the debugger can easily detect the program execution flow , find program errors, reconstruct the program running track, etc.

Motorola was the first to recognize the development trend of OCD technology, and took the lead in creating the BDM debugging interface on the 683xx and 68HC16 processors. And MIPS, Intel, IBM and ARM have realized the serial debugging interface based on JTAG standard. Although the BDM and JTAG debug interfaces are far apart in implementation details, they provide similar debug functionality from the user's point of view. Since JTAG is an IEEE international standard, most CPU manufacturers currently use it to implement the on-chip debugging logic of the processor. The existing on-chip debugging technology relies on the realization of a specific structure, which requires a lot of changes to the processor core and requires more resources, which is not convenient to implement; at the same time, the existing on-chip debugging technology can only achieve program address breakpoints and single-step Execution and other debugging functions, and the special function register (SFR-special function register) is an important part of the microprocessor and plays an important role in the microprocessor. It is very important for the user to know the running status of the special function register in real time. Therefore, it is necessary to realize the SFR breakpoint.

Contents of the invention

The object of the present invention is to provide an on-chip dynamic tracking method of an enhanced microprocessor with SFR breakpoint function. Through an independent enhanced on-chip debug module with SFR breakpoint function (Enhanced OCD module with SFR Breakpoint Function: E-OCD-SFR-B) integrated in the microprocessor, the debugger's concern during program execution can be Some locations or SFRs are set as breakpoints, and the information of these locations is tracked, recorded and output in real time to achieve the purpose of dynamic tracking. Moreover, the whole process does not need a special tracking buffer unit, and only a small number of registers can meet the temporary storage requirements of data. And by adding an external debugging enable signal to realize switching between debugging and normal operation.

For achieving the above object, design of the present invention is as follows:

Build an enhanced on-chip debug module with SFR breakpoint function (EnhancedOCD module with SFR Breakpoint Function: E-OCD-SFR-B) integrated in the processor, through which certain positions or SFRs are marked as observation points. E-OCD-SFR-B can freely switch between the debugging mode and the normal working mode through the setting of the external debugging enable signal (DBG_enable). The debug enable signal (DBG_enable) keeps low level, and in normal working mode, E-OCD-SFR-B does not interfere with the work of the processor; the debug enable signal (DBG_enable) becomes high level, allowing debugging, debugging The mode can be divided into address comparison mode and SFR breakpoint mode. 1) Address comparison mode: In the process of program execution, the address of each instruction is compared with the value of the breakpoint register (breakpoint register) to detect the observation point. If an observation point is detected, the signal will be output to the clock module, the system clock (clk) will be suspended, so as to achieve the purpose of suspending the operation of the microprocessor, and the debug clock (DBG_clk) will start running. At this time, the selected The information of the internal register is output to the specified output register (desired_SFR). If the data output is completed, the external debugging enable signal is set to be low level, and the execution of the program is resumed. 2) SFR breakpoint mode: select a specific SFR, and compare the value in this SFR with the breakpoint register value during program running. If an observation point is detected, the signal will be output to the clock module, the system clock (clk) will be suspended, so as to achieve the purpose of suspending the operation of the microprocessor, and the debug clock (DBG_clk) will start running. At this time, the selected The information of the internal register is output to the specified output register (desired_SFR). If the data output is completed, the external debugging enable signal is set to be low level, and the execution of the program is resumed.

According to above-mentioned design, the present invention adopts following technical scheme:

The enhanced on-chip debugging method is characterized in that it realizes the single-step execution and address breakpoint debugging functions on the general chip, and at the same time adds the SFR breakpoint function to realize the complete controllability and observability of SFR, so the debugging mode is divided into address There are two kinds of comparison mode and SFR breakpoint mode, and the specific steps are:

a. Set a debug command register module DBG_command, which is used to generate the commands required for debugging, and control the start and mode of debugging.

In the debug command register DBG_command of the debug module, select the breakpoint mode as address comparison mode or SFR breakpoint mode, and select the special function register to be output. If you choose the address comparison mode, you can set the breakpoint to the current address or the address specified by the breakpoint register; if you choose the SFR breakpoint mode, you also need to set which SFR to choose as the breakpoint;

b. Write a value in the breakpoint register breakpoint register.

c. If the address comparison mode is selected, compare the program counter pointer PC with the preset breakpoint register value, and if they are equal, stop the operation of the microprocessor, and output the value of the preset special function register to the output SFR register desired_SFR;

d. If the SFR breakpoint mode is selected, compare the selected SFR value with the preset breakpoint register value, if they are the same, stop the operation of the microprocessor, and output the preset special function register value to the output SFR register desired_SFR;

e. Start the dynamic tracking process by setting the external debugging enable DBG_en signal to a high level, meet the setting conditions, and enter the debugging state. At this time, you only need to set the debugging enable DBG_en signal to a low level to restore to the original normal operating state.

The above method of setting a debug command register DBG_command is:

Define DBG_command as an 8-bit register, which is used to store the binary code of the debugging command, and decode the received debugging command into the corresponding control signal.

The format of DBG_command is shown in Figure 1 attached to the manual. Among them, other binary codes not used in DBG_command are temporarily reserved and can be expanded in the future.

SFR_output_select——select the special function registers that need to be output after entering the debug mode.

Three bits are set here, so you can choose among 8 SFRs; the selection format is shown in Table 2 of the attached manual.

SFR_select——In SFR breakpoint mode, which SFR is selected as a breakpoint comparison.

Two bits are defined here, so you can choose from 4 SFRs, and the selection format is shown in Table 3 of the attached manual.

PC_break——Multiplexed with the upper two bits of SFR_output_select. In the address comparison mode, select the address of the breakpoint. The selection format is shown in Table 4 of the attached manual.

single_step——Single-step operation flag.

mode - breakpoint mode selection flag. 0 is address comparison mode; 1 is SFR breakpoint mode

In the SFR breakpoint mode, it is necessary to set the mode selection bit, the SFR used as the breakpoint comparison, and the SFR to be output.

start——debugging start flag. Setting this bit to 1 indicates that debugging has started.

The method for setting the value of the breakpoint register (breakpoint_register) above is: pre-define an undefined special function register, define it as a breakpoint register, and write the set breakpoint value into the breakpoint register. .

There are two types of dynamic tracking operations according to the situation in the process of on-chip debugging:

a) The first is the address breakpoint mode, which is to compare the program pointer PC with the preset breakpoint register value. If they are equal, the breakpoint condition is triggered, and the signal is output to the clock generation module to stop the clock operation of the microprocessor core. , and the debug clock starts to work at the same time, output the value of the special function register to be observed to the output register, and wait for the next step of processing.

b) The second is the SFR breakpoint mode, which compares the selected SFR value with the preset breakpoint register value. If they are equal, the breakpoint condition is triggered, and the output meets the signal to the clock generation module to stop the microprocessor core. The clock is running, and the debugging clock starts to work at the same time, output the value of the special function register to be observed to the output register, and wait for the next step of processing.

The operation method for freely switching between the debugging mode and the normal operation mode according to the situation during the on-chip debugging process is as follows:

In order to realize the free switching between the two working modes, a debug enable (DBG_enable) signal is added.

a) Enter debug mode from normal operation mode: the DBG_enable signal must be set to high level, otherwise the debug command register (DBG_command) will not work;

b) Restore from debug mode to normal operation mode: Just set the DBG_enable signal to be low level, and the normal operation of the microprocessor can be resumed conveniently.

Compared with the prior art, the present invention has the following obvious outstanding substantive features and significant advantages: the present invention uses an independent enhanced on-chip debugging module with SFR breakpoint function integrated in the microprocessor to control the program execution process Some positions and special function registers are set as breakpoints, and then the information of the internal registers at these breakpoints is tracked, recorded and output in real time to achieve the purpose of dynamic tracking. And by adding a debugging enable signal to realize switching between the debugging mode and the normal working mode. The whole process of the invention does not need a special tracking buffer unit, and only a small amount of registers can meet the temporary storage requirements of data. The invention is suitable for 8051 series microprocessors and other microprocessor fields.

Description of drawings:

Figure 1 is a flowchart of the enhanced on-chip debugging with SFR breakpoint function.

Fig. 2 is a schematic diagram of the internal structure of the breakpoint module.

Figure 3 is the clock generation module.

Detailed ways

A preferred embodiment of the present invention is described in detail as follows in conjunction with accompanying drawing:

The on-chip dynamic tracking method of this microprocessor adopts the following workflow (see Figure 1) to realize the dynamic tracking of the processor running process:

a) If the debug enable signal (DBG_enable) is kept at a low level, the debug command register (DBG_command) does not work at this time, and the microprocessor operates normally. If you want to debug, set the debug enable signal (DBG_enable) to a high level.

b) Write the initial value to the debug command register (DBG_command), and the format description of the debug command register is shown in Table 1 of the accompanying drawing. In this design, the start flag bit start is defined first, if the flag position is 1, it indicates the start of debugging. The reason for setting the start flag is: if there is no debug start flag, because the default value of the debug register (breakpoint_register) is all 0, once the debug enable signal becomes high, if the PC or the selected SFR A value of 0 triggers a breakpoint condition, which brings unexpected breakpoints and reduces the correctness of the on-chip debug unit. In this design, two bits are defined for the SFR breakpoint selection (SFR_select), that is, four special function registers can be selected. Here, the commonly used accumulator (ACC-Accumulator), stack (SP-Stack Point), Status (PSW-ProgramStatusWord), P0 (port 0). For the selection of the output SFR, three bits are defined, that is, the output can be selected from 8 SFRs. Here, it is set to the commonly used stack (SP-Stack Point), accumulator (Acc-Accumulator), status register (PSW-ProgramStatusWord), B register, P0 (port0), P1 (port 1), P2 (port 2), P3 (port 3). The mode selection bit (mode) selects the breakpoint mode. When it is set to 0, the address breakpoint mode is selected, and when it is set to 1, the SFR breakpoint mode is selected. In this design, the high two bits of the debug command register (DBG_command) are multiplexed for the address selection bit (PC_break) as a breakpoint in the address comparison mode. PC_break is equal to 01, and the current PC is selected as a breakpoint. The advantage of this mode is that you can freely choose any interesting position in the program to set a breakpoint, which is more suitable for users who do not know much about the operation of the program; PC_break is equal to 10, Select the specified PC as a breakpoint. When the program runs to this specific address, the breakpoint condition will be triggered and enter the debugging stage.

c) Write the predetermined value into the breakpoint register (breakpoint_register), as shown in Figure 2, wait for comparison; the breakpoint register is different because of the different selections of the breakpoint mode, if the selection is the current address comparison mode of the address comparison mode, then In principle, at this time, the current address is compared with the breakpoint register. In fact, the two are the same, so it is enough to directly trigger the match signal; if the specified address comparison mode of the address comparison mode is selected, the program counter (PC) is selected. Compared with the breakpoint register value, the breakpoint register is 16bit at this time; if it is the SFR breakpoint mode, select SFR and the breakpoint register value for comparison, and the breakpoint register is 8bit at this time.

d) The setting of the debugging enable signal can realize free switching between the debugging mode and the normal working mode. If the debug enable signal is held low, the microprocessor is operating normally. Set the external debug enable signal DBG_enable to high level to allow breakpoint comparison.

e) The comparator (compare) in Figure 2 compares the value of the breakpoint register with the address or the selected SFR value. The structure of the comparator is a set of XOR gate circuits. If the two sets of signals are the same, the breakpoint condition is satisfied, and the match signal (match) becomes high level, and this signal is output to the clock generation module; in the address comparison In the current address mode, the match signal is directly output without a comparator;

f) The clock signal is the basis of the operation of the microprocessor, so the most important thing for on-chip debugging is to realize the controllability of the clock signal. It can be seen from the clock generation module in Figure 3 that if the match signal is at low level, it indicates that the breakpoint condition is not met at this time, and the system clock (clk) still works normally after being ORed with the match signal; if the match signal is at high level Ping, it indicates that the breakpoint condition has been triggered at this time, enters the debugging mode, needs to suspend the operation of the microprocessor, after the match signal and the system clock signal are ORed, the output clock becomes always high, and the operation of the microprocessor stops .

g) After the breakpoint condition is triggered, the signal to be observed can be output to the output register (desired_SFR), because the system clock has stopped running at this time, so it is necessary to add a debug clock (DBG_clk) to the clock generation module. Next, output the signal value to be observed. In this way, the internal SFR is completely visible, and the original intention of on-chip debugging is realized. The advantage is that the controllability and visibility of the operation of the microprocessor and the special function registers can be realized without adding additional external dedicated circuits.

h) When it is necessary to restore from the debug mode to the normal operating state, it is only necessary to set the debug enable signal (DBG_enable) to low level, and if DBG_enable is low level, the value of the debug command register (DBG_command) is all 0, and the The command register is invalidated at this time and program execution resumes.

The above-mentioned debugging command register DBG_command format is shown in Table 1, the SFR output selection format is shown in Table 2, the SFR breakpoint selection format is shown in Table 3, and the address breakpoint format is shown in Table 4.

Table 1

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR_output_select.2 or PC_break.1 SFR_output_select.1 or PC_break.0 SFR_output_select.0 SFR_select.1 SFR_select.0 Single_step mode start R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0

Table 2

SFR_output_select code illustrate 000 desired_SFR<=SP; select stack as output 001 desired_SFR<=acc; Select accumulator output 010 desired_SFR<=PSW; Select Status Register Output 011 desired_SFR<=B; Select B register output 100 desired_SFR<=p0; Select p0 port output 101 desired_SFR<=p1; Select p1 port output 110 desired_SFR<=p2; Select p2 port output 111 desired_SFR<=p2; Select p3 port output

table 3

SFR_select the code illustrate 00 DBG_data_in <= acc select accumulator value breakpoint 01 DBG_data_in <= SP; Select the stack value as a breakpoint 10 DBG_data_in <= PSW; Select the status register value as a breakpoint 11 DBG_data_in <= p0; Select the port value of p0 as a breakpoint

Table 4

PC_break illustrate 01 Select the current program address as a breakpoint 10 Select the value in the breakpoint register as the breakpoint

Claims (6)

1. a dynamic tracking method on an enhanced microprocessor chip with SFR breakpoint, it is characterized in that: by an integrated internal independent enhanced debug module with SFR breakpoint function in microprocessor, program execution process Some location program addresses or some SFRs in the program are set as observation points, and then the information specified at these observation points is tracked, recorded and output in real time; the specific steps are: a. Set a debug command register module DBG_command, which is used to generate the commands required for debugging, and control the start and mode of debugging; In the debug command register DBG_command of the debug module, select the breakpoint mode as address comparison mode or SFR breakpoint mode, and select the special function register to be output. If you choose the address comparison mode, you can set the breakpoint to the current address or the address specified by the breakpoint register; if you choose the SFR breakpoint mode, you also need to set which SFR to choose as the breakpoint; b. Write a value in the breakpoint register breakpoint register; c. If the address comparison mode is selected, compare the program counter pointer PC with the preset breakpoint register value, and if they are equal, stop the operation of the microprocessor, and output the value of the preset special function register to the output SFR register desired_SFR; d. If the SFR breakpoint mode is selected, compare the selected SFR value with the preset breakpoint register value, if they are the same, stop the operation of the microprocessor, and output the preset special function register value to the output SFR register desired_SFR; e. Start the dynamic tracking process by setting the external debugging enable DBG_en signal to a high level, meet the setting conditions, and enter the debugging state. At this time, you only need to set the debugging enable DBG_en signal to a low level to restore to the original normal operating state. 2. the dynamic tracing method on the enhanced microprocessor chip of band SFR breakpoint according to claim 1, it is characterized in that the method for the debugging command register DBG_command of debugging module is set in the described step a is: Define DBG_command as an 8-bit register, which is used to store the binary code of the debugging command issued by the debugging tool, and decode the received debugging command into the corresponding control signal. Set DBG_command according to different working methods: If working in the address comparison mode, the mode selection bit mode is set to 0; when the address selection bit PC_break is equal to 01, the current address is selected, and when it is equal to 10, the specified address is selected; when the debugging start flag bit start is set to 1, the debugging starts, and when it is set to zero, the debugging ends. If working in SFR breakpoint mode, the mode selection bit mode is set to 1; the output SFR selection bit SFR_output_select defines 3 bits, which can be selected from 8 different SFRs; the SFR breakpoint selection bit SFR_select defines two bits, which can be selected in 4 Which one of the different SFRs is selected as a breakpoint; when the single-step operation flag single_step is set to 1, single-step operation. 3. the dynamic tracing method on the enhanced microprocessor chip of band SFR breakpoint according to claim 1, it is characterized in that the setting method of the breakpoint register in the described step b is: If the working mode is selected as the address comparison mode, the breakpoint register at this time is 16bit, and if the working mode is selected as the SFR breakpoint mode, the breakpoint register is 8bit. 4. the on-chip dynamic tracking method of the enhanced microprocessor with SFR breakpoint according to claim 1, is characterized in that the method for the address comparison mode work in the described step c is: The microprocessor runs according to the program address pointer PC, so the address comparison mode is to compare the value of the PC with the value of the breakpoint register. When the PC runs to a specific address, that is, the same as the value of the breakpoint register, the symbol signal is output to The clock module suspends the operation of the microprocessor, and the debugging clock starts to work at the same time. Under the debug clock, output the value of the special function register to be checked to the output register desired_SFR; 5. the on-chip dynamic tracking method of the enhanced microprocessor with SFR breakpoint according to claim 1, is characterized in that the method of the SFR breakpoint pattern work in the described step d is: First, set the SFR that needs to be set as a breakpoint in the DBG_command register; because two bits are defined in the DBG_command register for the selection of the breakpoint SFR, so a total of 4 commonly used SFRs can be selected; select the breakpoint SFR Finally, if the value in the selected SFR is compared with the breakpoint register, if they are equal, the breakpoint condition is triggered, the symbol signal is output to the clock module, the microprocessor suspends operation, and enters the debug mode; at the same time, the debug clock starts to work; Under the debug clock, output the value of the special function register to be checked to the output register desired_SFR; 6. the on-chip dynamic tracking method of the enhanced microprocessor with SFR breakpoint according to claim 1, is characterized in that the debug mode in the described step e and the method for normal operation mode switching are: In normal mode, the microprocessor runs normally. If the following tasks are completed, it will enter the debugging mode. First, set the debug enable signal. If the signal value is set to "1" at this time, enter the debug mode, and then input a specific value to the debug command register. At this time, the debug start flag in the debug command register is 1. When the debugging starts, when the microprocessor runs to a specific trigger condition, the corresponding debugging process is carried out; from the debugging state to the normal operation state, it is only necessary to set the debugging enable signal to a low level.