CN110597555A - Non-volatile in-memory computing chip and operation control method thereof - Google Patents

Abstract

The present invention provides a non-volatile in-memory computing chip and an operation control method thereof. The non-volatile in-memory computing chip includes: a cache module for caching data; a non-volatile in-memory computing module connected to the cache The module is used to perform operations on the data sent by the cache module; the post-processing module is connected to the non-volatile in-memory computing module, and is used to post-process the calculation results of the non-volatile in-memory computing module; wherein, The non-volatile in-memory computing module includes: a non-volatile memory cell array, a row-column decoder connected to the non-volatile memory cell array, and a read-write circuit connected to the non-volatile memory cell array. Among them, through the above-mentioned non-volatile in-memory computing chip combined with the operation control method, the multiplication and accumulation operation and the binary neural network operation are realized based on the integrated storage and calculation technology, without the need to transmit data between the memory and the processor, reducing power consumption and time. delay.

Description

Non-volatile in-memory computing chip and operation control method thereof

technical field

The invention relates to the technical field of application of semiconductor integrated circuits, in particular to a non-volatile in-memory computing chip and an operation control method thereof.

Background technique

With the introduction of deep learning theory and the improvement of numerical computing equipment, deep learning neural network technology has developed rapidly and has been widely used in computer vision, natural language processing and other fields. Now the neural network generally adopts floating-point calculation, which requires a large storage space and a long operation time.

A binary neural network (Binary Neural Network, BNN) refers to a neural network obtained by simultaneously binarizing the weight values in its weight matrix and each activation function value (eigenvalue) on the basis of a floating-point neural network, namely : Binarize the weight value and activation function value to 1 or -1. Through the binarization operation, the parameters of the model take up less storage space (memory consumption is theoretically reduced to 1/32 of the original, from floating point 32 bits to 1 bit), and bit operations are used to replace multiplication in the network The addition operation greatly reduces the operation time and power consumption. Therefore, the binary neural network can solve the problems that the current floating-point neural network model is applied to embedded or mobile scenarios (such as mobile phones, wearable devices, self-driving cars, etc.) It reduces storage space occupation, reduces computing time, and has become a popular research direction of deep learning in recent years due to its potential advantages of high model compression rate and fast computing speed.

However, although the phase transition between the binary neural network and the floating-point neural network can reduce the storage space occupied and reduce the operation time, however, because the binary neural network still needs to transmit data between the memory and the processor, frequent data movement is still It will bring higher power consumption and delay.

Contents of the invention

Aiming at the problems in the prior art, the present invention provides a non-volatile in-memory computing chip and an operation control method thereof, which can at least partly solve the problems in the prior art.

In order to achieve the above object, the present invention adopts the following technical solutions:

In the first aspect, a non-volatile in-memory computing chip is provided, including:

A cache module for caching data;

A non-volatile in-memory computing module, connected to the cache module, for performing operations on data sent by the cache module;

A post-processing module, connected to the non-volatile in-memory computing module, for post-processing the calculation results of the non-volatile in-memory computing module;

Wherein, the non-volatile in-memory computing module includes: a non-volatile memory cell array, a row-column decoder connected to the non-volatile memory cell array, and a read-write circuit connected to the non-volatile memory cell array.

Further, the cache module includes: a first cache unit and a second cache unit,

The first cache unit is connected to the front end of the non-volatile in-memory computing module, and is used to receive and cache input data and feature map data;

The second cache unit is connected to the non-volatile in-memory computing module for caching weight data.

Further, the row and column decoder includes: a row decoder and a column decoder, and the nonvolatile memory cell array includes: a plurality of nonvolatile memory cells arranged in an array;

Each column of non-volatile memory cells is connected to the column decoder through a bit line, and each row of non-volatile memory cells is connected to the row decoder through a word line. The bit line of each row of non-volatile memory cells Both the source line and the source line are connected to the read-write circuit.

Further, the non-volatile memory unit includes: a non-volatile memory device and a three-terminal switch element connected in series;

One end of the non-volatile memory device is connected to the bit line, the other end is connected to the first end of the three-terminal switching element, the second end of the three-terminal switching element is connected to the word line, and the third end of the three-terminal switching element is connected to the source line.

Further, the row and column decoder includes: a row decoder and a column decoder, and the nonvolatile memory cell array includes: a plurality of nonvolatile memory cells arranged in an array;

Each column of non-volatile memory cells is connected to the column decoder through a bit line, and each row of non-volatile memory cells is connected to the row decoder through a source line. The bit line of each row of non-volatile memory cells Both the source line and the source line are connected to the read-write circuit.

Further, the non-volatile storage unit includes: a non-volatile storage device connected in series and a two-terminal switch element;

One end of the series branch formed by the nonvolatile memory device and the two-terminal switching element is connected to the bit line, and the other end is connected to the source line.

Further, it also includes: an amplifier, which is connected to each bit line, and is used to compare the total analog current/voltage on each bit line with reference information, and output the calculation result of the non-volatile memory calculation module.

Further, it also includes: a counter, the counter is connected to the read-write circuit, and the output of the counter is used as the calculation result of the non-volatile in-memory calculation module.

Further, the nonvolatile memory unit is a resistive change memory unit, a phase change memory unit, a ferroelectric memory unit, or a spin memory unit.

In the second aspect, a control method for implementing multiplication and accumulation operations based on non-volatile in-memory calculations is provided, including:

storing the first binary operation signal into a row of non-volatile storage units, and storing one bit of the first binary operation signal in each non-volatile storage unit;

The second binary operation signal is loaded to the row of non-volatile storage units, and the corresponding bits of the first binary operation signal and the second binary operation signal are applied to the same non-volatile storage when the multiplication and accumulation operation is performed. unit;

Loading an NOR operation instruction into the row of non-volatile storage units, so that the row of non-volatile storage units executes the first binary operation signal and the second binary operation in response to the NOR operation instruction The exclusive OR operation of the corresponding bit of the signal, and store the operation result in the corresponding non-volatile storage unit;

The data in each non-volatile storage unit in the row of non-volatile storage units is read and accumulated to obtain the multiplication-accumulation operation result of each bit of the first binary operation signal and the second binary operation signal.

In the third aspect, a control method for implementing binary neural network operations based on non-volatile in-memory calculations is provided, including:

storing at least one binary weight signal in at least one row of non-volatile storage units, and storing one bit of the binary weight signal in each non-volatile storage unit;

Loading the feature signal to the row of non-volatile storage units, and applying the corresponding bit when the binary weight signal and the feature signal perform a multiplication-accumulation operation to the same non-volatile storage unit;

Loading the NOR operation instruction into the non-volatile storage unit of the row, so that the non-volatile storage unit of the row responds to the NOR operation instruction to perform the NOR operation of the binary weight signal and the corresponding bit of the feature signal, And store the operation result in the corresponding non-volatile storage unit;

The data in each non-volatile storage unit in the row of non-volatile storage units is read and accumulated to obtain a multiplication-accumulation operation result of the binary weight signal and each bit of the characteristic signal.

Further, it also includes:

The result of the multiply-accumulate operation is cached as the feature signal of the next layer.

Further, it also includes:

The result of the multiply-accumulate operation is post-processed to obtain the result of the binary neural network operation.

The embodiment of the present invention provides a non-volatile in-memory computing chip and its operation control method. The non-volatile in-memory computing chip includes: a cache module for caching data; a non-volatile in-memory computing module connected to the The cache module is used to perform calculations on the data sent by the cache module; the post-processing module is connected to the non-volatile in-memory computing module, and is used to post-process the calculation results of the non-volatile in-memory computing module; The non-volatile in-memory computing module includes: a non-volatile memory cell array, a row-column decoder connected to the non-volatile memory cell array, and a read-write circuit connected to the non-volatile memory cell array. Among them, through the above-mentioned non-volatile in-memory computing chip combined with the operation control method, the multiplication and accumulation operation and the binary neural network operation are realized based on the integrated storage and calculation technology, without the need to transmit data between the memory and the processor, reducing power consumption and time. delay.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present application, those of ordinary skill in the art can also obtain other drawings based on these drawings without creative effort. In the attached picture:

Fig. 1 is a structural block diagram 1 of a non-volatile in-memory computing chip in an embodiment of the present invention;

Fig. 2 shows the structure of the computing module 20 in the non-volatile memory in Fig. 1;

Fig. 3 is a structural block diagram 2 of a non-volatile in-memory computing chip in an embodiment of the present invention;

Fig. 4 shows a kind of structure of the non-volatile storage unit in Fig. 2;

Figure 5 shows a structure based on the nonvolatile memory cell array shown in Figure 4;

Figure 6a shows another structure of the nonvolatile memory cell in Figure 2;

Figure 6b shows a third structure of the nonvolatile memory cell in Figure 2;

Fig. 7 shows another structure based on the nonvolatile memory cell array shown in Fig. 6b;

8a to 8c show the operation logic of three kinds of non-volatile storage units provided by the embodiment of the present invention;

Fig. 9 shows a truth table for implementing the same-or operation or the exclusive-or operation using the logic shown in Fig. 8a to Fig. 8c;

FIG. 10a shows a circuit structure for implementing an exclusive-or logical operation or an exclusive-or logical operation by using the nonvolatile memory cell array shown in FIG. 5;

FIG. 10b shows another circuit structure for realizing the exclusive OR logic operation or the exclusive OR logic operation by using the nonvolatile memory cell array shown in FIG. 5;

FIG. 11a shows a circuit structure for realizing the same-OR logic operation or the exclusive-or logic operation by using the nonvolatile memory cell array shown in FIG. 7;

FIG. 11b shows another circuit structure for realizing the exclusive OR logic operation or the exclusive OR logic operation by using the nonvolatile memory cell array shown in FIG. 7;

Fig. 12 shows the specific structure of post-processing module 30 in Fig. 1;

FIG. 13 shows a flowchart 1 of a control method for implementing multiply-accumulate operations based on non-volatile in-memory calculations in an embodiment of the present invention;

FIG. 14 shows the second flow chart of the control method for implementing multiply-accumulate operations based on non-volatile in-memory calculations in an embodiment of the present invention;

FIG. 15 shows a flow chart of a control method for implementing binary neural network operations based on non-volatile in-memory calculations in an embodiment of the present invention.

Fig. 16 shows a neural network computing architecture.

Detailed ways

In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the application. Obviously, the described embodiment is only It is an embodiment of a part of the application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

The detailed features and advantages of the present invention are described in detail below in the embodiments, the content of which is sufficient to enable any person skilled in the art to understand the technical content of the present invention and implement it accordingly, and according to the content disclosed in this specification, claims and drawings , any person skilled in the art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the concept of the present invention in detail, but do not limit the scope of the present invention in any way.

It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

At present, although the phase transition between the binary neural network and the floating-point neural network can reduce the storage space occupation and reduce the operation time, however, because the binary neural network still needs to transmit data between the memory and the processor, frequent data movement is still It will bring higher power consumption and delay.

In order to at least partially solve the above-mentioned technical problems existing in the prior art, an embodiment of the present invention provides a non-volatile in-memory computing chip, which can integrate storage and computing into the same chip, and realize multiplication and accumulation operations based on integrated storage and computing technology And binary neural network operations, so as to directly use the memory for calculation, reduce data transmission between the memory and the processor, and reduce power consumption and delay.

FIG. 1 is a structural block diagram 1 of a non-volatile in-memory computing chip in an embodiment of the present invention. As shown in FIG. 1 , the non-volatile in-memory computing chip includes: a cache module 10 , a non-volatile in-memory computing module 20 and a post-processing module 30 .

Wherein, the cache module 10 is used to receive input data and cache data, and may also be used to output data, wherein, the cached data may be input data, or may be an intermediate operation result or post-processing of the non-volatile in-memory computing module 20 The calculation results output by the module, etc., such as: input data, weight data, feature map data, etc.

Specifically, the cache module 10 can be implemented by using SRAM or MRAM.

The non-volatile in-memory computing module 20 is connected to the cache module, and is used to perform operations on the data sent by the cache module.

Wherein, the non-volatile in-memory computing module 20 can store data, and can also implement AND logic operations, OR logic operations, exclusive-OR logic operations, exclusive-OR logic operations, and multiply-add-accumulate (MAC) operations based on non-volatile characteristics. )Wait.

A post-processing module (Post-processing Engine) 30 is connected to the non-volatile in-memory computing module for post-processing the calculation results of the non-volatile in-memory computing module.

Specifically, the post-processing may include operations such as pooling, batch normalization, shifting, offset, averaging, maximum and minimum values, and activation functions.

Wherein, the calculation module 20 in the non-volatile memory includes: a non-volatile memory cell array 21, a row-column decoder 23 connected to the non-volatile memory cell array, a reader connected to the non-volatile memory cell array The write circuit 22 may also include a MAC peripheral circuit 24 (such as a counter, an amplifier, etc.) connected to the non-volatile memory cell array 21, see FIG. 2 .

Specifically, the non-volatile memory cell array 21 can be RRAM, PCRAM, MRAM and so on.

It is worth noting that the non-volatile in-memory computing chip provided by the embodiment of the present invention receives or caches data by using a cache module, and controls the non-volatile in-memory computing module 20, so that the non-volatile in-memory computing The module 20 performs logical operations on the data to be operated, and the post-processing module 30 processes the operation results, then sends them to the cache module for output or continues to participate in the next round of operations, and then realizes multiplication-accumulation operations or binary neural networks based on the integration of storage and calculation technology In computing and other computing processes, there is no need to transfer data between the memory and the processor, reducing power consumption and delay.

In an optional embodiment, referring to FIG. 3 , the cache module 10 may include: a first cache unit 11 and a second cache unit 12 .

The first cache unit 11 is connected to the front end of the non-volatile in-memory computing module 20 for receiving and buffering input data and feature map data; the second cache unit 12 is connected to the non-volatile in-memory computing module for Cache weight data.

Wherein, by setting two cache units to respectively cache different data, the data cache reading speed can be improved, and the flexibility of the non-volatile in-memory computing chip can be improved.

In an optional embodiment, the cache module 20 can also be connected with a nonvolatile off-chip memory (can be traditional Flash, hard disk, or new nonvolatile memory RRAM, MRAM, PCRAM), thereby improving The capacity and access speed of the off-chip storage prevent the serious overflow of cache data and affect the operation during large-scale operations.

In an optional embodiment, the row and column decoder includes: a row decoder and a column decoder, and the nonvolatile memory cell array includes: a plurality of nonvolatile memory cells arranged in an array; Each row of nonvolatile memory cells is connected to the column decoder through a bit line BL, and each row of nonvolatile memory cells is connected to the row decoder through a word line WL. Each row of nonvolatile memory cells Both the bit line BL and the source line SL are connected to the read/write circuit.

In a further embodiment, the nonvolatile memory unit includes: a nonvolatile memory device R connected in series and a three-terminal switch element T1 (1T1R structure for short), see FIG. 4 ;

One end of the non-volatile memory device R is connected to the bit line BL, and the other end is connected to the first end of the three-terminal switching element T1, and the second end of the three-terminal switching element T1 is connected to the word line WL. The third end of the three-terminal switching element T1 is connected to the source line SL. The structure of the non-volatile memory cell array formed by the arrangement of the non-volatile memory cell array is shown in FIG. 5 .

Wherein, the switch element can be realized by PMOS transistor or NMOS transistor, the first terminal can be the drain of the MOS transistor, the second terminal can be the gate of the MOS transistor, and the third terminal can be the source of the MOS transistor.

Of course, the first terminal of the transistor provided in the embodiment of the present invention may be the source, and the third terminal may be the drain, which is not limited in the present invention, and can be reasonably selected according to the type of the transistor.

In another optional embodiment, the row and column decoder includes: a row decoder and a column decoder, and the nonvolatile memory cell array includes: a plurality of nonvolatile memory cells arranged in an array;

Each row of nonvolatile memory cells is connected to the column decoder through a bit line, and each row of nonvolatile memory cells is connected to the row decoder through a source line. The bit of each row of nonvolatile memory cells Both the source line and the source line are connected to the read-write circuit.

In a further embodiment, the non-volatile memory unit includes: a non-volatile memory device R connected in series and a two-terminal switching element T2 or T3 (also called 1T1R structure), see FIG. 6a and FIG. 6b;

One end of the series branch formed by the nonvolatile memory device and the two-terminal switching element is connected to the bit line BL, and the other end is connected to the source line SL. Refer to FIG. 7 for the structure of the nonvolatile memory cell array (referred to as the cross-point array) formed by the arrangement of the nonvolatile memory cell array.

In the 1T1R cell structure, the state of the nonvolatile memory device (usually two states, a low-impedance state representing a logic 0 and a high-impedance state representing a logic 1, or vice versa) depends on the bit line BL and the source line The voltage difference on SL (note: high voltage represents 1, low voltage represents 0), when the voltage difference between the bit line BL and the source line SL exceeds a certain threshold, the state of the non-volatile memory device is flipped (regardless of the current any state), when the voltage between the bit line BL and the source line SL does not exceed the threshold, the state of the non-volatile memory device remains in the initial state, such as a unidirectional RRAM device, an electric field regulated MRAM device, and the like. Based on this principle, the inventor found through extensive research and analysis that the above-mentioned 1T1R structure can be used to realize the XNOR operation. As shown in Figure 8a, Figure 8b, and Figure 8c, let the voltage on BL be the input operand A, the voltage on SL be the input operand C, and the data currently stored in the non-volatile memory device be the operand Bi, then it can be Get the truth table, referring to FIG. 9 , it can be seen that when C=0, Bi and A perform exclusive OR (XOR) operation, but when C=1, Bi and A perform exclusive OR (XNOR) operation.

A large number of studies by the inventor have found that the process of the MAC operation of two vectors can be equivalent to the accumulation of the same-or operation (XNOR) of each element of two items, for example, sequence A=[0101] and B=[ 1011], A*B=a1*b1+a2*b2+a3*b3+a4*b4=a1⊙b1+a2⊙b2+a3⊙b3+a4⊙b4=1. Wherein, the symbol of XNOR is ⊙, and XNOR=XOR (exclusive OR operation ⊕) is inverse.

Based on the above principles, for the nonvolatile memory cell arrays shown in FIG. 5 and FIG. 7 , the XNOR operation of two vectors can be realized by adding peripheral circuits.

FIG. 10 a shows a circuit structure for implementing exclusive OR logic operations or exclusive OR logic operations by using the nonvolatile memory cell array shown in FIG. 5 . As shown in Figure 10a, each bit line is connected to an amplifier (equivalent to the read-write unit of the read-write circuit), and the output terminals of each amplifier are connected to a counter, and the counter counts the data representing 1 in the read data , and the counting result is used as the operation result of the non-volatile in-memory computing module.

The operation data B={b ₁ ,b ₂ ,...,b _M } (for neural network operations, B is equivalent to the weight data of a certain layer, for convolutional neural network operations, B is equivalent to convolution kernel data) can be stored In a row of non-volatile memory cells (through the read-write circuit and the row-column decoder, by controlling the voltage difference between the bit line and the source line), the representation A={a ₁ ,a ₂ ,…,a _M } The signal is loaded on the bit lines of the non-volatile memory cells in this row, and the NOR instruction {1,1,...,1} is loaded on the source lines of the non-volatile memory cells. When all the bit lines are high, Under the action of A, XNOR operation is performed in each unit, and XNOR operation of A and B is performed corresponding to each row. Finally, by gating different WL, reading the state of unit 1 of each row and accumulating through the counter can be realized. MAC operation.

Those skilled in the art can understand that the XOR operation instruction {0,0,...,0} can also be loaded on the source line of the non-volatile storage unit, and under the action of A, XOR is performed in each unit Operation, corresponding to each row to perform the XOR operation of A and B, and finally by gating different WL, read the state of unit 0 of each row and accumulate it through the counter, and also realize the MAC operation.

Fig. 10b shows another circuit structure that utilizes the nonvolatile memory cell array shown in Fig. 5 to realize NOR logic operation or XOR logic operation; As shown in Fig. 10b, the amplifier is connected to each bit line for The total analog current/voltage on each bit line is compared with the reference information, and the calculation result of the calculation module in the non-volatile memory is output.

The operation data B={b ₁ ,b ₂ ,...,b _M } (for neural network operations, B is equivalent to the weight data of a certain layer, for convolutional neural network operations, B is equivalent to convolution kernel data) can be stored In a row of non-volatile memory cells (through the read-write circuit and the row-column decoder, by controlling the voltage difference between the bit line and the source line), the representation A={a ₁ ,a ₂ ,…,a _M } The signal is loaded on the bit lines of the non-volatile memory cells in this row, and the NOR instruction {1,1,...,1} is loaded on the source lines of the non-volatile memory cells. When all the bit lines are high, Under the action of A, XNOR operation is performed in each unit, and XNOR operation of A and B is performed corresponding to each row. By reading the total analog current/voltage of all units, the total analog current/voltage of all units is read by the amplifier. The voltage is compared with the reference signal, and the comparison result is used as the MAC operation result.

FIG. 11 a shows a circuit structure for implementing exclusive OR logic operations or exclusive OR logic operations by using the nonvolatile memory cell array shown in FIG. 7 . FIG. 11 b shows another circuit structure for implementing exclusive-or logic operations or exclusive-or logic operations by using the nonvolatile memory cell array shown in FIG. 7 . Its operation principle and circuit description refer to FIG. 10a and FIG. 10b , which will not be repeated here.

FIG. 12 shows the specific structure of the post-processing module 30 in FIG. 1 . Referring to FIG. 12 , the post-processing module 30 includes a plurality of PE channels, respectively realizing post-processing functions of different mid-budget combinations. The PE channel 1 includes: nonlinear function + pooling + batch normalization + activation function. Different PE channels are implemented by combining different types of operations in the required order.

It is worth noting that the post-processing module is a common technology in the art and will not be repeated here.

It is worth noting that the nonvolatile memory cells used in the embodiments of the present invention are preferably resistive change memory cells, phase change memory cells, ferroelectric memory cells, spin memory cells, and the like.

Wherein, the non-volatile in-memory computing chip may also include a controller for controlling the state and timing of the entire chip.

Fig. 13 shows a flowchart 1 of a control method for implementing a multiply-accumulate operation based on non-volatile in-memory calculations in an embodiment of the present invention; The control method can be used to control the above-mentioned non-volatile in-memory computing chip to realize the multiply-accumulate operation.

The control method for implementing multiplication and accumulation operations based on non-volatile in-memory calculations may include the following:

Step S100: Store the first binary operation signal into a row of non-volatile memory cells.

Wherein, each non-volatile storage unit stores one bit of the first binary operation signal.

Specifically, each binary bit is written into a non-volatile memory cell by controlling the voltage difference between the bit line and the source line of the non-volatile memory cell through the cooperation of the row-column decoder and the read-write circuit.

It should be noted that the first binary operation signal represents the first binary operation data.

Step S200: Load the second binary operation signal to the row of non-volatile memory cells.

Wherein, the corresponding bits of the first binary operation signal and the second binary operation signal are applied to the same non-volatile storage unit when performing a multiply-accumulate operation;

Specifically, through the cooperation of the row and column decoder and the read-write circuit, the bit line corresponding to the storage unit of the non-volatile storage unit in the row is configured according to the second binary operation signal.

It should be noted that the second binary operation signal represents the second binary operation data.

Step S300: Load an exclusive-OR operation instruction into the row of non-volatile storage units, so that the row of non-volatile storage units responds to the exclusive-or operation instruction to execute the first binary operation signal and the The second binary operation signal corresponds to the NOR operation of the bits, and the operation result is stored in the corresponding non-volatile storage unit.

Wherein, the same-or operation instruction can be set as all 1s or all 0s, and is configured according to the circuit conditions, and the exclusive-or operation instruction and the same-or operation instruction can be reversed.

Specifically, through the cooperation of the row-column decoder and the read-write circuit, the row of non-volatile memory cells is configured according to an NOR operation instruction.

Step S400: Read and accumulate the data in each non-volatile storage unit in the row of non-volatile storage units to obtain the multiplication and accumulation of each bit of the first binary operation signal and the second binary operation signal Operation result.

Specifically, the data in each non-volatile memory cell in the row of non-volatile memory cells can be read through the cooperation of the row-column decoder and the read-write circuit, and the data in each non-volatile memory cell of the row that is read can be read through the counter. The MAC operation can be realized by counting a specific state of the non-volatile storage unit. Referring to FIG. 10a and FIG. 11a, first, read the data in each non-volatile storage unit in the row of non-volatile storage units; then , counting the data representing 1 in the read data; finally, using the counting result as the result of the multiplication and accumulation operation of each bit of the first binary operation signal and the second binary operation signal.

Or, by reading the total analog current/voltage of all units, compare the total analog current/voltage of all units with the reference signal through the amplifier, and use the comparison result as the result of the MAC operation, refer to Figure 10b and Figure 11b, first , read the total analog current/voltage of all non-volatile memory cells in the row of non-volatile memory cells; then, compare the total analog current/voltage with the first reference signal; finally, use the comparison result as A multiplication and accumulation operation result of each bit of the first binary operation signal and the second binary operation signal.

Through the above-mentioned technical solution, the present invention can use the above-mentioned control method to control the above-mentioned non-volatile in-memory calculation to realize the multiplication and accumulation operation, without the need to transmit data between the memory and the processor, reducing power consumption and delay.

Fig. 14 shows the second flow chart of the control method for implementing the multiply-accumulate operation based on the non-volatile in-memory calculation in the embodiment of the present invention; The control method can be used to control the above-mentioned non-volatile in-memory computing chip to realize the multiply-accumulate operation.

The control method shown in FIG. 14 based on non-volatile in-memory calculations to realize multiply-accumulate operations is the same as the control method shown in FIG. The characteristic storage unit utilizes the principle that the same OR operation is the inversion of the XOR operation, and when the operation result is read, the data representing 0 in the read data is counted; finally, the count result is used as the first binary A multiplication and accumulation operation result of each bit of the operation signal and the second binary operation signal.

Or, by reading the total analog current/voltage of all units, compare the total analog current/voltage of all units with the reference signal through the amplifier, and use the comparison result as the result of the MAC operation. The reference signals used in the exclusive OR operation are different, and other principles are the same as those in the exclusive OR operation, which will not be repeated here.

FIG. 15 shows a flow chart of a control method for implementing binary neural network operations based on non-volatile in-memory calculations in an embodiment of the present invention. As shown in Figure 15, the control method for implementing binary neural network operations based on non-volatile in-memory calculations may include the following:

Step S1000: storing at least one binary weight signal (equivalent to Bi) into at least one row of non-volatile storage units;

It is worth noting that, referring to Fig. 16, the neural network operation includes multiple layers, each layer is used to perform MAC operation on the input data and weight data, and the operation result is used as the input of the next layer.

Wherein, one bit of the binary weight signal is stored in each non-volatile storage unit.

Specifically, each binary bit is written into a non-volatile memory cell by controlling the voltage difference between the bit line and the source line of the non-volatile memory cell through the cooperation of the row-column decoder and the read-write circuit.

In addition, for convolutional neural networks, one layer may correspond to multiple convolution kernels. At this time, the data corresponding to each convolution kernel is used as a weight data, and the multiple weight data corresponding to multiple convolution kernels are respectively It is written into multiple rows of non-volatile storage units, so as to realize the operations corresponding to multiple convolution kernels at the same time.

Step S2000: Load the characteristic signal (equivalent to A) to the row of non-volatile memory cells.

The corresponding bits of the binary weight signal and the characteristic signal are applied to the same non-volatile storage unit when performing a multiply-accumulate operation;

Specifically, through the cooperation of row and column decoders and read-write circuits, the bit lines corresponding to the storage cells of the row of non-volatile memory cells are configured according to the characteristic signal.

Step S3000: Load the exclusive-OR operation instruction into the non-volatile storage unit of the row, so that the non-volatile storage unit of the row performs the correspondence between the binary weight signal and the characteristic signal in response to the exclusive-or operation instruction. bit exclusive OR operation, and store the operation result in the corresponding non-volatile storage unit;

Wherein, the same-or operation instruction can be set as all 1s or all 0s, and is configured according to the circuit conditions, and the exclusive-or operation instruction and the same-or operation instruction can be reversed.

Specifically, through the cooperation of the row-column decoder and the read-write circuit, the row of non-volatile memory cells is configured according to an NOR operation instruction.

Step S4000: Read and accumulate the data in each non-volatile storage unit in the row of non-volatile storage units, and obtain the multiplication-accumulation operation result of each bit of the binary weight signal and the characteristic signal.

Specifically, the data in each non-volatile storage unit in the row of non-volatile storage units can be read through the cooperation of the row-column decoder and the read-write circuit, and the data in each non-volatile storage unit in the row can be read through the counter. A certain state of counting can realize the MAC operation, referring to Fig. 10a and Fig. 11a, first, read the data in each non-volatile memory unit in the non-volatile memory unit of this row; Then, to read The data representing 1 in the data is counted; finally, the counting result is used as the result of the multiplication and accumulation operation of each bit of the weight signal and the characteristic signal.

Or, by reading the total analog current/voltage of all units, compare the total analog current/voltage of all units with the reference signal through the amplifier, and use the comparison result as the result of the MAC operation, refer to Figure 10b and Figure 11b, first , read the total analog current/voltage of all non-volatile memory cells in the row of non-volatile memory cells; then, compare the total analog current/voltage with the first reference signal; finally, use the comparison result as The multiplication and accumulation operation result of each bit of the weight signal and the feature signal.

It is worth noting that, assuming that the weight data itself is stored in the non-volatile memory cell array, then, firstly, the weight data B _i needs to be read out to the cache module (because during the operation, the operation result B _i+1 is stored in the current unit , which means that the initial weight data B _i will be destroyed, so when executing the MAC operation, it is necessary to copy B _i to the cache module first, and then write it back after execution);

In addition, if the weight data is stored in an off-chip memory, the weight data is first imported into a non-volatile memory cell array.

From the above technical solution, it can be known that the present invention can use the above control method to control the above-mentioned non-volatile in-memory calculation to realize the neural network operation, especially for the convolutional neural network operation, the effect is better and obvious, and there is no need for memory and processor Transfer data between, reduce power consumption and delay.

In an optional embodiment, the control method for implementing binary neural network operations based on non-volatile in-memory calculations may also include:

The result of the multiply-accumulate operation is cached as a feature signal of the next layer.

Specifically, the result of the multiply-accumulate operation is cached in the cache module for subsequent use.

In an optional embodiment, the control method for implementing binary neural network operations based on non-volatile in-memory calculations may also include:

The result of the multiply-accumulate operation is post-processed to obtain the result of the binary neural network operation.

Specifically, the post-processing may include operations such as pooling, batch normalization, shifting, offset, averaging, maximum and minimum values, and activation functions.

Those skilled in the art can understand that, for the above-mentioned control method based on non-volatile in-memory calculations to realize binary neural network operations, an XOR operation instruction can be used to replace the XOR operation instruction, because the XOR operation is the same as the XOR operation The results are mutually reciprocal. Therefore, if the number of 1s in the storage unit is counted when the exclusive OR operation is used, then the number of 0s in the storage unit is counted when the XOR operation is used. The principle is the same as the above method. Let me repeat.

In the present invention, specific examples have been applied to explain the principles and implementation methods of the present invention. The description of the above examples is only used to help understand the method of the present invention and its core idea; meanwhile, for those of ordinary skill in the art, according to this The idea of the invention will have changes in the specific implementation and scope of application. To sum up, the contents of this specification should not be construed as limiting the present invention.

It should also be noted that the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes Other elements not expressly listed, or elements inherent in the process, method, commodity, or apparatus are also included. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for the related parts, please refer to the part of the description of the method embodiment.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art, Within the scope of not departing from the technical solution of the present invention, when the technical content disclosed above can be used to make some changes or be modified into equivalent embodiments with equivalent changes, but all the content that does not depart from the technical solution of the present invention, according to the technical content of the present invention Technical Essence Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

Claims (13)

1. A computing chip in a non-volatile memory, characterized in that, comprising: A cache module for caching data; A non-volatile in-memory computing module, connected to the cache module, for performing operations on the data sent by the cache module; A post-processing module, connected to the non-volatile in-memory computing module, for post-processing the calculation results of the non-volatile in-memory computing module; Wherein, the non-volatile in-memory computing module includes: a non-volatile memory cell array, a row-column decoder connected to the non-volatile memory cell array, a reader connected to the non-volatile memory cell array Write the circuit. 2. The non-volatile in-memory computing chip according to claim 1, wherein the cache module comprises: a first cache unit and a second cache unit, The first cache unit is connected to the front end of the non-volatile in-memory computing module, and is used to receive and cache input data and feature map data; The second cache unit is connected to the non-volatile in-memory computing module for caching weight data. 3. The non-volatile in-memory computing chip according to claim 1, wherein the row-column decoder comprises: a row decoder and a column decoder, and the non-volatile memory cell array comprises : non-volatile storage units arranged in multiple arrays; Each row of nonvolatile memory cells is connected to the column decoder through a bit line, and each row of nonvolatile memory cells is connected to the row decoder through a word line. The bit of each row of nonvolatile memory cells Both the source line and the source line are connected to the read-write circuit. 4. The non-volatile in-memory computing chip according to claim 3, wherein the non-volatile storage unit comprises: a non-volatile storage device and a three-terminal switch element connected in series; One end of the non-volatile memory device is connected to the bit line, the other end is connected to the first end of the three-terminal switch element, the second end of the three-terminal switch element is connected to the word line, and the three-terminal switch The third end of the element is connected to the source line. 5. The non-volatile in-memory computing chip according to claim 1, wherein the row-column decoder comprises: a row decoder and a column decoder, and the non-volatile memory cell array comprises : non-volatile storage units arranged in multiple arrays; Each row of nonvolatile memory cells is connected to the column decoder through a bit line, and each row of nonvolatile memory cells is connected to the row decoder through a source line. The bit of each row of nonvolatile memory cells Both the source line and the source line are connected to the read-write circuit. 6. The non-volatile in-memory computing chip according to claim 5, wherein the non-volatile storage unit comprises: a non-volatile storage device connected in series and a two-terminal switching element; One end of the series branch formed by the nonvolatile memory device and the two-terminal switching element is connected to the bit line, and the other end is connected to the source line. 7. The non-volatile in-memory computing chip according to any one of claims 3 or 5, further comprising: an amplifier connected to each bit line for converting The total analog current/voltage is compared with the reference information, and the calculation result of the non-volatile memory calculation module is output. 8. The non-volatile in-memory computing chip according to any one of claims 3 or 5, further comprising: a counter, the counter is connected to the read-write circuit, and the output of the counter is used as a non-volatile The operation result of the volatile in-memory computing module. 9. The non-volatile in-memory computing chip according to any one of claims 4 or 6, wherein the non-volatile storage unit is a resistive storage unit, a phase-change storage unit, or a ferroelectric storage unit , Spin storage unit. 10. A control method based on non-volatile in-memory calculations to realize multiply-accumulate operations, characterized in that it comprises: storing the first binary operation signal into a row of non-volatile storage units, and storing one bit of the first binary operation signal in each non-volatile storage unit; The second binary operation signal is loaded to the row of non-volatile storage units, and the corresponding bits of the first binary operation signal and the second binary operation signal are applied to the same non-volatile storage when the multiplication and accumulation operation is performed. unit; Loading an NOR operation instruction into the row of nonvolatile storage units, so that the row of nonvolatile storage units responds to the NOR operation instruction to execute the first binary operation signal and the second binary operation signal. Exclusive OR operation of the corresponding bit of the binary operation signal, and store the operation result in the corresponding non-volatile storage unit; Reading and accumulating the data in each non-volatile storage unit in the row of non-volatile storage units to obtain a multiplication-accumulation operation result of each bit of the first binary operation signal and the second binary operation signal. 11. A control method based on non-volatile in-memory calculations to realize binary neural network operations, comprising: storing at least one binary weight signal in at least one row of non-volatile storage units, and storing one bit of the binary weight signal in each non-volatile storage unit; Loading the feature signal to the row of non-volatile storage units, and applying the corresponding bit when the binary weight signal and the feature signal perform a multiplication-accumulation operation to the same non-volatile storage unit; Loading the NOR operation instruction to the non-volatile storage unit of the row, so that the non-volatile storage unit of the row responds to the NOR operation instruction to perform the same operation of the binary weight signal and the corresponding bit of the characteristic signal. OR operation, and store the operation result in the corresponding non-volatile storage unit; Reading and accumulating the data in each non-volatile storage unit in the row of non-volatile storage units to obtain a multiplication-accumulation operation result of each bit of the binary weight signal and the characteristic signal. 12. The control method for realizing binary neural network operations based on non-volatile in-memory calculations according to claim 11, further comprising: The result of the multiply-accumulate operation is cached as a feature signal of the next layer. 13. The control method for realizing binary neural network operations based on non-volatile in-memory calculations according to claim 11, further comprising: The result of the multiply-accumulate operation is post-processed to obtain the result of the binary neural network operation.