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CN119384111A - Flexible silicon wafer and preparation method thereof, and flexible solar cell prepared using the flexible silicon wafer - Google Patents

Flexible silicon wafer and preparation method thereof, and flexible solar cell prepared using the flexible silicon wafer Download PDF

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Publication number
CN119384111A
CN119384111A CN202411978257.4A CN202411978257A CN119384111A CN 119384111 A CN119384111 A CN 119384111A CN 202411978257 A CN202411978257 A CN 202411978257A CN 119384111 A CN119384111 A CN 119384111A
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silicon wafer
area
dielectric film
amorphous silicon
layer
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毛卫平
姚美灵
花灯根
廖纪星
施栓林
黄强
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Zhongnengchuang Photoelectric Technology Changzhou Co ltd
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Zhongnengchuang Photoelectric Technology Changzhou Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The invention discloses a flexible silicon wafer, a preparation method thereof and a flexible solar cell prepared by adopting the flexible silicon wafer. The preparation method of the flexible silicon wafer comprises the steps of polishing the front side and the back side of the silicon wafer by adopting polishing solution, depositing a thick dielectric film on the back side area of the silicon wafer by adopting an ALD method or a PECVD method, winding a thick dielectric film on the side area and the front side edge area of the silicon wafer, forming a thin dielectric film in a transition area between the thick dielectric film on the front side edge area of the silicon wafer and a middle non-mask area, texturing the transition area covered by the middle area and the thin dielectric film of the silicon wafer by adopting alkaline solution, removing the thick dielectric film in other areas by adopting an acidic solution containing HF, and cleaning the silicon wafer. The method can improve the bending strength of the silicon wafer, improve the flexibility of HJT batteries and expand the application range of thin HJT batteries.

Description

Flexible silicon wafer, preparation method thereof and flexible solar cell prepared by adopting flexible silicon wafer
Technical Field
The invention relates to the technical field of batteries, in particular to a flexible silicon wafer, a preparation method thereof and a flexible solar battery prepared by adopting the flexible silicon wafer.
Background
Crystalline silicon solar cells are the most widely used solar cells in today's society and are seen everywhere in daily life. Besides the large-scale application of the conventional solar cell in a ground photovoltaic power station and distributed photovoltaic, the flexible solar cell also has huge development space in the fields of wearable electronics, mobile communication, vehicle-mounted mobile energy, photovoltaic building integration, aerospace and the like. However, the conventional crystalline silicon solar cell cannot be bent, and has high brittleness and other limitations, so that the flexible application scene of the crystalline silicon solar cell is limited.
The thickness of the silicon wafer is reduced to realize certain bending property, but as the crystalline silicon is an indirect band gap semiconductor, the current density of the battery can be obviously reduced due to the reduction of the thickness of the silicon wafer, and the photoelectric conversion efficiency is greatly reduced. In the existing crystalline silicon battery, the high-temperature processes of PERC and TOPCon are easy to cause silicon wafer warpage and limit silicon wafer thinning, compared with the preparation process of PERC and TOPCon, HJT is lowest in temperature, the HJT low-temperature process is suitable for silicon wafer flaking, and certain flexibility can be achieved by adopting a HJT battery and combining a thin silicon wafer. However, with conventional thin HJT cells, the areas that are particularly subjected to stress concentrations remain susceptible to fracture under mechanical shock and vibration conditions.
Chinese patent application No. CN116435403A proposes stacking textured silicon wafers, and performing plasma edge etching on the silicon to smooth the texture of the edge area. In the process of etching the pyramid at the edge of the silicon wafer, the method is easy to generate new surface relief, and introduces new stress concentration points, so that the bending strength of the silicon wafer is not increased and reduced.
Chinese patent application No. CN116230787A proposes to glue the edge of a polished silicon wafer, baking the polished silicon wafer to protect the polished silicon wafer as a mask, making texture in the middle of the silicon wafer, removing the glue, and forming the silicon wafer with the polished edge and the texture in the middle. The method has complex process, high cost for coating the adhesive film and treating the organic wastewater, and is not suitable for mass production.
Therefore, it is necessary to develop a new method for preparing an edge-smoothed silicon wafer, to improve the bending strength of the silicon wafer, to improve the flexibility of HJT cells, and to expand the application range of thin HJT cells.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a flexible silicon wafer, a preparation method thereof and a flexible solar cell prepared by adopting the flexible silicon wafer.
The invention provides a flexible silicon wafer, the front surface of which comprises three parts, namely a middle area, a transition area extending from the boundary of the middle area to the central direction of the middle area by a preset width and a front surface edge area except the middle area and the transition area, wherein the middle area and the transition area of the front surface of the silicon wafer are provided with pyramid suede, the pyramid size of the middle area is larger than that of the transition area, and the front surface edge area is a polished surface.
The invention also provides a preparation method of the flexible silicon wafer, which comprises the steps of polishing the front surface and the back surface of the silicon wafer, winding a thick dielectric film on the edge area of the front surface of the silicon wafer, forming a thin dielectric film in the transition area between the thick dielectric film on the edge area of the front surface of the silicon wafer and the middle non-mask area, using the dielectric film as a mask, texturing the middle area and the transition area of the silicon wafer to form pyramid suede surfaces with different sizes, removing the thick dielectric film on the edge area of the front surface of the silicon wafer to form a polished surface, and cleaning the surface of the silicon wafer.
The invention also provides a flexible solar cell, which comprises the flexible silicon wafer.
The invention also provides a preparation method of the silicon heterojunction battery, which comprises the following steps:
(1) Polishing the front and back surfaces of the silicon wafer by adopting a polishing solution;
(2) Depositing a thick dielectric film on the back surface area of the silicon wafer by adopting an ALD (atomic layer deposition) method or a PECVD (plasma enhanced chemical vapor deposition) method, plating the thick dielectric film around the side surface area and the front edge area of the silicon wafer, and forming a thin dielectric film in a transition area between the thick dielectric film on the front edge area of the silicon wafer and a middle non-mask area;
(3) Etching the transition area covered by the middle area and the thin dielectric film of the silicon wafer by adopting alkaline solution, removing the thick dielectric film of other areas by adopting acid solution containing HF, and cleaning the silicon wafer;
(4) Depositing a first intrinsic amorphous silicon layer and a first doped amorphous silicon layer on the front surface of the silicon wafer in sequence by adopting a CVD method;
(5) Depositing a first transparent conductive film layer on the first doped amorphous silicon layer by adopting a PECVD method, and depositing a second transparent conductive film layer on the second doped amorphous silicon layer;
(6) And printing low-temperature conductive metal paste on the front surface and the back surface of the silicon wafer respectively by adopting a printing process, and respectively curing to form a first metal electrode and a second metal electrode.
The invention has the following beneficial effects:
The invention provides a flexible silicon wafer, a preparation method thereof and a flexible solar cell prepared by adopting the flexible silicon wafer, and the front surface of the flexible silicon wafer comprises three parts: the polishing device comprises a middle area, a transition area and a front edge area, wherein the middle area and the transition area are provided with pyramid suedes, the pyramid size of the middle area is larger than that of the transition area, and the front edge area is a polishing surface. According to the silicon wafer, the front edge area of the silicon wafer is the polished surface, more energy can be consumed in the breaking process, the phenomenon that the silicon wafer is broken due to the fact that stress is concentrated at the bottom of the edge pyramid during bending of the silicon wafer is avoided, the bending strength of the silicon wafer is greatly improved, in addition, a pyramid suede structure with smaller size than that of the middle area exists in the transition area of the front of the silicon wafer, stress concentration of the pyramid suede can be further prevented, and the bending strength of the silicon wafer is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a HJT cell structure provided in comparative example 1, numbered 1-N single crystal silicon wafer, 2-first intrinsic amorphous silicon layer, 3-first doped amorphous silicon layer, 4-first transparent conductive film layer, 5-first metal electrode, 6-second intrinsic amorphous silicon layer, 7 second doped amorphous silicon layer, 8-second transparent conductive film layer, 9-second metal electrode;
FIG. 2 is a flow chart of the HJT cell preparation process provided in comparative example 1;
FIG. 3 is a schematic view of a flexible silicon wafer provided in example 1, numbered 1-1-middle region, 1-3-transition region, 1-2-front side edge region;
FIG. 4 is a schematic diagram of a silicon heterojunction cell provided in example 2, numbered 1-N monocrystalline silicon wafer, 2-first intrinsic amorphous silicon layer, 3-first doped amorphous silicon layer, 4-first transparent conductive film layer, 5-first metal electrode, 6-second intrinsic amorphous silicon layer, 7-second doped amorphous silicon layer, 8-second transparent conductive film layer, 9-second metal electrode;
fig. 5 is a flow chart of a process for preparing a silicon heterojunction cell provided in example 2.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below. The specific conditions are not noted in the examples and are carried out according to conventional conditions or conditions recommended by the manufacturer. The reagents or apparatus used were conventional products commercially available without the manufacturer's attention.
The flexible silicon wafer, the preparation method thereof and the flexible solar cell prepared by the flexible silicon wafer are specifically described below.
In a first aspect, an embodiment of the present invention provides a flexible silicon wafer, where the front surface of the flexible silicon wafer includes three portions, a middle region, a transition region extending from a boundary of the middle region to a central direction of the middle region by a preset width, and a front surface edge region except for the middle region and the transition region, where the middle region and the transition region have pyramid suedes, and a pyramid size of the middle region is greater than a pyramid size of the transition region, and the front surface edge region is a polished surface.
Pyramid suede exists on the edge surface and the side surface of a silicon wafer of the HJT battery prepared at present, so that stress is easily concentrated at the bottom of an edge pyramid in the bending process of the battery, and cracks are generated to cause the rupture of the battery.
In order to improve the bending strength of a silicon wafer, improve the flexibility of a solar cell and expand the application of a thin solar cell, the embodiment of the invention provides a flexible silicon wafer, the front surface of the silicon wafer comprises 3 parts, namely a middle area, a transition area and a front surface edge area, wherein pyramid suedes are arranged in the transition area among the middle area, the middle area and the front surface edge area, the front surface edge area is of a polishing structure without the pyramid suedes, the smooth edge area consumes more energy in the breaking process, the stress is concentrated at the bottom of an edge pyramid when the silicon wafer is bent, the silicon wafer is prevented from being broken, and the bending strength of the silicon wafer is greatly improved. The transition area is provided with pyramid suede with smaller size than the middle area, so that stress concentration of the straight suede can be further prevented, and bending strength of the silicon wafer is improved. Therefore, the thin crystalline silicon wafer has flexible structural characteristics, the flexibility of the crystalline silicon wafer is obviously improved, and the thin crystalline silicon wafer can be widely applied to silicon heterojunction (HJT, SHJ, HIT) solar cells, tunnel oxide passivation contact (TOPCon) solar cells, passivation emitter and back (PERC), interdigital Back Contact (IBC) solar cells and the like, and has wide application prospects and practical values.
In some alternative embodiments, the back and side regions of the flexible silicon wafer are also polished surfaces.
The embodiment of the invention provides a flexible silicon wafer, wherein the front edge area, the side area and the back area of the flexible silicon wafer are polished surfaces, and pyramid suede surfaces are only arranged in the middle area and the transition area of the front surface of the silicon wafer. The flexible silicon wafer with the structure can enable the crystal silicon wafer to have the characteristic of flexibility on the basis of not changing the surface reflectivity, so that the mechanical property is improved, the smooth edge area consumes more energy in the breaking process, the bending strength of the silicon wafer is greatly improved, the polished surface is adopted on the back surface, the surface passivation is obviously improved compared with the textured surface, the Voc of the battery is improved, the internal reflection of long-wave light is further enhanced, the short-circuit current Jsc is improved, and therefore the battery efficiency is further improved. In addition, the surface area of the polished surface of the back is lower than that of the pyramid suede, so that the ITO consumption can be reduced, and the battery cost is reduced.
In some alternative embodiments, the front edge region has a width of 0.5mm to 3mm, the transition region has a width of 20 μm to 200 μm, the middle region has a pyramid size of 1 μm to 3 μm, and the transition region has a pyramid size of 0.7 μm to 1.5 μm.
The embodiment of the invention also provides a preparation method of the flexible silicon wafer, which comprises the steps of polishing the front surface and the back surface of the silicon wafer, winding a thick dielectric film on the edge area of the front surface of the silicon wafer, forming a thin dielectric film in a transition area between the thick dielectric film on the edge area of the front surface of the silicon wafer and a middle non-mask area, using the dielectric film as a mask, texturing the middle area and the transition area of the silicon wafer to form pyramid suede surfaces with different sizes, removing the thick dielectric film on the edge area of the front surface of the silicon wafer to form a polished surface, and cleaning the surface of the silicon wafer.
In some alternative embodiments, the method comprises the steps of:
(1) Polishing the front and back surfaces of the silicon wafer by adopting a polishing solution;
(2) Depositing a thick dielectric film on the back surface area of the silicon wafer by adopting an ALD (atomic layer deposition) method or a PECVD (plasma enhanced chemical vapor deposition) method, plating the thick dielectric film around the side surface area and the front edge area of the silicon wafer, and forming a thin dielectric film in a transition area between the thick dielectric film on the front edge area of the silicon wafer and a middle non-mask area;
(3) And (3) texturing the intermediate region of the silicon wafer and the transition region covered by the thin dielectric film by adopting an alkaline solution, removing the thick dielectric film in other regions by adopting an acidic solution containing HF, and cleaning the silicon wafer.
In some optional embodiments, in the step (2), the deposition temperature is controlled to be 300-400 ℃, the deposited dielectric film is at least one of SiO x、SiNx、SiOxNy, the thickness of the deposited thick dielectric film in the front edge area, the side area and the back area of the silicon wafer is 20-150 nm, and the thickness of the thin dielectric film in the transition area is 1-20 nm.
In some optional embodiments, in the step (3), alkaline solution is adopted to make texture in an unmasked area and a transition area in the middle of the silicon wafer so as to form pyramid texture of 1-3um in the middle area, the transition area forms pyramid texture of 0.7-1.5 um, the alkaline solution contains NaOH, texture making additive and water, the temperature of the alkaline solution is controlled to be 70-85 ℃, and the polished surface is reserved in the back area, the side area and the front edge area of the silicon wafer under the blocking of a dielectric film.
In a third aspect, an embodiment of the present invention further provides a flexible solar cell, where the flexible solar cell includes the flexible silicon wafer described above.
In some alternative embodiments, the flexible solar cell comprises a silicon heterojunction solar cell, a tunnel oxide passivation contact solar cell, or a back contact solar cell.
In some optional embodiments, the silicon heterojunction solar cell has a structure that a flexible silicon wafer is used as a matrix, a first intrinsic amorphous silicon layer, a first doped amorphous silicon layer, a first transparent conductive film layer and a first metal electrode are sequentially arranged on the front surface of the flexible silicon wafer, a second intrinsic amorphous silicon layer, a second doped amorphous silicon layer, a second transparent conductive film layer and a second metal electrode are sequentially arranged on the back surface of the flexible silicon wafer, wherein:
the flexible silicon wafer is a Czochralski single crystal or an ingot single crystal and comprises an n-type doped or p-type doped single crystal silicon wafer;
The first intrinsic amorphous silicon layer is a composite film layer of one or more of undoped amorphous silicon, amorphous silicon oxide and amorphous silicon carbide semiconductor films;
The first doped amorphous silicon layer is an n-type doped or p-type doped amorphous silicon layer and comprises one or a combination of more than one of amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon oxide and microcrystalline silicon carbide semiconductor film;
the first transparent conductive film layer is a composite layer of one or more of doped indium oxide, zinc oxide or tin oxide;
the first metal electrode is one or more than one compound layers of Ag, cu, al, ni;
the second intrinsic amorphous silicon layer is a composite film layer of one or more of undoped amorphous silicon, amorphous silicon oxide and amorphous silicon carbide semiconductor films;
The second doped amorphous silicon layer is an n-type doped or p-type doped amorphous silicon layer and comprises one or a combination of more than one of amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon oxide and microcrystalline silicon carbide semiconductor thin films;
The second transparent conductive film layer is a composite layer of one or more of doped indium oxide, zinc oxide or tin oxide;
the second metal electrode is one or more than one compound layers of Ag, cu, al, ni.
In some alternative embodiments, the flexible silicon wafer has a thickness of 50 μm to 150 μm;
the thickness of the first intrinsic amorphous silicon layer is 4nm-10nm, and the first intrinsic amorphous silicon layer is prepared by PECVD or Cat-CVD deposition;
the thickness of the first doped amorphous silicon layer is 5nm-30nm, and the first doped amorphous silicon layer is prepared by PECVD or Cat-CVD deposition;
The thickness of the first transparent conductive film layer is 60nm-120nm, and the first transparent conductive film layer is prepared by magnetron sputtering or RPD deposition;
The thickness of the first metal electrode is 10 μm-50 μm, and the width is 5 μm-50 μm;
the thickness of the second intrinsic amorphous silicon layer is 4nm-10nm, and the second intrinsic amorphous silicon layer is prepared by PECVD or Cat-CVD deposition;
the second doped amorphous silicon layer is prepared by PECVD or Cat-CVD deposition, and the conductivity type of the second doped amorphous silicon layer is opposite to that of the first doped amorphous silicon layer;
the thickness of the second transparent conductive film layer is 60nm-120nm, and the second transparent conductive film layer is prepared by magnetron sputtering or RPD deposition;
the second metal electrode has a thickness of 10 μm-50 μm and a width of 5 μm-50 μm, and is prepared by screen printing, ink-jet printing, laser transfer printing or electroplating.
In a fourth aspect, an embodiment of the present invention further provides a method for preparing a silicon heterojunction battery, including the following steps:
(1) Polishing the front and back surfaces of the silicon wafer by adopting a polishing solution;
(2) Depositing a thick dielectric film on the back surface area of the silicon wafer by adopting an ALD (atomic layer deposition) method or a PECVD (plasma enhanced chemical vapor deposition) method, plating the thick dielectric film around the side surface area and the front edge area of the silicon wafer, and forming a thin dielectric film in a transition area between the thick dielectric film on the front edge area of the silicon wafer and a middle non-mask area;
(3) Etching the transition area covered by the middle area and the thin dielectric film of the silicon wafer by adopting alkaline solution, removing the thick dielectric film of other areas by adopting acid solution containing HF, and cleaning the silicon wafer;
(4) Depositing a first intrinsic amorphous silicon layer and a first doped amorphous silicon layer on the front surface of the silicon wafer in sequence by adopting a CVD method;
(5) Depositing a first transparent conductive layer on the first doped amorphous silicon layer by adopting a PECVD method, and depositing a second transparent conductive layer on the second doped amorphous silicon layer;
(6) And printing low-temperature conductive metal paste on the front surface and the back surface of the silicon wafer respectively by adopting a printing process, and respectively curing to form a first metal electrode and a second metal electrode.
The invention is further described below with reference to examples.
Example 1
A preparation method of a flexible silicon wafer comprises the following steps:
(1) Polishing the front and back surfaces of the silicon wafer by adopting a polishing solution;
(2) Depositing a thick dielectric film on the back surface area of the silicon wafer by adopting a PECVD method, plating the thick dielectric film around the side surface area and the front edge area of the silicon wafer, and forming a thin dielectric film in the transition area between the thick dielectric film and the middle non-mask area of the front edge area of the silicon wafer;
(3) Etching the thin dielectric films of the unmasked area and the transitional area in the middle of the silicon wafer by adopting alkaline solution to form pyramid suede surfaces with different sizes, taking the dielectric films as masks in other areas, and reserving polished surfaces;
(4) And removing the thick dielectric films in the front edge area, the side area and the back area of the silicon wafer by adopting an HF solution, and cleaning the surface of the silicon wafer.
In the step (1), polishing solution is adopted to polish the surface of the silicon wafer, the alkaline solution is composed of NaOH, polishing additive and water, and the temperature of the alkaline solution is 60-80 ℃.
In the step (2), the deposition temperature is controlled to be 300-400 ℃, the composition of a deposited dielectric film is SiO x, the thickness of a deposited thick dielectric film in the front edge area, the side area and the back area of the silicon wafer is 50-80 nm, and the average thickness of a thin dielectric film in a transition area is 10-20 nm.
In the step (3), alkaline solution is adopted to make wool in an unmasked area and a transition area in the middle of the silicon wafer so as to form pyramid wool surfaces with the thickness of 2-3 mu m in the middle area and pyramid wool surfaces with the thickness of 1-2 mu m in the transition area, the alkaline solution contains NaOH, wool making additives and water, the temperature of the alkaline solution is controlled to be 70-85 ℃, and the polished surfaces of the back area, the side area and the front edge area of the silicon wafer are reserved under the blocking of a thick dielectric film.
And (4) removing the thick dielectric film in other areas by using hydrofluoric acid solution, and cleaning the surface of the silicon wafer by using acid-base solution.
The structure of the flexible silicon wafer prepared by the preparation method is shown in fig. 3, the flexible silicon wafer is provided with a front surface, a back surface opposite to the front surface and side surfaces, wherein the front surface of the flexible silicon wafer is provided with three parts, namely a middle area 1-1, a transition area 1-3 extending from the boundary of the middle area to the central direction of the middle area 1-1 by a preset width, and a front surface edge area 1-2 which is remained except the middle area 1-1 and the transition area 1-3, the middle area 1-1 and the transition area 1-3 of the front surface of the silicon wafer are provided with pyramid suedes, the pyramid size of the middle area 1-1 is larger than that of the transition area 1-3, and the back surface area (not shown), the side surface area (not shown) and the front surface edge area 1-2 are polished surfaces.
Example 2
As shown in figures 3 and 4, a silicon heterojunction cell is formed by taking an N-type monocrystalline silicon wafer 1 as a matrix, wherein the N-type monocrystalline silicon wafer 1 is a flexible silicon wafer and has a front surface, a back surface opposite to the front surface and a side surface, the front surface of the flexible silicon wafer is provided with three parts, namely a middle area 1-1, a transition area 1-3 extending from the boundary of the middle area to the central direction of the middle area 1-1 by a preset width, and a front surface edge area 1-2 except the middle area 1-1 and the transition area 1-3, wherein the middle area 1-1 and the transition area 1-3 of the front surface are provided with a textured pyramid 1, the second transparent conductive layer 8 and the second metal electrode 9, the front surface is provided with a middle area 1-1 and a transition area 1-3, and the front surface is not provided with a pyramid 1-1 and the side surface is not provided with a pyramid 1-3, and the front surface is not provided with a pyramid 1-1.
As shown in fig. 5, a method for preparing the silicon heterojunction battery comprises the following steps:
(1) Polishing the surface (front and back) of the silicon wafer by adopting a polishing solution, wherein an alkaline solution comprises NaOH, a polishing additive and water, and the temperature is 60-80 ℃;
(2) And depositing SiO x dielectric films on the back side area, the side area and the front side edge area of the silicon wafer by adopting a PECVD deposition mode by taking SiH 4 and N 2 O as reaction gases, wherein the deposition temperature is 300-400 ℃, the thickness of SiO x is 20-40 nm, and a transition area of 100-200 mu m exists between the front side edge area and the middle texturing area. The dielectric film in the transition area is thinner, and the average thickness is 10 nm-20 nm;
(3) The method comprises the steps of adopting alkaline solution to texture an unmasked area in the middle of a silicon wafer to form pyramid texture with the size of 2-3 mu m, wherein the alkaline solution contains NaOH, texture-making additive and water, and the temperature is 70-85 ℃, and the back surface area, the side surface area and the front surface edge area of the silicon wafer are blocked by a thick dielectric film to keep a polished surface;
(4) Removing thick dielectric films in other areas by using hydrofluoric acid solution, and cleaning the surface of the silicon wafer by using acid-base solution;
(5) The first intrinsic amorphous silicon layer 2 and the first doped amorphous silicon layer 3 adopt a PECVD deposition mode, and the first intrinsic amorphous silicon layer 2 with the thickness of 4nm to 6nm and the first doped amorphous silicon layer 3 with the thickness of 5nm to 10nm are formed on the front surface of the silicon wafer;
(6) A first transparent conductive film layer 4 of 75nm is deposited on the first doped amorphous silicon layer 3 by PVD method, and a second transparent conductive film layer 8 of 75nm is deposited on the second doped amorphous silicon layer 7. The mass percentage of indium element in the transparent conductive film layer ITO is 90%, and the mass percentage of tin element is 10%. The PVD equipment is filled with Ar and O 2,O2 to Ar flow ratio of 0.025, pressure of 0.5Pa, and substrate temperature is room temperature.
(7) The low-temperature conductive metal paste is printed on the front side and the back side of the silicon wafer respectively by adopting a printing process, the front side and the back side of the silicon wafer are respectively provided with the low-temperature conductive metal paste, the low-temperature metal paste is one of silver-containing Ag and silver-coated copper Ag@Cu-low-temperature metal paste, and then the low-temperature paste is processed by adopting a low-temperature hot air curing mode to form a low-temperature metal paste electrode with ohmic contact, namely a first metal electrode 5 is formed on the front side of the silicon wafer, and a second metal electrode 9 is formed on the back side of the silicon wafer.
Comparative example 1
As shown in fig. 1 and 2, a HJT battery and a method for manufacturing the same include the steps of:
S1, texturing and cleaning, namely, eliminating organic stains and metal impurities on the surface of a silicon wafer by using acid-base chemicals, forming a surface pyramid texture on the surface of a monocrystalline silicon wafer, increasing the absorption of sunlight and reducing reflection, wherein the monocrystalline silicon wafer is a phosphorus doped N-type monocrystalline silicon wafer with the resistivity of 0.1 omega cm-10 omega cm and the thickness of 100 mu m-200 mu m, and then, cleaning the surface of the silicon wafer by adopting an RCA standard cleaning method to remove the surface contamination impurities. Finally, the surface oxide layer is removed with a 2% hydrofluoric acid solution.
S2, PECVD deposition of a front intrinsic amorphous silicon layer, a back intrinsic amorphous silicon layer and a doped amorphous silicon layer, namely, a PECVD deposition mode is adopted to form a 4nm-6nm first intrinsic amorphous silicon layer 2 and a 5nm-10nm first doped amorphous silicon layer 3 on the front surface of a silicon wafer, and a 5nm-7nm second intrinsic amorphous silicon layer 6 and a 8nm-15nm second doped amorphous silicon layer 7 on the back surface of the silicon wafer;
And S3, PVD depositing a front transparent conductive film layer and a back transparent conductive film layer, namely, depositing a 75nm first transparent conductive film layer 4 on the first doped amorphous silicon layer 3 by adopting a PVD method, and depositing a 75nm second transparent conductive film layer 8 on the second doped amorphous silicon layer 7. The mass percentage of indium element in the transparent conductive film layer ITO is 90%, and the mass percentage of tin element is 10%. The PVD equipment is filled with Ar and O 2,O2 to Ar flow ratio of 0.025, pressure of 0.5Pa, and substrate temperature is room temperature.
And S4, screen printing/curing the front and back low-temperature metal paste, namely, forming a low-temperature metal electrode on the front and back transparent conductive film layer by utilizing a screen printing low-temperature curing mode, namely, forming a first metal electrode 5 on the front surface of the silicon wafer and forming a second metal electrode 9 on the back surface of the silicon wafer.
Comparative example 2
A texturing sheet, HJT battery and preparation method thereof for plasma edge etching treatment:
S1, texturing and cleaning, namely, eliminating organic stains and metal impurities on the surface of a silicon wafer by using acid-base chemicals, forming a surface pyramid texture on the surface of a monocrystalline silicon wafer, increasing the absorption of sunlight and reducing reflection, wherein the monocrystalline silicon wafer is a phosphorus doped N-type monocrystalline silicon wafer with the resistivity of 0.1 omega cm-10 omega cm and the thickness of 100 mu m-200 mu m;
S2, stacking the silicon chips in an ICP plasma etching chamber, and etching the pyramid at the edge of the silicon chips by taking CF 4、O2 as reaction gas and controlling power and reaction time;
And S3, cleaning the surface of the silicon wafer by adopting an RCA standard cleaning method to remove surface pollution impurities. Finally, the surface oxide layer is removed with a 2% hydrofluoric acid solution.
S4, preparing HJT batteries by adopting the silicon wafer.
The cells obtained in examples and comparative examples were subjected to performance tests, each parameter of the solar cell was measured using an IV tester, and the cell bending strength was measured using a three-point bending strength test method, and the results are shown in the following table.
As can be seen from the above data, in comparative example 1, HJT cells had pyramid pile surfaces on the edge surfaces and sides, so that stress was easily concentrated on the bottoms of the edge pyramids during bending of the cells, and cracks were generated to fracture the cells. In comparative example 2, new surface relief is easily generated in the process of etching the pyramid at the edge of the silicon wafer by using plasma, a new stress concentration point is introduced, so that the bending strength of the silicon wafer is not increased and reduced, and meanwhile, the new surface relief introduced at the edge causes edge recombination loss, so that the efficiency of the battery is reduced.
According to the technical scheme provided by the invention, the silicon wafer is polished and edge mask is protected, so that the texture surface is formed only in the middle area of the front surface of the silicon wafer in the texturing process. The front edge area, the side surface area and the back surface area of the silicon wafer are polished surfaces, more energy can be consumed in the breaking process, the phenomenon that the silicon wafer breaks due to the fact that stress is concentrated at the bottom of an edge pyramid when the silicon wafer is bent is avoided, and the bending strength of the silicon wafer is greatly improved. And the transition area is provided with a pyramid with a smaller size than the middle suede area, so that the stress concentration of the front suede can be further prevented, and the bending strength of the silicon wafer is improved. The polished surface is adopted on the back surface, the passivation of the surface is obviously improved compared with the surface of the polished surface, the Voc of the battery is improved, the internal reflection of long-wave light is further enhanced, the short-circuit current Jsc is improved, and therefore, the battery efficiency is further improved.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1.一种柔性硅片，其特征在于，所述柔性硅片的正面包括三个部分：中间区域、自所述中间区域边界起向中间区域中心方向延伸预设宽度的过渡区域、及除所述中间区域和所述过渡区域剩余的正面边缘区域，其中：所述硅片正面的中间区域和所述过渡区域具有金字塔绒面，且所述中间区域的金字塔尺寸大于所述过渡区域的金字塔尺寸，所述正面边缘区域为抛光面。1. A flexible silicon wafer, characterized in that the front side of the flexible silicon wafer comprises three parts: a middle area, a transition area extending from the boundary of the middle area to the center of the middle area with a preset width, and a front edge area remaining except the middle area and the transition area, wherein: the middle area and the transition area on the front side of the silicon wafer have a pyramid velvet surface, and the pyramid size of the middle area is larger than the pyramid size of the transition area, and the front edge area is a polished surface. 2.根据权利要求1所述的柔性硅片，其特征在于，所述柔性硅片的背面区域和侧面区域同样为抛光面。2 . The flexible silicon wafer according to claim 1 , wherein the back area and the side area of the flexible silicon wafer are also polished surfaces. 3.根据权利要求1所述的柔性硅片，其特征在于，所述正面边缘区域宽度为0.5mm-3mm，过渡区域的宽度为20μm-200μm，所述中间区域的金字塔尺寸为1μm-3μm，所述过渡区域的金字塔尺寸为0.7μm-1.5μm。3. The flexible silicon wafer according to claim 1 is characterized in that the width of the front edge area is 0.5mm-3mm, the width of the transition area is 20μm-200μm, the pyramid size of the middle area is 1μm-3μm, and the pyramid size of the transition area is 0.7μm-1.5μm. 4.一种根据权利要求1-3中任一项所述的柔性硅片的制备方法，其特征在于，其包括：将硅片正面和背面进行抛光；在所述硅片正面边缘区域绕镀厚介质膜，并在所述硅片正面边缘区域的厚介质膜和中间的非掩膜区之间的过渡区域形成薄介质膜；以介质膜作掩膜，对所述硅片的中间区域和过渡区域进行制绒以形成不同尺寸的金字塔绒面；再去除硅片正面边缘区域的厚介质膜形成抛光面，并对硅片表面进行清洗。4. A method for preparing a flexible silicon wafer according to any one of claims 1 to 3, characterized in that it comprises: polishing the front and back sides of the silicon wafer; coating a thick dielectric film around the edge area of the front side of the silicon wafer, and forming a thin dielectric film in the transition area between the thick dielectric film in the edge area of the front side of the silicon wafer and the middle non-mask area; using the dielectric film as a mask, texturing the middle area and transition area of the silicon wafer to form pyramid velvet surfaces of different sizes; then removing the thick dielectric film in the edge area of the front side of the silicon wafer to form a polished surface, and cleaning the surface of the silicon wafer. 5.根据权利要求4所述的制备方法，其特征在于，包括以下步骤：5. The preparation method according to claim 4, characterized in that it comprises the following steps: （1）采用抛光溶液，对硅片正面、背面进行抛光；(1) Polishing the front and back sides of the silicon wafer using a polishing solution; （2）采用ALD法或PECVD法在硅片的背面区域沉积厚介质膜，并在所述硅片的侧面区域和正面边缘区域绕镀厚介质膜，在所述硅片正面边缘区域的厚介质膜和中间的非掩膜区之间的过渡区域形成薄介质膜；(2) depositing a thick dielectric film on the back side of the silicon wafer by ALD or PECVD, and coating the thick dielectric film on the side and front edge regions of the silicon wafer, and forming a thin dielectric film in the transition region between the thick dielectric film on the front edge region of the silicon wafer and the middle non-mask region; （3）采用碱性溶液对硅片中间区域和薄介质膜覆盖的过渡区进行制绒，然后采用含HF的酸性溶液去除其他区域的厚介质膜，并对硅片进行清洗。(3) Use an alkaline solution to texturize the middle area of the silicon wafer and the transition area covered by the thin dielectric film, and then use an acidic solution containing HF to remove the thick dielectric film in other areas and clean the silicon wafer. 6.根据权利要求5所述的制备方法，其特征在于，所述步骤（2）中，控制沉积温度为300℃~400℃，沉积的介质膜组成为SiOx、SiNx、SiOxNy中的至少一种，所述硅片正面边缘区域、侧面区域、背面区域沉积的厚介质膜厚度为20nm~150nm，所述过渡区域的薄介质膜厚度为1nm-20nm。6. The preparation method according to claim 5, characterized in that in the step (2), the deposition temperature is controlled to be 300°C-400°C, the deposited dielectric film is composed of at least one of SiOx , SiNx , and SiOxNy , the thickness of the thick dielectric film deposited in the front edge region, the side region, and the back region of the silicon wafer is 20nm-150nm, and the thickness of the thin dielectric film in the transition region is 1nm-20nm. 7.根据权利要求5所述的制备方法，其特征在于，所述步骤（3）中，采用碱性溶液，在硅片中间的未掩膜区和过渡区域制绒，以在中间区域形成1μm-3μm的金字塔绒面，过渡区域形成0.7μm-1.5μm的金字塔绒面；所述碱性溶液包含NaOH与制绒添加剂、水，控制所述碱性溶液的温度70℃-85℃；所述硅片的背面区域、侧面区域、正面边缘区域在介质膜的阻挡下，保留抛光面。7. The preparation method according to claim 5 is characterized in that in the step (3), an alkaline solution is used to texture the unmasked area and transition area in the middle of the silicon wafer to form a pyramid texture surface of 1μm-3μm in the middle area and a pyramid texture surface of 0.7μm-1.5μm in the transition area; the alkaline solution contains NaOH, a texturing additive, and water, and the temperature of the alkaline solution is controlled at 70℃-85℃; the back area, side area, and front edge area of the silicon wafer retain the polished surface under the blocking of the dielectric film. 8.一种柔性太阳电池，其特征在于，所述柔性太阳电池包括如权利要求1-3中任一项所述的柔性硅片或权利要求4-7中任一项所述的制备方法制备得到的柔性硅片。8. A flexible solar cell, characterized in that the flexible solar cell comprises a flexible silicon wafer as described in any one of claims 1 to 3 or a flexible silicon wafer prepared by the preparation method as described in any one of claims 4 to 7. 9.根据权利要求8所述的柔性太阳电池，其特征在于，所述柔性太阳电池包括硅异质结太阳电池、隧穿氧化层钝化接触太阳电池或背接触太阳电池；9. The flexible solar cell according to claim 8, characterized in that the flexible solar cell comprises a silicon heterojunction solar cell, a tunneling oxide layer passivation contact solar cell or a back contact solar cell; 所述硅异质结太阳电池的结构为：以柔性硅片为基体，其正面依次设置第一本征非晶硅层、第一掺杂非晶硅层、第一透明导电膜层以及第一金属电极；背面依次设置第二本征非晶硅层、第二掺杂非晶硅层、第二透明导电膜层以及第二金属电极，其中：The structure of the silicon heterojunction solar cell is as follows: a flexible silicon wafer is used as a substrate, a first intrinsic amorphous silicon layer, a first doped amorphous silicon layer, a first transparent conductive film layer and a first metal electrode are sequentially arranged on the front side; a second intrinsic amorphous silicon layer, a second doped amorphous silicon layer, a second transparent conductive film layer and a second metal electrode are sequentially arranged on the back side, wherein: 所述柔性硅片，为直拉单晶或铸锭单晶，包括n型掺杂或p型掺杂单晶硅片；厚度在50μm-150μm；The flexible silicon wafer is a Czochralski single crystal or a cast single crystal, including an n-type doped or p-type doped single crystal silicon wafer; the thickness is 50 μm-150 μm; 所述第一本征非晶硅层，为未掺杂的非晶硅、非晶氧化硅、非晶碳化硅半导体薄膜中的一种或几种的复合膜层；厚度在4nm-10nm；采用PECVD或Cat-CVD沉积制备；The first intrinsic amorphous silicon layer is a composite film layer of one or more of undoped amorphous silicon, amorphous silicon oxide, and amorphous silicon carbide semiconductor films; the thickness is 4nm-10nm; and it is prepared by PECVD or Cat-CVD deposition; 所述第一掺杂非晶硅层，为n型掺杂或p型掺杂非晶硅层，包括非晶硅、非晶氧化硅、非晶碳化硅、微晶硅、微晶氧化硅、微晶碳化硅半导体薄膜中的一种或几种的组合；厚度在5nm-30nm范围内；采用PECVD或Cat-CVD沉积制备；The first doped amorphous silicon layer is an n-type doped or p-type doped amorphous silicon layer, including one or a combination of amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, and microcrystalline silicon carbide semiconductor films; the thickness is in the range of 5nm-30nm; and it is prepared by PECVD or Cat-CVD deposition; 所述第一透明导电膜层，为掺杂的氧化铟、氧化锌或氧化锡中的一种或几种的复合层；厚度在60nm-120nm；采用磁控溅射或RPD方式沉积制备；The first transparent conductive film layer is a composite layer of one or more of doped indium oxide, zinc oxide or tin oxide; the thickness is 60nm-120nm; and it is deposited by magnetron sputtering or RPD; 所述第一金属电极，为Ag、Cu、Al、Ni中的一种或几种的复合层；厚度在10μm-50μm，宽度在5μm-50μm；采用丝网印刷、喷墨印刷、激光转印或电镀方式制备；The first metal electrode is a composite layer of one or more of Ag, Cu, Al, and Ni; the thickness is 10 μm-50 μm, the width is 5 μm-50 μm; and it is prepared by screen printing, inkjet printing, laser transfer or electroplating; 所述第二本征非晶硅层，为未掺杂的非晶硅、非晶氧化硅、非晶碳化硅半导体薄膜中的一种或几种的复合膜层；厚度在4nm-10nm；采用PECVD或Cat-CVD沉积制备；The second intrinsic amorphous silicon layer is a composite film layer of one or more of undoped amorphous silicon, amorphous silicon oxide, and amorphous silicon carbide semiconductor films; the thickness is 4nm-10nm; and it is prepared by PECVD or Cat-CVD deposition; 所述第二掺杂非晶硅层，为n型掺杂或p型掺杂非晶硅层，包括非晶硅、非晶氧化硅、非晶碳化硅、微晶硅、微晶氧化硅、微晶碳化硅半导体薄膜中的一种或几种的组合；厚度在5nm-30nm；采用PECVD或Cat-CVD沉积制备；第二掺杂非晶硅层与第一掺杂非晶硅层导电类型相反；The second doped amorphous silicon layer is an n-type doped or p-type doped amorphous silicon layer, including one or a combination of amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, and microcrystalline silicon carbide semiconductor films; the thickness is 5nm-30nm; it is prepared by PECVD or Cat-CVD deposition; the second doped amorphous silicon layer is opposite to the first doped amorphous silicon layer in conductivity type; 所述第二透明导电膜层，为掺杂的氧化铟、氧化锌或氧化锡中的一种或几种的复合层；厚度在60nm-120nm；采用磁控溅射或RPD方式沉积制备；The second transparent conductive film layer is a composite layer of one or more of doped indium oxide, zinc oxide or tin oxide; the thickness is 60nm-120nm; and it is deposited by magnetron sputtering or RPD; 所述第二金属电极，为Ag、Cu、Al、Ni中的一种或几种的复合层；厚度在10μm-50μm，宽度在5μm-50μm；采用丝网印刷、喷墨印刷、激光转印或电镀方式制备。The second metal electrode is a composite layer of one or more of Ag, Cu, Al, and Ni; the thickness is 10 μm-50 μm, the width is 5 μm-50 μm; and it is prepared by screen printing, inkjet printing, laser transfer or electroplating. 10.一种硅异质结电池的制备方法，其特征在于，包括以下步骤：10. A method for preparing a silicon heterojunction battery, characterized in that it comprises the following steps: （1）采用抛光溶液，对硅片正面、背面进行抛光；(1) Polishing the front and back sides of the silicon wafer using a polishing solution; （2）采用ALD法或PECVD法在硅片的背面区域沉积厚介质膜，并在所述硅片的侧面区域和正面边缘区域绕镀厚介质膜，在所述硅片正面边缘区域的厚介质膜和中间的非掩膜区之间的过渡区域形成薄介质膜；(2) depositing a thick dielectric film on the back side of the silicon wafer by ALD or PECVD, and coating the thick dielectric film on the side and front edge regions of the silicon wafer, and forming a thin dielectric film in the transition region between the thick dielectric film on the front edge region of the silicon wafer and the middle non-mask region; （3）采用碱性溶液对硅片中间区域和薄介质膜覆盖的过渡区进行制绒，然后采用含HF的酸性溶液去除其他区域的厚介质膜，并对硅片进行清洗；(3) Use an alkaline solution to texturize the middle area of the silicon wafer and the transition area covered by the thin dielectric film, then use an acidic solution containing HF to remove the thick dielectric film in other areas and clean the silicon wafer; （4）采用CVD法，在硅片正面依次沉积第一本征非晶硅层和第一掺杂非晶硅层；在硅片背面沉积第二本征非晶硅层和第二掺杂非晶硅层；(4) using a CVD method, sequentially depositing a first intrinsic amorphous silicon layer and a first doped amorphous silicon layer on the front side of the silicon wafer; and depositing a second intrinsic amorphous silicon layer and a second doped amorphous silicon layer on the back side of the silicon wafer; （5）采用PECVD法，在所述第一掺杂非晶硅层上沉积第一透明导电膜层，在所述第二掺杂非晶硅层上沉积第二透明导电膜层；(5) depositing a first transparent conductive film layer on the first doped amorphous silicon layer and depositing a second transparent conductive film layer on the second doped amorphous silicon layer by using a PECVD method; （6）采用印刷工艺，在硅片正面、背面分别印刷低温导电金属浆料，分别固化形成第一金属电极和第二金属电极。(6) Using a printing process, a low-temperature conductive metal paste is printed on the front and back sides of the silicon wafer, and the paste is solidified to form a first metal electrode and a second metal electrode.
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