CN116798465A - Method of operating a memory device and memory device - Google Patents

Abstract

There is provided a method of operating a storage device, comprising: the output node of a cell of a memory device is precharged based on an activation input of the cell. A memory device is provided that includes a precharge circuit configured to precharge an output node of a cell of the memory device based on an activation input for the cell. By using the technical scheme, the power consumption can be reduced.

Description

Methods of operating storage devices and storage devices

Technical field

The present invention relates to the field of circuit technology, and in particular to a precharge circuit.

Background technique

In conventional computing devices, memory functional blocks are separated from processor functional blocks. Retrieve data from memory to perform operations in processor function blocks.

Compute-in-memory (CIM) devices are devices that can perform operations (such as calculations) in memory. This architecture can have the advantage of increasing speed or reducing power consumption. One application example of CIM devices is the implementation of neural networks. Neural networks make extensive use of a multiply-accumulate operation, in which multiple inputs are multiplied by multiple filter weights and then the multiple products are summed. The CIM device may include hardware for performing multiplication and accumulation operations and storage units for storing filter weights.

Contents of the invention

Some aspects relate to a method of operating a memory device, including precharging an output node of a cell based on an activation input for the cell of the memory device.

Some aspects relate to a storage device including a precharge circuit configured to precharge an output node of a cell based on an activation input for the cell of the storage device.

This application precharges the output node of the unit based on the activation input of the unit of the storage device, which can reduce power consumption.

The foregoing summary is provided by way of illustration and is not intended to be limiting.

Description of the drawings

The drawings are not drawn to scale. In the drawings, each identical or nearly identical component shown in the various figures is designated by a similar numeral. For clarity, not every component in every figure is labeled.

Figure 1 shows a high-level block diagram of a CIM device with an array of CIM cells arranged in rows and columns.

FIG. 2 is a block diagram showing functional circuit blocks of the CIM unit and functional circuit blocks that provide signals to the CIM unit.

Figure 3 shows additional details of an example of a CIM unit in which the calculation circuit is configured to perform a multiplication of the input A by the value W stored in the memory unit.

Figures 4A-4C illustrate embodiments for performing precharge based on activation input.

Figures 5A-5C illustrate embodiments for performing precharge based on activation input.

Figure 6 shows that the CIM unit 1 may have a plurality of memory cells storing respective weights W and a demultiplexer 12 providing the input A to the transistor gates of the selected multiplication path corresponding to the selected weight W.

7 illustrates an example of precharge logic that includes a pulse generator configured to generate pulses to initiate precharge in response to changes in any one or more of a plurality of input signals.

Detailed ways

The devices and techniques described in this article allow for reduced power consumption in memory arrays due to precharge operations. The inventors have recognized that conventional techniques for precharging the output node of a cell result in frequent switching of the precharge device connected to the output node due to frequent charging and discharging of the gate capacitance of the precharge device. High power consumption. Power consumption can be reduced by switching precharge devices infrequently. In some embodiments, a precharge operation of a memory cell may be triggered by an activation input corresponding to the memory cell. Since the activation signal changes value relatively infrequently, the precharging device can be switched infrequently, which can reduce the power consumption caused by precharging. Such technology could be used in CIM devices or other devices with memory arrays.

Figure 1 shows a high level block diagram of a CIM device 10 having an array of CIM units 1 arranged in rows and columns. CIM device 10 may have any number of rows and columns. Each CIM unit 1 has at least one memory unit and associated computing circuitry, as discussed further below. Before performing calculation operations, the output nodes of the calculation circuit need to be precharged.

Figure 2 is a block diagram illustrating the functional circuit blocks of the CIM unit 1 according to some embodiments. The CIM unit 1 includes a storage unit 2 , a calculation circuit 3 that performs calculations based on an activation input A and a value W stored in the memory unit, and a precharging device 4 that precharges the output node of the calculation circuit 3 . The precharge logic 5 can control the precharge device 4 to precharge the output node 7 of the calculation circuit 3 with appropriate timing. In some embodiments, precharge device 4 may be turned on (conducted) in response to activation input A. After the precharging operation, the precharging device 4 is turned off (non-conductive). When the CIM device 10 performs a calculation operation, the calculation circuit 3 is prepared to perform calculations using the input A and the value W stored in the storage unit 2 . When the CIM device 10 controls the calculation circuit 3 to perform calculation operations, the calculation results are provided to the output node 7 . The memory unit 2 may be any suitable type of memory unit, such as a static random access memory (SRAM) unit or a ternary content addressable memory (TCAM) unit.

Figure 3 shows additional details of an example of a CIM unit in accordance with some embodiments. In this embodiment, the calculation circuit 3a includes a multiplication path, the multiplication path includes: a first transistor and a second transistor, the first transistor includes a control terminal, a first terminal and a second terminal, wherein the control terminal of the first transistor receives a value W, the second terminal of the first transistor is coupled to the ground, the first terminal of the first transistor is coupled to the second terminal of the second transistor, the second transistor includes a control terminal, a first terminal and a second terminal, and the control terminal of the second transistor The terminal receives the activation input A, and the first terminal of the second transistor is coupled to the node MB. The precharging device 4a may be a PMOS transistor. The PMOS transistor includes a control terminal, a first terminal, and a second terminal. The control terminal of the PMOS transistor receives the signal PRCHG. The first terminal is coupled to the power rail 8 and the second terminal is coupled to the node MB. . The input of the inverter 11 is coupled to the node MB. The weak PMOS device includes a control terminal, a first terminal and a second terminal. The control terminal of the weak PMOS device is coupled to the output of the inverter 11 . The first terminal of the weak PMOS device is coupled to The second end of the power rail 8 is coupled to the node MB. In this example, the calculation circuit 3 a is configured to perform a multiplication of the activation input A by the value W stored in the memory unit 2 . The precharge logic 5 provides signal PRCHG which is used to control the precharge device 4a to precharge the output node 7a, also shown as node MB. The precharge device 4a may be a PMOS transistor controlled to perform a precharge operation in response to the signal PRCHG having a low logic level. During precharge operation, precharge device 4a is conductive and connects output node 7a to power rail 8. The CIM unit 1 may include an inverter 11 that inverts the signal MB of the node MB to generate the signal M. Signal M may be provided to an adder tree to perform the addition portion of the multiply-accumulate calculation. When performing a calculation operation, the input A is multiplied by the value W stored in storage unit 2. Values A and W can be numeric values. If A and W are both logic high, output node 7a is pulled down to ground (logic low). If A or W or both are logic low, output node 7a is not pulled down to ground but remains at the precharge voltage (logic high in this example). The CIM unit 1 may include circuitry for keeping MB at a high logic level when the precharge device is off and A or W or both have a low logic level: in this example, the weak PMOS device performs this function.

Figure 4A shows a circuit diagram of an embodiment of a CIM cell in which the gate of the pre-charging device 4a is connected to the activation input A. As shown in the truth table of Figure 4B, when activation input A has a logic value of 0, pre-charging device 4a conducts and pre-charges node MB to the voltage of power rail 8. Figure 4C shows the timing of activation input A with a low logic value that results in MB being precharged to a high logic value. When a calculation operation is performed and both A and W have high logic values, node MB is pulled down to a low logic value.

Figure 5A shows a schematic diagram of another embodiment in which precharge logic 5a generates precharge signal PRCHG in response to activation input A. The precharge logic 5a includes a pulse generator 51 and other logic circuits. The pulse generator 51 receives the pulse signal CLK and the enable signal EN, and generates the pulse signal PCLK. Other logic circuits include inverters and AND gates. The inverter receives the pulse signal PCLK and outputs the inverted signal of the pulse signal PCLK. One input terminal of the AND gate receives the inverted signal of the pulse signal PCLK, and the other input terminal receives the activation signal. Input A, the output terminal of the AND gate outputs the precharge signal PRCHG. Using the precharge logic 5a, the precharge operation can be initiated by a logic signal A having a low logic level or in response to a pulse signal PCLK generated in response to the enable signal EN. Figure 5C shows the structure of the pulse generator 51. Those skilled in the art can understand that the pulse generator 51 can also adopt other structures and is not limited to the structure shown in Figure 5C. FIG. 5B shows a timing diagram of the signal shown in FIG. 5A , the signal PEN being an internal signal of the pulse generator 51 . In some embodiments, when computing operations are enabled in CIM device 10, enable signal EN may transition from a low logic level to a high logic level. In response, pulse generator 51 may generate pulses that cause an initial precharge operation to be performed. Specifically, referring to Figure 5B, when EN changes from low level to high level, the edge detector (Edge Detector) generates a high level signal PEN. MST LAT is a negative level sensitive latch, and SLV LAT is a positive level sensitive latch. When EN changes from low to high and CLK is low, the MST LAT output is high. At this point, the SLV LAT is disabled, so it holds its previous low value, which is inverted by the inverter (INV). So both inputs of the AND gate are high, making PEN high. If the D input of the pulse generation circuit (Pulsegen) is high before the rising edge of CLK, it generates a pulse. Therefore, if EN changes from low to high, a PCLK pulse is generated. If EN changes from high to low, PEN is low and therefore PCLK is not generated.

Figure 6 shows that the CIM unit may have a plurality of storage units and a demultiplexer 12 for storing respective weights W, and a demultiplexer (DEMUX) 12 for providing the input A to the selected The transistor gate of the selected multiplier path of weight W. The selection signal FA[u:0] is the selection signal of the demultiplexer, which determines which filter weight W is selected and applies the activation signal A to the gate of the transistor RWL corresponding to the selected weight W. Among them, FA[u:0] is the u+1-bit filter address input. W ⁰ , W ¹ ,... ^WR-1 , ^WR in the figure represent the weight, R=2 ^(u+1) -1. RWL[0], RWL[1],...RWL[R-1], RWL[R] in the figure represent transistors.

In some embodiments, the precharge operation may be triggered in response to a change in the selection signal FA[u:0]. To this end, the enable signal EN of the precharge logic 5a may be the selection signal FA[u:0]. Alternatively or additionally, the precharge operation may be triggered in response to a change in any of a plurality of signals, such as an enable signal that switches to a logic high level when computing operations are enabled in the CIM device 10 EN, and FA[u:0]. Precharge logic 5 may activate precharge operation in response to a change in any such signal. Figure 7 shows an example of such precharge logic, such as precharge logic 5b, which includes a pulse generator 71 configured to generate pulses in response to changes in the enable signal EN or the select signal FA[u:0] to start precharging. Among them, when any bit of FA[u:0] changes from low to high or from high to low, the pulse generator 71 will generate a pulse.

The use of sequential terms such as "first", "second", "third", etc. in the claims to modify claim elements does not in itself imply any priority or precedence of one claim element over another claim element. or sequence or temporal order in which method actions are performed, but used only as a label to distinguish one claim element with a specific name from another claim element with the same name (but using ordinal terms).

Additionally, the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. The use of "including," "includes," "having," or "involving" and variations thereof herein is intended to encompass the items listed thereafter and their equivalents as well as additional items.

The use of "coupled" or "connected" means that circuit elements or signals are connected to each other directly or indirectly through intervening elements.

The terms "about," "substantially," and "approximately" may be used in some embodiments to mean within ±20% of a target value, in some embodiments within ±10% of a target value, and in some embodiments within ±10% of a target value. Within ±5% of the target value, and in some embodiments within ±2% of the target value. The terms "about," "substantially," and "approximately" may include target values.

Those skilled in the art will readily observe that many modifications and variations of the apparatus and methods can be made while maintaining the teachings of the present invention. Accordingly, the foregoing disclosure should be construed as being limited only by the metes and bounds of the appended claims.

Claims (23)

1. A method of operating a memory device, the method comprising:

the output node of a cell of a memory device is precharged based on an activation input of the cell.

2. The method of claim 1, wherein the precharging is performed when the activation input has a first logic level.

3. The method of claim 1, wherein the precharging is performed by coupling the output node to a power rail using a transistor.

4. A method according to claim 3, wherein the transistor comprises a PMOS transistor.

5. The method of claim 1, wherein the storage device is a memory-integrated CIM device, and the unit includes a storage unit and a computing circuit configured to perform a computation based on the activation input and a value stored in the storage unit.

6. The method of claim 5, wherein the calculating comprises multiplying.

7. The method of claim 1, further comprising precharging the output node in response to an enable signal.

8. The method of claim 7, further comprising generating a pulse in response to a change in the enable signal.

9. The method of claim 1, wherein the unit stores a plurality of filter weights selectable based on a selection signal, and further comprising precharging the output node in response to a change in the selection signal.

10. The method of claim 1, wherein the cells comprise static random access memory, SRAM, cells and/or ternary content addressable memory, TCAM, cells.

11. A memory device, comprising:

the precharge circuit is configured to precharge an output node of a cell of the memory device based on an activation input of the cell.

12. The memory device of claim 11, wherein the precharge circuit precharges the output node when the activation input has a first logic level.

13. The memory device of claim 11, wherein the precharge circuit comprises a transistor configured to couple the output node to a power supply rail.

14. The memory device of claim 13, wherein the transistor comprises a PMOS transistor.

15. The storage device of claim 11, wherein the storage device is a memory-integrated CIM device, and the unit includes a storage unit and a computing circuit configured to perform a calculation based on the activation input and a value stored in the storage unit.

16. The storage device of claim 15, wherein the computation comprises multiplication.

17. The memory device of claim 11, wherein the precharge circuit is configured to precharge the output node in response to an enable signal.

18. The memory device of claim 11, wherein the precharge circuit comprises a pulse generator.

19. The memory device of claim 11, wherein the unit stores a plurality of filter weights selectable based on a selection signal, and the precharge circuit is configured to precharge the output node in response to a change in the selection signal.

20. The memory device of claim 11, wherein the cells comprise static random access memory, SRAM, cells and/or ternary content addressable memory, TCAM, cells.

21. The memory device of claim 11, wherein the memory device comprises a precharge circuit, the precharge circuit comprising:

precharge logic responsive to the activation input having a first logic level or responsive to a pulse signal, generating a control signal for controlling a precharge device to precharge the output node;

and the precharge device is used for receiving a control signal and precharging the output node under the control of the control signal.

22. The memory device of claim 11, wherein the pulse signal is generated in response to an enable signal EN or in response to a change in a selection signal, wherein the selection signal is used to select a filter weight.

23. The storage device of claim 22, further comprising: a demultiplexer for providing the activation input to a multiplication path corresponding to the filter weight selected by the selection signal.