CN101303681A - Dynamic Reconfiguration of PCI Express Links - Google Patents

Abstract

A method and circuitry for dynamically reconfiguring the links of a PCI Express bus. A computer system has been initially configured with PCI Express bus links to various endpoints, using the scaling features of the PCI Express standard. During operation of the computer system, the status of the endpoints is detected and unused links (or unused portions of links) are rerouted to other endpoints.

Description

Dynamic Reconfiguration of PCI Express Links

This application is a divisional application of a Chinese patent application with the application number 200410090715.7, the application date being November 8, 2004, and the invention title being "Dynamic Reconfiguration of PCI Express Links".

technical field

The present invention relates to computer systems, and more particularly to bus connections for computer systems.

Background technique

The components of a computer, including its processor, chipset, cache memory, memory, expansion cards, and storage devices, communicate with each other through one or more "buses". In general computer terms, a "bus" is a pathway through which information flows between two or more devices. A bus usually has access points, or places where devices can be connected to the bus. Once connected, devices on the bus can send and receive information to and from other devices.

Today's personal computers tend to have at least four buses. Each bus is further removed from the processor in some way; each bus is connected to the bus above it.

The processor bus is the highest level bus and is used by the chipset to send information to and from the processor. The cache bus (sometimes called the backside bus) is used to access system cache memory. The memory bus connects the memory subsystem with the chipset and processor. In many systems, the processor and memory buses are the same bus and are collectively referred to as the front side bus or system bus.

A local I/O (input/output) bus connects external devices to the memory, chipset, and processor. Graphics cards, disk storage devices, and network interface cards typically use this bus. The two most common local I/O buses are the VESA Local Bus (VLB) and the Peripheral Component Interconnect (PCI) bus. The Industry Standard Architecture (ISA) I/O bus can also be used for slow peripherals such as mice, modems, and low-speed audio and networking devices.

The current generation of the PCI bus is known as the PCI Express bus. This bus is a high bandwidth serial bus that maintains software compatibility with existing PCI devices.

Contents of the invention

One aspect of the present invention resides in a method of reconfiguring a PCI Express bus link. The status of bus endpoints is detected, such as whether the endpoint is occupied and how much bandwidth the endpoint requires. Based on this detection, all or a portion of links with unused bandwidth can be switched to another endpoint.

For example, all paths of links routed to unoccupied endpoints may be rerouted to occupied endpoints. Or as another example, one or more lanes of a link routed to an endpoint that requires less bandwidth than the link provides may be switched to an endpoint that requires more bandwidth.

The advantage of the present invention is: it helps to overcome the bandwidth limitation of PCI Express bus. Dynamic reconfiguration of PCI Express lanes allows unused bandwidth to be switched to other devices on the bus.

Description of drawings

A more complete understanding of the present embodiments and advantages may be obtained from the following description taken in conjunction with the accompanying drawings, in which like reference numerals indicate like features, and in which:

Fig. 1 illustrates various internal units of an information handling system according to the present invention.

FIG. 2 illustrates a portion of the system of FIG. 1 and further illustrates a first example of reconfiguring links.

Figure 3 illustrates a second example of reconfiguring links.

Figure 4 illustrates a third example of reconfiguring links.

Detailed ways

FIG. 1 illustrates various internal units of an information handling system 100 in accordance with the present invention. As will be explained below, the system 100 has a PCI Express bus 17 and additional circuitry 19 for dynamically reconfiguring one or more links 17b of said bus. The PCIExpress bus 17 connects peripheral components in a conventional manner, but is enhanced so that it can detect the status of endpoint 17c and reroute the bandwidth of that endpoint if it is not needed.

In the embodiment of FIG. 1, system 100 is represented by a personal computer system, but could also be some other type of information handling system, such as a server, workstation or embedded system. For the purposes of this disclosure, an information handling system may include a system that can compute, classify, process, send, receive, retrieve, initiate, switch, store, display, declare, detect, record, reproduce, process, or utilize business, scientific, control or Any means or collection of means of information, intelligence or data in any form for any other purpose. For example, an information handling system may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU), hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices, and various input and output (I/O) devices, such as keyboards, mice, and video display. The information handling system may also include one or more buses operable to carry communications between the various hardware components.

CPU 10 may be any central processing unit. A representative example of CPU 10 is the processor from the Pentium family, which is available from Intel Corporation. For purposes of the present invention, the CPU 10 is at least programmed to execute an operating system with BIOS (Basic Input/Output System) programming.

Host bridge 11 (often referred to as north bridge) is a chip (or part of a chipset) that connects CPU 10 with endpoints 12, memory 13 and with PCI Express bus 17. The type of endpoint 12 connected to the host bridge 11 depends on the application. For example, if system 100 is a desktop computer, endpoints 12 are typically graphics adapters, HDDs (via a Serial ATA link), and local I/O (via a USB link). For servers, endpoints 12 are typically GbE (Gigabit Ethernet) and IBE devices and additional bridge devices.

The communication between the CPU 10 and the host bridge 11 is realized via the front side bus 14.

The PCI Express bus 17 includes a switch fabric 17a and links 17b by means of which a number of PCI endpoints 45 can be connected. The switch fabric 17a provides output from the host bridge 11 to the link 17b and provides link extension.

"Link scaling" refers to allocating the available bandwidth of the PCI Express bus 17 such that a predetermined number of links 17b are physically routed to endpoints 18, each of which has a the size of. Each link 17b includes one or more paths. A link with a single via (referred to as having x1 width) has two low-voltage differential pairs; the link is duplex in series between two devices. Data transfer between the two devices occurs simultaneously in both directions. Scalable performance through wider link widths (x1, x2, x4, x8, x16, x32). Links are expanded symmetrically and have the same number of lanes in each direction.

PCI endpoint 18 may be a peripheral device or chip, physically connected using a card slot or other connection mechanism. The particular endpoint 45 connected to the PCI Express bus 17 depends on the type of application of the system 100. Representative examples of PCI endpoints 18 for desktop computer systems are mobile docking adapters, Ethernet adapters, and other add-on devices. For server platforms, endpoint 45 may be a Gigabit Ethernet connection with additional switching capabilities for I/O and cluster interconnect. For a communication platform, endpoint 18 may be a cable card.

In the conventional PCI Express bus 17, the switching structure 17a is a logical element implemented as an independent component or as a part of the host bridge 11. As explained below, in the present invention, the PCI Express bus 17 operates in conjunction with additional switching and control circuitry 19. This circuit 19 detects the status of the endpoints 45 and is able to switch the link from one endpoint to the other.

FIG. 2 is a partial view of system 100 and illustrates dynamic reconfiguration of PCI Express link 17b in accordance with the present invention. Each link 17b is shown as two pairs of signals - a sending pair and a receiving pair. The sending pair is identified with the T symbol, and the receiving pair is identified with the R symbol.

Slots 23 and 24 are designed to connect card-type terminals 45 . Although only two slots are shown, many slot configurations are possible depending on the required link size (x1, x4, etc.). Slots 23 and 24 represent physical locations, typically within the computer enclosure of system 100, where cards for various I/O devices may be installed. In other embodiments, system 100 may have one or more chip connections in addition to, or instead of, slot connections. In general terms, the term "endpoint connection" may be used collectively for connections involving chips, cards, or any other type of endpoint.

In the example of FIG. 1 , the slots 23 are arranged according to the link width of a×4 (link A). The slots 24 are arranged in accordance with a x 4 link width (link B).

Reconfiguration is accomplished using switches 25 and 26 and link configuration controller 27 . It should be understood that Figure 2 is an example and that many different variations of the switching and control circuitry are possible, as well as the number of links, slots and switches, and the various link widths.

The link configuration controller 27 detects whether the slots 23 and 24 are occupied (in use). Because the PCI bus 40 allows slots to be "hot plugged" and "hot swapped," this detection is dynamic in the sense that the controller 27 detects the event immediately whenever a device is installed or removed from a slot 23 or 24 .

The link configuration controller 27 can be implemented by a programmable logic device, and can be an independent logic circuit or can be integrated with other system logic. For example, a link configuration controller may be integrated into host bridge 20 .

The controller 27 sends a signal to the switches 25 and 26 if the state of the slot (occupied or unoccupied) changes. The switches 25 and 26 can be realized by high-speed switching devices. As with controller 27 , switches 25 and 26 may be integrated with other circuitry, such as with controller 27 and/or with host bridge 20 .

In the example of FIG. 2, link B has switch 25 on its transmit path and switch 26 on its receive path. Both switches 25 and 26 are operable to switch link B to either slot 23 or slot 24 . If link B is switched to slot 23, then slot 23 receives the x8 link. If link B is switched to slot 24, then slot 24 receives the x4 link. It is assumed that appropriate physical connections have been made between switches 25 and 26 and slot 23 to enable switching between alternative channels.

In the example shown, slot 23 is occupied and slot 24 is unoccupied. This state is detected by the controller 27 which has set the switches 25 and 26 to switch all links B to slot 23 .

Figure 3 illustrates another example of the operation of the present invention. In this example, both slots 33 and 34 are occupied. The system has been configured with three x4 links. Link A is an x4 link and is routed to slot 33 . Link B is also a x4 link and is routed to slot B. Link C is a x4 link and is routed to switches 35 and 36, making it a "switchable" link.

Controller 27 has detected that both slots 33 and 34 are occupied, and has also detected that slot 33 requires an x8 link and slot 34 requires only an x4 link. In response, controller 27 has delivered control signals to switches 35 and 36, such that link C is routed to slot 33, making it an x8 slot. For this example, assume that the cards occupying slots 33 and 34 have some means for notifying controller 27 (either directly or through the operating system of system 100) of their bandwidth requirements.

Figure 4 illustrates a third example where a switch is used to reconfigure the link to the endpoint such that only a portion of the link is rerouted. In the example of FIG. 4, the existing configurations of slots 43 and 44 are x4 and x8, respectively. However, the x8 endpoint has been set in slot 43 and the x4 endpoint has been set in slot 44 . Controller 27 has detected the status and bandwidth requirements of the two slots, and has operated switches 45 and 46 such that a portion of link B is rerouted to slot 43 . In a variation on this example, slot 44 may be unoccupied and link B is split into x4 lanes routed to slot 43 and x4 lanes routed to other endpoints.

The examples described above achieve "reconfiguration" when they reroute existing links, ie links that are already physically routed to various endpoints on the bus. In the absence of the present invention, the PCI Express bus tends to operate in such a way that whatever link configuration is established when system 100 is initialized. Furthermore, the methods and circuits of the above examples are "dynamic" in the sense that state detection and switching occurs while the system 100 is being powered on for operation (during startup) and while the operating system is running. Thus, state detection has the real-time (current) state of the endpoint. The detection and switching of the present invention operate on the link that has been pre-extended according to the expansion capability of the PCI Express bus. It is dynamic reconfiguration as compared to static configuration for scaling.

In the above example, the controller 27 detects the status of the slots and delivers control signals to the configuration switches. In other embodiments, one or more of these functions may be performed by the operating system of system 100, such as by its BIOS. That is, the BIOS can be programmed to detect the status of its slots on the PCI Express bus 40, and/or switch lanes in response to the status. Thus, in various embodiments, the detection and switching functions of the present invention may be hardware or software controlled.

Reconfiguration is still very useful without the "dynamic" detection aspect of the present invention. In other words, there may be situations when it is desirable to manually reroute existing PCI Express bus links. For example, within a chassis with x4 links, cards requiring x8 links can physically fit in the slots. The x8 cards can be switched with x4 cards and their links rerouted.

Claims (22)

1, a kind of method that reconfigures the PCI Express bus links of information handling system, described link is routed to the end points on the bus, may further comprise the steps:

Detect step, detect the state of one or more end points; And

Switch step according to the result who detects step, switches to other end points more than one with all links from an end points.

2, the method for claim 1, wherein detected state and to switch end points be when occurring in system and switching on for operation and operating system when moving.

3, the method for claim 1, wherein said detection step are that whether occupied being used for carried out by detecting end points.

4, method as claimed in claim 3, wherein said switch step is carried out by link is switched to one or more occupied end points from unappropriated end points.

5, the method for claim 1, wherein said detection step are to carry out by the bandwidth demand that detection is installed in the device on the occupied end points.

6, the method for claim 1, wherein said switch step adopt the switch beyond the PCI Express bus switch structure to carry out.

7, the method for claim 1, wherein said information handling system has operating system, and the use of described detection step is carried out for the circuit of carrying out the setting of described detection step.

8, the method for claim 1, wherein said information handling system has operating system, and described detection step uses described operating system to carry out.

9, the method for claim 1, wherein said information handling system is operated during described detection step and switch step.

10, a kind of circuit that reconfigures the PCI Express bus links of information handling system, described link is routed to the end points on the bus, comprising:

Controller is used to detect the state of one or more end points; And

Switch is associated with a link at least, and response comes from the signal of controller, can operate so that all links are switched to other end points more than one from an end points.

11. circuit as claimed in claim 10, wherein when system switches on for operation and operating system when moving, described controller detected state and described switch handoff links.

12, circuit as claimed in claim 10, whether wherein said controller detects end points occupied.

13, circuit as claimed in claim 12 wherein can be operated described switch, so that link is switched to one or more occupied end points from unappropriated end points.

14, circuit as claimed in claim 10, wherein said controller detects the bandwidth demand of the device that is installed in occupied end points.

15, circuit as claimed in claim 10, wherein said controller are the controllers beyond the PCI Express bus switch structure.

16, circuit as claimed in claim 10, wherein said information handling system has host bridge, and wherein described controller is integrated in the described host bridge.

17, circuit as claimed in claim 10 wherein will come from the described switch of signal guide of described controller.

18, circuit as claimed in claim 10 wherein makes the signal that the comes from described controller operating system by information handling system.

19, a kind of information handling system comprises:

CPU (central processing unit);

Storer is used to store the executable program of CPU (central processing unit);

PCI Express bus is used for the I/O end points is linked to each other with described system, and has switching fabric and link from host bridge to described end points;

Wherein host bridge further with bus and CPU and storer be connected; And

Link reconfigures circuit, the link that is used to reconfigure the link of PCI Express bus and is routed to the end points on the described bus, and described link reconfigures circuit and comprises controller, is used to detect the state of one or more described end points; And switch, be associated with at least one link, can operate described switch so that response comes from the signal of described controller, all links are switched to other end points more than one from an end points.

20, system as claimed in claim 19, wherein said controller detects the bandwidth demand of the device that is installed in occupied end points.

21, system as claimed in claim 19, wherein said controller is the controller beyond the PCI Express bus switch structure.

22, system as claimed in claim 19 wherein is integrated into described controller in the host bridge.

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