TWI461921B - Electronic device and method for switching mode of thunderbolt connector thereof - Google Patents

Description

Mode switching method for electronic device and lightning connector thereof

The present invention relates to an electronic device, and more particularly to a mode switching method for a lightning connector in an electronic device.

A single conventional electronic device with a Thunderbolt connecter can only perform one of the Host mode and the end-point device mode in a fixed manner. Conventional technology has no way to dynamically switch between performing host mode and endpoint device mode on the same electronic device.

The invention provides a mode switching method for an electronic device and a lightning connector thereof. The mode switching method of the lightning connector can make the electronic device serve as a host or an endpoint device.

The present invention provides an electronic device. The electronic device includes a core unit, a peripheral device, a lightning (hereinafter referred to as Thunderbolt) connector, a Thunderbolt controller unit, a first switching circuit, and a second switching circuit. The core unit has a first high-speed Peripheral Component Interconnect Express (PCIE) connection end and a second PCIE connection end. The peripheral device has a PCIE connection. The Thunderbolt connector is coupled to the Thunderbolt controller unit, wherein the Thunderbolt controller unit has a host mode and an endpoint device mode. The first common end of the first switching circuit is coupled to the PCIE connection of the peripheral device The first selection end of the first switching circuit is coupled to the first PCIE connection end of the core unit. The first common end of the second switching circuit is coupled to the first PCIE connection end of the Thunderbolt controller unit, the first selection end of the second switching circuit is coupled to the second PCIE connection end of the core unit, and the second switching circuit is The second selection end is coupled to the second selection end of the first switching circuit.

The invention provides a mode switching method of a Thunderbolt connector of an electronic device. The Thunderbolt switching method includes providing a Thunderbolt controller unit having a host mode and an endpoint device mode; when the Thunderbolt controller unit is operating in the host mode, coupling the Thunderbolt controller unit to the core unit of the electronic device, And coupling the peripheral device of the electronic device to the core unit; when the Thunderbolt controller unit operates in the endpoint device mode, coupling the peripheral device to the Thunderbolt controller unit.

Based on the above, the electronic device provided by the present invention can utilize the coupling relationship between the first switching unit and the second switching unit to transform the core unit, the peripheral device, and the Thunderbolt controller unit, so that the electronic device provided by the present invention is provided. Not only as a host, but also as an endpoint device.

The above described features and advantages of the present invention will be more apparent from the following description.

FIG. 1 is a functional block diagram of an electronic device 100 according to an embodiment of the invention. The electronic device 100 includes a core unit 110 and a high speed peripheral device. A Peripheral Component Interconnect Express (hereinafter referred to as PCIE) device 120, a Thunderbolt (hereinafter referred to as Thunderbolt) connector 130, a Thunderbolt controller unit 140, a first switching circuit 150, and a second switching circuit 160 are provided. The core unit 110 has a PCIE connection 111 and a PCIE connection 112. The peripheral device 120 has a PCIE connection end 121. The peripheral device 120 can be any device connected to the PCIE bus, such as a Universal Serial Bus (USB) chip, and a wireless local area network (hereinafter referred to as WLAN). The chip is either an external serial Advanced Technology Attachment (hereinafter referred to as ESATA) chip or the like. The electronic device 100 can be connected to different peripheral devices via different peripheral devices.

The Thunderbolt connector 130 is coupled to the Thunderbolt connector of the Thunderbolt controller unit 140. The Thunderbolt controller unit 140 can be coupled to an external Thunderbolt device via a Thunderbolt connector 130. Among them, the Thunderbolt controller unit 140 can be dynamically set to a host mode and an end-point device. The host mode may be, for example, a router mode, but the host mode in the embodiment of the present invention is not limited to the router mode. When in the host mode, the electronic device 100 is implemented as a Thunderbolt host. When in the endpoint device mode, the electronic device 100 is implemented as an endpoint device.

The first switching circuit 150 and the second switching circuit 160 may be any circuit having a signal path switching function, such as a Q-switch, a multiplexer, a switch, and the like. The first switching circuit 150 can selectively The common terminal 151 is electrically connected to one of the selection terminals 152 and 153, and the second switching circuit 160 can selectively electrically connect the common terminal 161 to one of the selection terminals 162 and 163. The common end 151 of the first switching circuit 150 is coupled to the PCIE connection end 121 of the peripheral device 120. The selection end 152 of the first switching circuit 150 is coupled to the PCIE connection end 111 of the core unit 110. The common terminal 161 of the second switching circuit 160 is coupled to the PCIE connection end 141 of the Thunderbolt controller unit 140. The selection terminal 162 of the second switching circuit 160 is coupled to the PCIE connection terminal 112 of the core unit 110. The selection terminal 163 of the second switching circuit 160 is coupled to the selection terminal 153 of the first switching circuit 150.

In some embodiments, Thunderbolt controller unit 140 can selectively operate in a host mode or an endpoint device mode depending on the user's instructions. In other embodiments, the Thunderbolt controller unit 140 can selectively operate in a host mode or an endpoint device mode depending on whether the core unit 110 is enabled. The means by which the core unit 110 is enabled or disabled may be in any manner, depending on the design requirements of the actual product. For example, when the core unit 110 is in a sleep mode (for example, S3 mode), a hibernation mode (for example, S4 mode), or a shutdown (for example, S5 mode), or when the core unit 110 is in another disabled state mode, The Thunderbolt controller unit 140 can operate in an endpoint device mode. Other embodiments of the present invention are not limited to the above modes except for the above three modes, and may be completed in other modes. For example, in the case where the core unit 110 is in the normal operating mode, the PCIE terminals 111 and 112 of the core unit 110 are disabled (or turned off). At this time, although the core The heart unit 110 is in a normal mode of operation, however for the Thunderbolt controller unit 140, the core unit 110 is disabled. When the PCIE connectors 111 and 112 are disabled, the Thunderbolt controller unit 140 can operate in an endpoint device mode.

The Thunderbolt controller unit 140 may operate in a host mode when the core unit 110 is in a normal mode of operation (eg, S0 mode or a mode in other enabled states). Other embodiments of the present invention are not limited to the above modes except for the above modes, and may be implemented in other modes.

When the Thunderbolt controller unit 140 operates in the host mode, the common terminal 151 of the first switching circuit 150 is coupled to the selection terminal 152 of the first switching circuit 150. The common terminal 161 of the second switching circuit 160 is coupled to the selection terminal 162 of the second switching circuit 160. As a result, the peripheral device 120 and the Thunderbolt controller unit 140 are respectively coupled to the PCIE terminals 111 and 112 of the core unit 110, and the peripheral device 120 and the Thunderbolt controller unit 140 are not coupled to each other. Therefore, the electronic device 100 can function as a Thunderbolt host, the core unit 110 can use the peripheral device 120 through the PCIE connection 111 and the first switching circuit 150, and the core unit 110 can pass through the PCIE connection 112, the second switching circuit 160, and the Thunderbolt controller. Unit 140 uses external endpoint devices (e.g., external hard drives, displays, communication networks, etc.) to which Thunderbolt connector 130 is connected.

When the Thunderbolt controller unit 140 is operating in the endpoint device mode, the core unit 110 may be disabled (eg, entering S3, S4, or S5 mode or The core unit 110 is in a mode of other disabled states, and the core unit 110 may still be in an enabled (or normal operating mode) condition. In other embodiments, the core unit 110, in the case of enabling (or normal operating mode), the Thunderbolt controller unit 140 can also be dynamically set to operate in an endpoint device mode or a host mode.

The common terminal 151 of the first switching circuit 150 is coupled to the selection terminal 153 of the first switching circuit 150 , and the common terminal 161 of the second switching circuit 160 is coupled to the selection terminal 163 of the second switching circuit 160 . As a result, the core unit 110 is not coupled to the peripheral device 120 and the Thunderbolt controller unit 140, and the peripheral device 120 and the Thunderbolt controller unit 140 are coupled to each other. Therefore, the electronic device 100 can function as a Thunderbolt endpoint device. That is, the external Thunderbolt host can use the peripheral device 120 inside the electronic device 100 through the Thunderbolt connector 130, the Thunderbolt controller unit 140, the second switching circuit 160, and the first switching circuit 150. Therefore, the user can use the interface/resource connected by the peripheral device 120 through the Thunderbolt connector 130 and the Thunderbolt controller unit 140, such as a Note Book or other electronic device operating in the Thunderbolt host mode.

FIG. 2 is a functional block diagram of an electronic device 200 according to an embodiment of the invention. The embodiment shown in FIG. 2 can be analogized with reference to the related description of FIG. 1. 2, the electronic device 200 includes a core unit 210, a peripheral device 221, a peripheral device 222, a peripheral device 223, a peripheral device 224, a Thunderbolt connector 230, a Thunderbolt controller unit 240, a first switching circuit 250, and a second switching circuit. 260. Peripheral devices 221~224 It can be any device connected to the PCIE bus, for example, the peripheral device 221 can be a USB host controller chip, the peripheral device 222 can be a WLAN chip, the peripheral device 223 can be an ESATA chip, and the peripheral device 224 can also be Other computer peripherals.

In the embodiment, the core unit 210 includes a central processing unit 211 and a south bridge wafer 212. The central processing unit 211 is coupled to the south bridge wafer 212. The south bridge wafer 212 has eight PCIE terminals (P ₁ ~ P ₈ ). The first switching circuit 250 has a total of eight selection terminals (C ₁ to C ₈ ) and four common terminals (X ₁ to X ₄ ). The second switching circuit 260 has a total of eight selection terminals (A ₁ to A ₈ ) and four common terminals (Y ₁ to Y ₄ ). The PCIE terminals P ₁ -P _{4 of the} south bridge chip 212 are respectively coupled to the selection terminals C ₁ -C _{4 of the} first switching circuit 250. The PCIE terminals P ₅ -P _{8 of the} south bridge chip 212 are respectively coupled to the selection terminals A ₅ -A _{8 of the} second switching circuit 260. The selection terminals C ₅ -C _{8 of the} first switching circuit 250 are respectively coupled to the selection terminals A ₁ -A _{4 of the} second switching circuit 260. The common terminal X _{1 of the} first switching circuit 250 is coupled to the PCIE connection terminal U _{1 of the} peripheral device 221. The common terminal X _{2 of the} first switching circuit 250 is coupled to the PCIE connection terminal U _{2 of the} peripheral device 222. The common terminal X _{3 of the} first switching circuit 250 is coupled to the PCIE connection terminal U _{3 of the} peripheral device 223. The common terminal X _{4 of the} first switching circuit 250 is coupled to the PCIE connection terminal U _{4 of the} peripheral device 224. The common terminals Y ₁ ~Y _{4 of the} second switching circuit 250 are coupled to the PCIE terminals E ₁ -E _{4 of the} Thunderbolt controller unit 220.

When the Thunderbolt controller unit 240 is operated in the host mode, the common terminals X ₁ -X ₄ of the first switching circuit 250 are respectively coupled to the selection terminals C ₁ -C _{4 of the} first switching circuit 250, and the second switching circuit 260 The common terminals Y ₁ ~Y ₄ are respectively coupled to the selection terminals A ₅ -A _{8 of the} second switching circuit 260. In this way, the central processing unit 211 of the core unit 210 can use the peripheral devices 221 to 224 through the south bridge chip 212 and the first switching circuit 250. At the same time, the central processing unit 211 of the core unit 210 can also be coupled to the Thunderbolt controller unit 240 through the south bridge chip 212 and the second switching circuit 260. Therefore, the central processing unit 211 can use the Thunderbolt through the Thunderbolt controller unit 240 operating in the host mode. An external Thunderbolt device (eg, an external hard drive, display, communication network, etc.) to which the connector 230 is coupled.

When the Thunderbolt controller unit 240 is operating in the endpoint device mode, the core unit 210 can be disabled. In another embodiment, when the Thunderbolt controller unit 240 is operating in the endpoint device mode, the core unit 210 may also be in the case of enabling (or normal operating mode). In a state in which the Thunderbolt controller unit 240 operates in the endpoint device mode, the common terminals X ₁ -X ₄ of the first switching circuit 250 are respectively coupled to the selection terminals C ₅ -C _{8 of the} first switching circuit 250, and the second The common terminals Y ₁ -Y ₄ of the switching circuit 260 are coupled to the selection terminals A ₁ -A _{4 of the} second switching circuit 260. As such, the core unit 210 is not coupled to the peripheral devices 221 - 224 and the Thunderbolt controller unit 240 , and the peripheral devices 221 - 224 are coupled to the Thunderbolt controller unit 240 . Therefore, an external Thunderbolt host (for example, a notebook computer) can use the peripheral devices 221 to 224 through the Thunderbolt connector 230, the Thunderbolt controller unit 240, the second switching circuit 260, and the first switching circuit 250.

FIG. 3 is a functional block diagram of an electronic device 300 according to an embodiment of the invention. The embodiment shown in FIG. 3 can refer to the related description of FIG. 1 and FIG. 2. And so on. The electronic device 300 is substantially similar to the electronic device 100, with the difference that the core unit 310 of the electronic device 300 includes a central processing unit (313), and the PCIE device 320 includes a graphics processing unit (Graphics Processing Unit) 322. The central processing unit 313 is coupled to the selection terminal 152 of the first switching unit 150 through the PCIE connection end 311. The central processing unit 313 is coupled to the selection terminal 162 of the second switching unit 160 through the PCIE connection terminal 312. The graphics processing unit 322 is coupled to the common terminal 151 of the first switching unit 150 through the PCIE connection end 321 . The selection terminal 153 of the first switching unit 150 is coupled to the selection terminal 163 of the second switching unit 160.

When the Thunderbolt controller unit 140 is operating in the host mode, the graphics processing unit 322 and the Thunderbolt controller unit 140 are coupled to the central processing unit 313 via the first switching circuit 150 and the second switching unit 160, respectively. The central processing unit 313 can use the mapping processing unit 322 through the first switching unit 150 to accelerate the image processing capability and reduce the burden on the central processing unit 313. At the same time, the central processing unit 313 can also use an external endpoint device (eg, an external hard drive, a display, a communication network, etc.) connected to the Thunderbolt connector 130 through the second switching unit 160 and the Thunderbolt controller unit 140.

When the Thunderbolt controller unit 140 is operating in the endpoint device mode, the central processing unit 313 is disabled (eg, entering the S3, S4, or S5 mode or in a mode that is disabled). In another embodiment, when the Thunderbolt controller unit 140 is operating in the endpoint device mode, the central processing unit 313 can also be maintained in the enabled (or normal mode of operation) condition. In the case where the Thunderbolt controller unit 140 operates in the endpoint device mode, the graphics processing unit 322 is coupled to the lightning controller unit 140 via the first switching circuit 150 and the second switching circuit 160, and the central processing unit 313 is not coupled to The graphics processing unit 322 and the Thunderbolt controller unit 140. As such, an external Thunderbolt host (eg, a notebook computer) can use the graphics processing unit 322 for image processing via the Thunderbolt connector 130 and the Thunderbolt controller unit 140.

FIG. 4 is a functional block diagram of an electronic device 400 according to an embodiment of the invention. The embodiment shown in FIG. 4 can be analogized with reference to the related descriptions of FIGS. 1, 2, and 3. The electronic device 400 is substantially similar to the electronic device 300, with the difference that the core unit 410 of the electronic device 400 includes a central processing unit 413 and a north bridge wafer 414. The north bridge wafer 414 is coupled to the central processing unit 413. The north bridge chip 414 is coupled to the selection terminal 152 of the first switching unit 150 through the PCIE connection terminal 411. The north bridge chip 414 is coupled to the select terminal 162 of the second switching unit 160 through the PCIE terminal 412. The graphics processing unit 322 is coupled to the common terminal 151 of the first switching unit 150 through the PCIE connection end 321 . The selection terminal 153 of the first switching unit 150 is coupled to the selection terminal 163 of the second switching unit 160.

When the Thunderbolt controller unit 140 is operating in the host mode, the graphics processing unit 322 and the Thunderbolt controller unit 140 are coupled to the PCIE connections 411 and 412 of the north bridge wafer 414, respectively. At this time, the central processing unit 413 can use the drawing processing unit 322 through the north bridge wafer 414 and the first switching unit 150 to accelerate the image processing capability and reduce the burden on the central processing unit 413. At the same time, the central processing unit 413 can also An external endpoint device (e.g., an external hard drive, display, communication network, etc.) coupled to the Thunderbolt connector 130 is used through the Northbridge die 414, the second switching unit 160, and the Thunderbolt controller unit 140.

When the Thunderbolt controller unit 140 is operating in the endpoint device mode, the north bridge wafer 414 is disabled. In another embodiment, when the Thunderbolt controller unit 140 is operating in the endpoint device mode, the north bridge wafer 414 can also be maintained in an enabled (or normal mode of operation) condition. In the case where the Thunderbolt controller unit 140 operates in the endpoint device mode, the north bridge wafer 414 is not coupled to the graphics processing unit 322 and the Thunderbolt controller unit 140, and the graphics processing unit 322 and the Thunderbolt controller unit 140 are coupled to each other. As such, an external Thunderbolt host (eg, a notebook computer) can use the graphics processing unit 322 for image processing via the Thunderbolt connector 130 and the Thunderbolt controller unit 140.

FIG. 5 is a functional block diagram of an electronic device 500 according to an embodiment of the invention. The embodiment shown in FIG. 5 can be analogized with reference to the related description of FIGS. 1 to 4. Referring to FIG. 5 , the electronic device 500 includes a core unit 510 , a peripheral device 120 , a Thunderbolt connector 130 , a Thunderbolt controller unit 140 , a first switching unit 150 , a second switching unit 160 , a third switching unit 520 , and a drawing processing unit 530 . . The core unit 510 includes a south bridge wafer 514 and a central processing unit 515, and the south bridge wafer 514 is coupled to the central processing unit 515. The PCIE connection 511 of the south bridge chip 514 is coupled to the selection terminal 152 of the first switching unit 150. The PCIE connection 512 of the south bridge chip 514 is coupled to the selection terminal 162 of the second switching unit 160. The PCIE connection 512 of the south bridge chip 514 is coupled to the selection terminal 166 of the second switching unit 160. The PCIE connection 516 of the central processing unit 515 is coupled to the selection terminal 522 of the third switching unit 520. The common end 161 of the second switching unit 160 is coupled to the PCIE connection 141 of the Thunderbolt controller unit 140. The common end 165 of the second switching unit 160 is coupled to the PCIE connection 142 of the Thunderbolt controller unit 140. The selection terminal 523 of the third switching unit 520 is coupled to the selection terminal 164 of the second switching unit 160. The common terminal 521 of the third switching unit 520 is coupled to the PCIE connection end 531 of the graphics processing unit 530.

When the Thunderbolt controller unit 140 operates in the host mode, the common terminal 151 of the first switching circuit 150 is coupled to the first selection terminal 152 of the first switching circuit 150. The common terminal 161 of the second switching circuit 160 is coupled to the selection terminal 162 of the second switching circuit 160. The common terminal 165 of the second switching circuit 160 is coupled to the selection terminal 166 of the second switching circuit 160. The common terminal 521 of the third switching circuit 520 is coupled to the selection terminal 522 of the third switching circuit 520. Therefore, the central processing unit 515 is coupled to the peripheral device 120 via the south bridge chip 514. The peripheral device 120 can be, for example, a USB host controller chip, a WLAN chip, an ESATA chip, or other low speed peripheral devices. The central processing unit 515 is coupled to the high speed peripheral device such as the graphics processing unit 530 through the PCIE connection terminal 516. In this way, the central processing unit 515 can use the peripheral device 120 through the south bridge chip 514, and can also use the graphics processing unit 530 to enhance the image processing capability and reduce the burden on the central processing unit 515. In addition, the central processing unit 515 can also pass through the south bridge chip 514, the second switching circuit 160, and the Thunderbolt controller unit 140. An external Thunderbolt endpoint device connected to the Thunderbolt connector 130 is used.

When the Thunderbolt controller unit 140 is operating in the endpoint device mode, the central processing unit 513 and the south bridge wafer 514 are disabled. In another embodiment, when the Thunderbolt controller unit 140 is operating in the endpoint device mode, the central processing unit 513 and the south bridge wafer 514 may also be maintained in an enabled (or normal mode of operation) condition. In the case where the Thunderbolt controller unit 140 operates in the endpoint device mode, the common terminal 151 of the first switching circuit 150 is coupled to the selection terminal 153 of the first switching circuit 150. The common terminal 161 of the second switching circuit 160 is coupled to the selection terminal 163 of the second switching circuit 160. The common terminal 165 of the second switching circuit 160 is coupled to the selection terminal 164 of the second switching circuit 160. The common terminal 521 of the third switching circuit 520 is coupled to the selection terminal 523 of the third switching circuit 520. Therefore, the Thunderbolt controller unit 140 is coupled to the peripheral device 120 through the second switching circuit 160 and the first switching unit 150, and the Thunderbolt controller unit 140 is coupled to the mapping processing unit through the second switching circuit 160 and the third switching unit 520. 530. An external Thunderbolt host (e.g., a notebook computer) can use the Thunderbolt connector 130 and the Thunderbolt controller unit 140 to use a high-speed transmission device such as a peripheral device 120 for low-speed transmission such as USB and a graphics processing unit 530.

FIG. 6A is a functional block diagram of the Thunderbolt controller unit 140 illustrated in FIG. 1 according to an embodiment of the invention. The Thunderbolt controller unit 240 of FIG. 2 and the Thunderbolt controller unit 140 of FIGS. 3 through 5 can also be analogized with reference to the description of FIG. 6A. Please refer to 6A, the Thunderbolt controller unit 140 includes a memory 143 and a Thunderbolt control wafer 144. The memory 143 can be any type of memory, such as a non-volatile memory (NVM). For example, the memory 143 can be a read only memory (ROM), a flash memory, an electronic erase rewritable read only memory (EEPROM), a programmable memory (PROM), or Erasable programmable memory (EPROM) and so on. In other embodiments, the memory 143 can also be a volatile memory such as a random access memory (RAM). The volatile memory may be powered by a battery to maintain data stored by the volatile memory.

The memory 143 includes a host mode firmware 143a and an endpoint device mode firmware 143b. The Thunderbolt control chip 144 is coupled to the common terminal 161 of the second switching circuit 160 through the PCIE connection 141. The Thunderbolt control wafer 144 is also coupled to the memory 143 and the Thunderbolt connector 130.

When Thunderbolt control wafer 144 executes host mode firmware 143a, Thunderbolt controller unit 140 operates in host mode. When Thunderbolt control wafer 144 executes endpoint device mode firmware 143b, Thunderbolt controller unit 140 operates in an endpoint device mode. To switch the Thunderbolt controller unit 140 from the host mode to the endpoint device mode, the Thunderbolt control chip 144 must be reset first, and then the Thunderbolt control chip 144 executes the endpoint device mode firmware 143b therein. Similarly, to switch the Thunderbolt controller unit 140 from the endpoint device mode to the host mode, the Thunderbolt control crystal must be reset first. The slice 144, and then the Thunderbolt control wafer 144 executes the host mode firmware 143a therein.

FIG. 6B is a functional block diagram of the Thunderbolt controller unit 140 illustrated in FIG. 1 according to another embodiment of the invention. The Thunderbolt controller unit 240 of FIG. 2 and the Thunderbolt controller unit 140 of FIGS. 3 through 5 can also be analogized with reference to the description of FIG. 6B. Referring to FIG. 6B, the Thunderbolt controller unit 140 includes a Thunderbolt control chip 144, a first memory 145, a second memory 146, and a switch 147. The first memory 145 and the second memory 146 can also be any type of memory, such as non-volatile memory or volatile memory. For example, the first memory 145 and the second memory 146 may be ROM), FLASH memory, EEPROM, PROM, or EPROM, and the like. If the first memory 145 and the second memory 146 are volatile memories, the volatile memory can be continuously powered by the battery to maintain the data stored by the first memory 145 and the second memory 146.

The Thunderbolt control chip 144 is coupled to the common terminal 161 of the second switching circuit 160 through the PCIE connection 141. Thunderbolt control wafer 144 is also coupled to Thunderbolt connector 130. The content of the first memory 145 includes host mode firmware 145a. The content of the second memory 146 includes the endpoint device mode firmware 146a. The selection end 147a of the switch 147 is coupled to the first memory 145, the selection end 147b of the switch 147 is coupled to the second memory 146, and the common end 147c of the switch 147 is coupled to the Thunderbolt control wafer 144.

When the common terminal 147c of the switch 147 is coupled to the selection terminal 147a, the Thunderbolt control wafer 144 is coupled to the first memory 145, so the Thunderbolt control wafer 144 reads and executes the host mode firmware 145a via the switch 147, at which time Thunderbolt control The unit 140 operates in a host mode.

When the common terminal 147c of the switch 147 is coupled to the selection terminal 147b, the Thunderbolt control wafer 144 is coupled to the second memory 146. After resetting the Thunderbolt control wafer 144, the Thunderbolt control wafer 144 reads and executes the endpoint device mode firmware 146a in the second memory 146 via the switch 147, at which time the Thunderbolt controller unit 140 operates in the endpoint device mode.

An electronic device according to another embodiment of the present invention may have two Thunderbolt controller units.

FIG. 7 is a functional block diagram of an electronic device 700 according to an embodiment of the invention. The embodiment shown in FIG. 7 can be analogized with reference to the related descriptions of FIGS. 1 to 5, 6A, and 6B. The electronic device 700 shown in FIG. 7 is substantially similar to the electronic device 200 shown in FIG. 2, except that the drawing processing unit 530 and the third switching circuit 710 and the fourth circuit unit 720 are added, and the Thunderbolt controller unit 240 is replaced by two. Thunderbolt controller units 740 and 770 and memory 790, Thunderbolt connector 230 are replaced with two Thunderbolt connectors 730, 780. The central processing unit 211 has four PCIE terminals T ₁ -T ₄ , and the south bridge wafer 212 has twelve PCIE terminals (P ₁ -P ₁₂ ). The Thunderbolt controller unit 740 has PCIE terminals R ₁ -R ₈ and the Thunderbolt controller unit 770 has PCIE terminals Q ₁ -Q ₈ . The third switching circuit 710 has a selection terminal D ₁ -D ₈ and a common terminal V ₁ -V ₄ , the fourth switching circuit 720 has a selection terminal N ₁ -N ₈ and a common terminal Z ₁ -Z ₄ , and the mapping processing unit 530 has 4 PCIE connectors G ₁ ~ G ₄ .

The selection terminals D ₁ -D _{4 of the} third switching circuit 710 are coupled to the PCIE connection terminals T ₁ -T _{4 of the} central processing unit 211. The selection terminals D ₅ -D _{8 of the} third switching circuit 710 are coupled to the selection terminals N ₅ -N _{8 of the} fourth switching circuit 720. The common terminals V ₁ V V _{4 of the} third switching circuit 710 are coupled to the PCIE terminals G ₁ G G _{4 of the} graphics processing unit 530. The selection terminals N1 N N4 of the fourth switching circuit 720 are coupled to the PCIE connection terminals P ₉ -P _{12 of the} south bridge chip 212. The common terminals Z ₁ -Z _{4 of the} fourth switching circuit 720 are coupled to the PCIE terminals Q ₁ -Q _{4 of the} Thunderbolt controller unit 770. The PCIE terminals R ₁ -R _{4 of the} Thunderbolt controller unit 740 are coupled to the common terminals Y ₁ -Y _{4 of the} second switching circuit 260. The Thunderbolt controller unit 740 is coupled to the Thunderbolt controller unit 770. The Thunderbolt controller unit 740 is coupled to the Thunderbolt connector 730. The Thunderbolt controller unit 770 is coupled to the Thunderbolt connector 780.

Memory 790 can also be any type of memory, such as non-volatile memory or volatile memory. For example, the memory 143 can be a ROM, a FLASH memory, an EEPROM, a PROM, an EPROM, or the like. In other embodiments, if the memory 790 is a volatile memory, the volatile memory can be continuously powered by the battery to maintain the data stored by the volatile memory. In another embodiment, the memory 790 can be analogized with reference to the description of memory 145, memory 146, and switch 147 in FIG. 6B.

The embodiment shown in FIG. 7 can be analogized with reference to the related description of FIG. 2. The Thunderbolt controller unit 740 is coupled to the memory 790. The memory 790 includes a host mode body 791 and an endpoint device mode body 792. When Thunderbolt controller unit 740 reads and executes host mode body 791 within memory 790, Thunderbolt controller unit 740 operates in host mode. When the Thunderbolt controller unit 740 reads and executes the endpoint device mode body 792 within the memory 790, the Thunderbolt controller unit 740 operates in the endpoint device mode. The Thunderbolt controller unit 770 is coupled to the memory 760. The memory 760 includes a host mode body 761 and an endpoint device mode body 762. Similar to the implementation of the Thunderbolt controller unit 740 switching mode of operation, the Thunderbolt controller unit 770 can also dynamically change the mode of operation to host mode or endpoint device mode. The implementation of the Thunderbolt controller unit 770 and the memory 760 can be referred to the relevant description of the Thunderbolt controller unit 740 and the memory 790, and thus will not be described herein.

When the Thunderbolt controller units 740 and 770 operate in the host mode, the common terminals X ₁ -X ₄ of the first switching circuit 250 are coupled to the selection terminals C ₁ -C _{4 of the} first switching circuit 250, respectively. The common terminals Y ₁ -Y ₄ of the second switching circuit 260 are respectively coupled to the selection terminals A ₅ -A _{8 of the} second switching circuit 260. The selection terminals D ₁ -D ₄ of the third switching circuit 710 are respectively coupled to the common terminals V ₁ -V _{4 of the} third switching circuit 710. The selection terminals N ₁ -N ₄ of the fourth switching circuit 720 are respectively coupled to the common terminals Z ₁ -Z _{4 of the} fourth switching circuit 720. In this way, the central processing unit 211 in the core unit 210 can use the peripheral devices 221 to 224 through the south bridge chip 212 and the first switching circuit 250. The central processing unit 211 can use the mapping processing unit 530 through the third switching circuit 710. The central processing unit 211 can pass through the south bridge wafer 212, the second switching circuit 260, and the Thunderbolt controller unit 740 using an external Thunderbolt device coupled to the Thunderbolt connector 730. The central processing unit 211 can also use an external Thunderbolt device coupled to the Thunderbolt connector unit 780 via the south bridge wafer 212, the fourth switching circuit 720, and the Thunderbolt controller unit 770. Therefore, the electronic device 700 can increase the speed of information transmission in the host mode. In addition, since the Thunderbolt controller unit 740 and the Thunderbolt controller unit 770 are coupled to each other, the external Thunderbolt device connected to the Thunderbolt connector 730 and the external Thunderbolt device connected to the Thunderbolt connector 780 can communicate with each other through the Thunderbolt controller unit 740 and 770. Transfer information to increase the speed of information transfer.

When Thunderbolt controller units 740 and 770 operate in the endpoint device mode, central processing unit 211 and/or south bridge wafer 212 may be disabled. In another embodiment, when Thunderbolt controller units 740 and 770 are operating in an endpoint device mode, central processing unit 211 and south bridge wafer 212 may also be in an enabled (or normal mode of operation) condition. In the case where the Thunderbolt controller units 740 and 770 operate in the endpoint device mode, the common terminals X ₁ -X ₄ of the first switching circuit 250 are coupled to the selection terminals C ₅ -C _{8 of the} first switching circuit 250, respectively. The common terminals Y ₁ -Y ₄ of the second switching circuit 260 are respectively coupled to the selection terminals A ₁ -A _{4 of the} second switching circuit 260. The common terminals V ₁ V V ₄ of the third switching circuit 710 are respectively coupled to the selection terminals D ₅ -D _{8 of the} third switching circuit 710. The common terminals Z ₁ -Z ₄ of the fourth switching circuit 720 are respectively coupled to the selection terminals N ₅ -N _{8 of the} fourth switching circuit 720. Therefore, an external Thunderbolt host (for example, a notebook computer) can use the peripheral devices 221 to 224 through the Thunderbolt connector 730, the Thunderbolt controller unit 740, the second switching circuit 260, and the first switching circuit 250. Similarly, the external Thunderbolt host can use the graphics processing unit 530 through the Thunderbolt connector 780, the Thunderbolt controller unit 770, the fourth switching circuit 720, and the third switching circuit 710. Therefore, the external Thunderbolt host can be connected to more peripheral devices in the endpoint device mode. Moreover, the external devices coupled to the Thunderbolt connectors 730 and 780 can still directly transmit information to each other.

FIG. 8 is a functional block diagram of an electronic device 800 in accordance with an embodiment of the present invention. The electronic device 800 is substantially similar to the electronic device 100, but the electronic device 800 further includes a microcontroller (Micro-Controller) 801. The embodiments shown in Figures 1 through 8 can be referred to each other with reference to their related descriptions. Referring to FIG. 8, the microcontroller 801 is coupled to the first switching circuit 150, the second switching circuit 160, the core unit 110, and the Thunderbolt controller unit 140.

When the user wants to operate the electronic device 800 in the host mode, the user can issue a mode switching command to the microcontroller 801 through the operation interface. The microcontroller 801 correspondingly controls the Thunderbolt controller unit 140, the first switching circuit 150, and the second switching circuit 160 according to the mode switching instruction. According to the control of the microcontroller 801, the first switching circuit 150 The selection terminal 152 and the common terminal 151 are coupled to each other, and the second switching circuit 160 couples the selection terminal 162 to the common terminal 161. Also, the microcontroller 801 also controls the operation mode of the Thunderbolt controller unit 140 to switch to the host mode.

When the user wants to operate the electronic device 800 in the endpoint device mode, the user can issue a mode switching command to the microcontroller 801 through the operation interface. The microcontroller 801 correspondingly controls the Thunderbolt controller unit 140, the first switching circuit 150, and the second switching circuit 160 according to the mode switching instruction. According to the control of the microcontroller 801, the selection terminal 153 of the first switching circuit 150 is coupled to the common terminal 151, and the selection terminal 163 of the second switching circuit 160 is coupled to the common terminal 161. Also, the microcontroller 801 also controls the operation mode of the Thunderbolt controller unit 140 to switch to the endpoint device mode. In addition, the microcontroller 801 disables the core unit 110 (e.g., controls the core unit 110 to enter the S3, S4, or S5 mode or a mode that is in other disabled states). In another embodiment, when the Thunderbolt controller unit 140 is operating in the endpoint device mode, the microcontroller 801 controls the core unit 110 to remain in the enabled (or normal mode of operation) condition.

A person skilled in the art can apply the content of the embodiment to the foregoing embodiment shown in FIG. 1 to FIG. 7 according to the teachings of the embodiment. For example, the microcontroller 801 can also be applied to the embodiments illustrated in FIGS. 2, 3, 4, 5, and 7.

9 is a flow chart of a routine 900 of a Thunderbolt mode switching method of an electronic device 100 in accordance with an embodiment of the present invention. Referring to FIG. 1 and FIG. 9, in step S901, a host mode and an endpoint device mode are provided. Thunderbolt controller unit 140. In step S902, it is determined whether the Thunderbolt controller unit 140 is operated in the host mode. If it is determined in step S902 that it is to operate in the host mode, then step S903 is performed, otherwise step S904 is performed (ie, the Thunderbolt controller unit 140 is operated in the endpoint device mode).

In step S903, when the Thunderbolt controller unit 140 is operated in the host mode, the Thunderbolt controller unit 140 is coupled to the core unit 110 of the electronic device 100, and the peripheral device 120 of the electronic device 100 is coupled to the core unit 110. As such, the core unit 110 can use the peripheral device 120 and the external endpoint device to which the Thunderbolt connector 130 is connected.

In step S904, when the Thunderbolt controller unit 140 operates in the endpoint device mode, the Thunderbolt controller unit 140 is not coupled to the core unit 110, the peripheral device 120 is not coupled to the core unit 110, and the peripheral device 120 is It is coupled to the Thunderbolt controller unit 140. As such, an external Thunderbolt host (eg, a notebook computer) can use the peripheral device 120 with the Thunderbolt controller unit 140 via the Thunderbolt connector 130.

FIG. 10 is a flowchart of a procedure 1000 of a Thunderbolt mode switching method of an electronic device according to another embodiment of the present invention. The steps of the program 1000 are substantially the same as the steps of the program 900, with the difference that the step S904 is replaced with the step S1004. More than step S904, step S100 includes disabling the core unit 110 when the Thunderbolt controller unit 140 is operating in the endpoint device mode.

11 is an electronic device according to another embodiment of the present invention. Flowchart of the program 1100 of the Thunderbolt mode switching method. The steps of the program 1100 are substantially the same as the steps of the program 900. The difference is that after the step S903 is completed, the step S1105 is executed again, and after the step S904 is completed, the step S1106 is executed. In step S1105, the Thunderbolt controller unit 140 will execute the host mode firmware included in the memory of the Thunderbolt controller unit 140. In step S1106, the Thunderbolt controller unit 140 will execute the endpoint device mode firmware included in the memory of the Thunderbolt controller unit 140. It is worth mentioning that, in another embodiment not shown, step S904 can also be replaced with step S1004.

FIG. 12 is a flow chart showing a procedure 1200 of a Thunderbolt mode switching method of an electronic device according to another embodiment of the present invention. Steps S901 to S904 in the program 1200 are the same as those in FIG. In the process 1200, after the step S903 is completed, step S1205 is executed to determine whether the original Thunderbolt controller unit 140 is operating in the host mode, that is, whether the original Thunderbolt controller unit 140 executes the host mode firmware. If the result of the determination in the step S1205 is YES, the flow proceeds to a step S1206, and the host mode continues to be executed by the Thunderbolt controller unit 140. If the decision result in the step S1205 is NO, the flow proceeds to a step S1207 to reset the Thunderbolt controller unit 140 and cause the Thunderbolt controller unit 140 to execute the host mode body.

After step S904 is executed, step S1205 is further executed to determine whether the original Thunderbolt controller unit 140 executes the host mode firmware. If the result of the determination in step S1205 is YES, the process proceeds to step S1208. The Thunderbolt controller unit 140 is reset and the Thunderbolt controller unit 140 executes the endpoint device mode body. If the result of the determination in the step S1205 is NO, the process proceeds to a step S1206, and the endpoint device mode body is executed by the Thunderbolt controller unit 140 as it is.

In summary, the electronic device and the Thunderbolt switching method provided by the present invention can utilize the coupling relationship between the selection end and the common end of the first switching circuit and the second switching circuit to operate the Thunderbolt controller unit on the host. Mode or endpoint device mode. Therefore, unlike the conventional Thunderbolt controller, the Thunderbolt controller unit of the electronic device provided by the present invention can be used as an external terminal device as a host, or as an endpoint device used by an external user and a Thunderbolt controller. A peripheral device to which the unit is coupled.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400, 500, 700, 800‧‧‧ electronic devices

110, 210, 310, 410, 510‧‧‧ core units

111, 112, 121, 141, 142, 311, 312, 321, 411, 412, 511 to 513, 516, 531, E ₁ to E ₄ , G ₁ to G ₄ , P ₁ to P ₁₂ , Q ₁ to Q ₄ , R ₁ ~ R ₄ , U ₁ ~ U ₄ ‧‧‧ PCIE connector

120, 221~224, 320‧‧‧ peripheral devices

130, 230, 730, 780‧‧‧Thunderbolt connectors

140, 240, 740, 770‧‧‧Thunderbolt controller unit

143, 760, 790‧‧‧ memory

143a, 145a, 761, 791‧‧‧ host mode firmware

143b, 145b, 762, 792‧‧‧ Endpoint device mode firmware

144‧‧‧Thunderbolt chip

145‧‧‧First memory

146‧‧‧Second memory

147‧‧‧ switch

147a, 147b, 152, 153, 162~164, 166, 522, 523, A ₁ ~ A ₈ , C ₁ ~ C ₈ , D ₁ ~ D ₈ , N ₁ ~ N ₈ ‧ ‧

147c, 151, 161, 165, 521, V ₁ ~ V ₄ , X ₁ ~ X ₄ , Y ₁ ~ Y ₄ , Z ₁ ~ Z ₄ ‧ ‧ common

150, 250‧‧‧ first switching circuit

160, 260‧‧‧ second switching circuit

211, 313, 413, 515‧‧‧ central processing unit

212, 514‧‧‧ South Bridge Wafer

322, 414, 530‧‧‧Drawing Processing Unit

520, 710‧‧‧ third switching circuit

720‧‧‧fourth switching circuit

801‧‧‧Microcontroller

900, 1000, 1100, 1200‧‧‧ procedures

S901~S904, S1004, S1105, S1106, S1205~S1208‧‧‧ steps

FIG. 1 is a functional block diagram of an electronic device according to an embodiment of the invention.

2 is a functional block diagram of an electronic device in accordance with an embodiment of the invention.

FIG. 3 is a functional block diagram of an electronic device according to an embodiment of the invention.

4 is a functional block diagram of an electronic device in accordance with an embodiment of the invention.

FIG. 5 is a functional block diagram of an electronic device according to an embodiment of the invention.

6A and 6B are block diagrams showing the function of the Thunderbolt controller unit shown in FIG. 1 according to an embodiment of the invention.

FIG. 7 is a functional block diagram of an electronic device according to an embodiment of the invention.

FIG. 8 is a functional block diagram of an electronic device according to an embodiment of the invention.

FIG. 9 is a flowchart of a Thunderbolt mode switching method of an electronic device according to an embodiment of the invention.

FIG. 10 is a flowchart of a Thunderbolt mode switching method of an electronic device according to an embodiment of the invention.

FIG. 11 is a flowchart of a Thunderbolt mode switching method of an electronic device according to an embodiment of the invention.

FIG. 12 is a flowchart of a Thunderbolt mode switching method of an electronic device according to an embodiment of the invention.

100‧‧‧Electronic devices

110‧‧‧ core unit

111, 112, 121, 141‧‧‧ PCIE connectors

120‧‧‧ peripheral devices

130‧‧‧Lightning connector

140‧‧‧Lightning controller unit

152, 153, 162, 163‧‧‧Selection

151, 161‧‧Common

150‧‧‧First switching circuit

160‧‧‧Second switching circuit

Claims (15)

An electronic device comprising: a core unit having a first high-speed Peripheral Component Interconnection Express (PCIE) connection end and a second PCIE connection end; a peripheral device having a PCIE connection end; a lightning a lightning controller unit coupled to the lightning connector, wherein the lightning controller unit has a host mode and an endpoint device mode; a first switching circuit having a first common terminal coupled to the periphery a first selection end of the first switching circuit is coupled to the first PCIE connection end of the core unit; and a second switching circuit, a first common end of the device is coupled to the lightning a first PCIE connection end of the controller unit, a first selection end of the second switching circuit is coupled to the second PCIE connection end of the core unit, and a second selection end of the second switching circuit is coupled And a second selection end of the first switching circuit. The electronic device of claim 1, wherein the first common end of the first switching circuit is coupled to the first one of the first switching circuit when the lightning controller unit is operated in the host mode a first common end of the second switching circuit coupled to the first selection end of the second switching circuit; and the first switching circuit when the lightning controller unit operates in the terminal device mode The first common end is coupled to the first portion of the first switching circuit The second common end of the second switching circuit is coupled to the second selection end of the second switching circuit. The electronic device of claim 1, wherein the core unit comprises a central processing unit, the peripheral device comprises a graphics processing unit; and when the lightning controller unit is operated in the host mode, the graphics processing unit is The first switching circuit is coupled to the central processing unit, and the lightning controller unit is coupled to the central processing unit via the second switching circuit; and when the lightning controller unit is operating in the endpoint device mode, The graphics processing unit is coupled to the lightning controller unit via the first switching circuit and the second switching circuit. The electronic device of claim 1, wherein the core unit comprises a north bridge chip, the peripheral device comprises a graphics processing unit; and when the lightning controller unit is operated in the host mode, the graphics processing unit a first switching circuit coupled to the north bridge chip, the lightning controller unit coupled to the north bridge wafer via the second switching circuit; and the graphics processing unit when the lightning controller unit is operating in the endpoint device mode The first switching circuit and the second switching circuit are coupled to the lightning controller unit. The electronic device of claim 1, wherein the core unit comprises a south bridge chip, and the first selection end of the first switching circuit is coupled to the south bridge wafer; when the lightning controller unit is operated In the host mode, the peripheral device is coupled to the south bridge chip via the first switching circuit, and the lightning controller unit is coupled to the south bridge wafer via the second switching circuit; and when the lightning controller unit is operated at the end Point device mode The peripheral device is coupled to the lightning controller unit via the first switching circuit and the second switching circuit. The electronic device of claim 5, wherein the core unit further comprises a central processing unit, and the electronic device further comprises: a graphics processing unit having a PCIE connection; and a third switching circuit A first common end is coupled to the PCIE connection end of the graphics processing unit, a first selection end of the third switching circuit is coupled to the central processing unit, and a second selection end of the third switching circuit is coupled a second selection end of the second switching circuit; wherein a second common end of the second switching circuit is coupled to a second PCIE connection end of the lightning controller unit; when the lightning controller unit is operated In the host mode, the graphics processing unit is coupled to the central processing unit via the third switching circuit; and when the lightning controller unit is operating in the endpoint device mode, the graphics processing unit is coupled to the third switching circuit The second switching circuit is coupled to the lightning controller unit. The electronic device of claim 1, wherein the lightning controller unit comprises: a memory including a host mode firmware and an end device mode firmware; and a lightning control chip coupled to the The first common end of the second switching circuit and the memory; wherein when the lightning control chip executes the host mode firmware, the lightning controller unit operates in the host mode; and when the lightning control chip When the endpoint device mode firmware is executed, the lightning controller unit operates in the endpoint device mode. The electronic device of claim 7, wherein the lightning control chip is reset to execute the host mode firmware to switch from the endpoint device mode to the host mode; and the lightning control chip is reset The endpoint device mode firmware is then executed to switch from the host mode to the endpoint device mode. The electronic device of claim 1, wherein the lightning controller unit comprises: a lightning control chip coupled to the first common end of the second switching circuit; a first memory, the content of which comprises a host mode firmware; a second memory, the content of which includes an endpoint device mode firmware; and a switch, a first selection end of the switch coupled to the first memory, a second selection of the switch The end is coupled to the second memory, a common end of the switch is coupled to the lightning control chip; wherein the lightning controller unit operates when the lightning control chip reads and executes the host mode firmware via the switch In the host mode; and when the lightning control chip reads and executes the endpoint device mode firmware via the switch, the lightning controller unit operates in the endpoint device mode. The electronic device of claim 1, wherein the peripheral device comprises a universal serial bus, a wireless area network chip or an external serial advanced technology attached wafer. A mode switching method for a lightning connector of an electronic device, comprising: providing a lightning controller unit, wherein the lightning controller unit has a host mode and an endpoint device mode; when the lightning controller unit operates in the host mode, Coupling the lightning controller unit to a core unit of the electronic device, and coupling a peripheral device of the electronic device to the core unit; and when the lightning controller unit operates in the endpoint device mode, The peripheral device is coupled to the lightning controller unit. The method for switching a lightning connector of an electronic device according to claim 11, wherein the core unit is disabled when the lightning controller unit operates in the endpoint device mode. The method for switching a lightning connector of an electronic device according to claim 11, further comprising: when the lightning controller unit executes a host mode firmware, the lightning controller unit operates in the host mode; When the lightning controller unit executes the endpoint device mode firmware, the lightning controller unit operates in the endpoint device mode. The method for switching a lightning connector of an electronic device according to claim 13 , further comprising: resetting the lightning controller unit and executing the host mode firmware by the lightning controller unit to obtain the terminal device Switching mode to this host mode; The lightning controller unit is reset and the endpoint device mode firmware is executed by the lightning controller unit to switch from the host mode to the endpoint device mode. The method for switching a lightning connector of an electronic device according to claim 11, wherein the peripheral device comprises a drawing processing unit, a universal serial bus, a wireless area network chip or an external serial The stage technology attaches a wafer or any PCIE device.